247 lines
8.6 KiB
Systemverilog
247 lines
8.6 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "../core/defines.sv"
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`include "../debug/jtag_def.sv"
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// tinyriscv soc顶层模块
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module tinyriscv_soc_top(
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input wire clk, // 时钟引脚
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input wire rst_ext_ni, // 复位引脚，低电平有效
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output wire halted_ind_pin, // jtag是否已经halt住CPU，高电平有效
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output wire uart_tx_pin, // UART发送引脚
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input wire uart_rx_pin, // UART接收引脚
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inout wire[1:0] gpio_pins, // GPIO引脚，1bit代表一个GPIO
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input wire jtag_TCK_pin, // JTAG TCK引脚
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input wire jtag_TMS_pin, // JTAG TMS引脚
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input wire jtag_TDI_pin, // JTAG TDI引脚
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output wire jtag_TDO_pin // JTAG TDO引脚
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);
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localparam int MASTERS = 3; // Number of master ports
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localparam int SLAVES = 3; // Number of slave ports
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// masters
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localparam int CoreD = 0;
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localparam int JtagHost = 1;
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localparam int CoreI = 2;
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// slaves
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localparam int Rom = 0;
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localparam int Ram = 1;
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localparam int JtagDevice = 2;
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wire master_req [MASTERS];
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wire master_gnt [MASTERS];
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wire master_rvalid [MASTERS];
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wire [31:0] master_addr [MASTERS];
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wire master_we [MASTERS];
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wire [ 3:0] master_be [MASTERS];
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wire [31:0] master_rdata [MASTERS];
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wire [31:0] master_wdata [MASTERS];
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wire slave_req [SLAVES];
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wire slave_gnt [SLAVES];
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wire slave_rvalid [SLAVES];
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wire [31:0] slave_addr [SLAVES];
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wire slave_we [SLAVES];
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wire [ 3:0] slave_be [SLAVES];
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wire [31:0] slave_rdata [SLAVES];
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wire [31:0] slave_wdata [SLAVES];
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wire [31:0] slave_addr_mask [SLAVES];
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wire [31:0] slave_addr_base [SLAVES];
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`ifdef VERILATOR
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wire sim_jtag_tck;
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wire sim_jtag_tms;
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wire sim_jtag_tdi;
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wire sim_jtag_trstn;
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wire sim_jtag_tdo;
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wire [31:0] sim_jtag_exit;
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`endif
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wire ndmreset;
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wire ndmreset_n;
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wire debug_req;
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wire core_halted;
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assign halted_ind_pin = core_halted;
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tinyriscv_core #(
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.DEBUG_HALT_ADDR(`DEBUG_ADDR_BASE + `HaltAddress),
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.DEBUG_EXCEPTION_ADDR(`DEBUG_ADDR_BASE + `ExceptionAddress)
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) u_tinyriscv_core (
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.clk (clk),
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.rst_n (ndmreset_n),
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.instr_req_o (master_req[CoreI]),
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.instr_gnt_i (master_gnt[CoreI]),
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.instr_rvalid_i (master_rvalid[CoreI]),
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.instr_addr_o (master_addr[CoreI]),
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.instr_rdata_i (master_rdata[CoreI]),
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.instr_err_i (1'b0),
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.data_req_o (master_req[CoreD]),
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.data_gnt_i (master_gnt[CoreD]),
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.data_rvalid_i (master_rvalid[CoreD]),
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.data_we_o (master_we[CoreD]),
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.data_be_o (master_be[CoreD]),
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.data_addr_o (master_addr[CoreD]),
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.data_wdata_o (master_wdata[CoreD]),
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.data_rdata_i (master_rdata[CoreD]),
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.data_err_i (1'b0),
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.irq_software_i (1'b0),
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.irq_timer_i (1'b0),
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.irq_external_i (1'b0),
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.irq_fast_i (15'b0),
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.debug_req_i (debug_req)
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);
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assign slave_addr_mask[Rom] = `ROM_ADDR_MASK;
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assign slave_addr_base[Rom] = `ROM_ADDR_BASE;
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// 指令存储器
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rom #(
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.DP(`ROM_DEPTH)
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) u_rom (
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.clk (clk),
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.rst_n (ndmreset_n),
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.addr_i (slave_addr[Rom]),
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.data_i (slave_wdata[Rom]),
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.sel_i (slave_be[Rom]),
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.we_i (slave_we[Rom]),
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.data_o (slave_rdata[Rom])
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);
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assign slave_addr_mask[Ram] = `RAM_ADDR_MASK;
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assign slave_addr_base[Ram] = `RAM_ADDR_BASE;
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// 数据存储器
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ram #(
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.DP(`RAM_DEPTH)
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) u_ram (
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.clk (clk),
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.rst_n (ndmreset_n),
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.addr_i (slave_addr[Ram]),
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.data_i (slave_wdata[Ram]),
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.sel_i (slave_be[Ram]),
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.we_i (slave_we[Ram]),
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.data_o (slave_rdata[Ram])
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);
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obi_interconnect #(
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.MASTERS(MASTERS),
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.SLAVES(SLAVES)
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) bus (
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.clk_i (clk),
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.rst_ni (ndmreset_n),
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.master_req_i (master_req),
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.master_gnt_o (master_gnt),
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.master_rvalid_o (master_rvalid),
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.master_we_i (master_we),
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.master_be_i (master_be),
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.master_addr_i (master_addr),
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.master_wdata_i (master_wdata),
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.master_rdata_o (master_rdata),
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.slave_addr_mask_i (slave_addr_mask),
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.slave_addr_base_i (slave_addr_base),
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.slave_req_o (slave_req),
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.slave_gnt_i (slave_gnt),
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.slave_rvalid_i (slave_rvalid),
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.slave_we_o (slave_we),
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.slave_be_o (slave_be),
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.slave_addr_o (slave_addr),
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.slave_wdata_o (slave_wdata),
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.slave_rdata_i (slave_rdata)
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);
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rst_gen #(
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.RESET_FIFO_DEPTH(5)
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) u_rst (
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.clk (clk),
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.rst_ni (rst_ext_ni & (~ndmreset)),
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.rst_no (ndmreset_n)
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);
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assign slave_addr_mask[JtagDevice] = `DEBUG_ADDR_MASK;
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assign slave_addr_base[JtagDevice] = `DEBUG_ADDR_BASE;
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// JTAG module
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jtag_top #(
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) u_jtag_top (
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.clk_i (clk),
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.rst_ni (rst_ext_ni),
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.debug_req_o (debug_req),
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.ndmreset_o (ndmreset),
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.halted_o (core_halted),
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.jtag_tck_i (sim_jtag_tck),
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.jtag_tdi_i (sim_jtag_tdi),
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.jtag_tms_i (sim_jtag_tms),
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.jtag_trst_ni (sim_jtag_trstn),
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.jtag_tdo_o (sim_jtag_tdo),
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.master_req_o (master_req[JtagHost]),
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.master_gnt_i (master_gnt[JtagHost]),
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.master_rvalid_i (master_rvalid[JtagHost]),
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.master_we_o (master_we[JtagHost]),
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.master_be_o (master_be[JtagHost]),
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.master_addr_o (master_addr[JtagHost]),
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.master_wdata_o (master_wdata[JtagHost]),
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.master_rdata_i (master_rdata[JtagHost]),
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.master_err_i (1'b0),
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.slave_req_i (slave_req[JtagDevice]),
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.slave_we_i (slave_we[JtagDevice]),
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.slave_addr_i (slave_addr[JtagDevice]),
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.slave_be_i (slave_be[JtagDevice]),
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.slave_wdata_i (slave_wdata[JtagDevice]),
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.slave_rdata_o (slave_rdata[JtagDevice])
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);
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`ifdef VERILATOR
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sim_jtag #(
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.TICK_DELAY(1),
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.PORT(9999)
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) u_sim_jtag (
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.clock ( clk ),
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.reset ( ~rst_ext_ni ),
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.enable ( 1'b1 ),
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.init_done ( rst_ext_ni ),
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.jtag_TCK ( sim_jtag_tck ),
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.jtag_TMS ( sim_jtag_tms ),
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.jtag_TDI ( sim_jtag_tdi ),
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.jtag_TRSTn ( sim_jtag_trstn ),
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.jtag_TDO_data ( sim_jtag_tdo ),
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.jtag_TDO_driven ( 1'b1 ),
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.exit ( sim_jtag_exit )
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);
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always @ (*) begin
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if (sim_jtag_exit) begin
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$display("jtag exit...");
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$finish(2);
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end
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end
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`endif
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endmodule
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