tinyriscv/rtl/core
liangkangnan fd2c981317 temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-07-09 15:18:09 +08:00
..
bpu.sv rtl: add static branch predict unit 2021-06-11 09:44:26 +08:00
csr.sv debug: add hw breakpoint support 2021-05-14 14:37:47 +08:00
csr_reg.sv temp commit 2021-07-09 15:18:09 +08:00
defines.sv temp commit 2021-05-25 11:45:53 +08:00
divider.sv temp commit 2021-04-30 18:27:30 +08:00
exception.sv temp commit 2021-05-25 09:41:00 +08:00
exu.sv rtl: add config for branch predictor 2021-06-28 11:31:04 +08:00
exu_alu_datapath.sv temp commit 2021-03-31 18:00:19 +08:00
exu_commit.sv temp commit 2021-03-31 18:00:19 +08:00
exu_dispatch.sv rtl: add static branch predict unit 2021-06-11 09:44:26 +08:00
exu_mem.sv rtl: core: optimize mem access 2021-06-05 20:00:15 +08:00
exu_muldiv.sv temp commit 2021-04-30 18:27:30 +08:00
gpr_reg.sv temp commit 2021-03-31 18:00:19 +08:00
idu.sv temp commit 2021-06-18 20:04:46 +08:00
idu_exu.sv temp commit 2021-06-18 20:04:46 +08:00
ifu.sv rtl: ifu optimization 2021-07-03 15:09:13 +08:00
ifu_idu.sv rtl: ifu optimization 2021-07-03 15:09:13 +08:00
pipe_ctrl.sv temp commit 2021-07-01 09:46:56 +08:00
rst_gen.sv rtl: add reset module 2021-04-13 14:12:47 +08:00
tinyriscv_core.sv temp commit 2021-07-09 15:18:09 +08:00
tracer.sv temp commit 2021-05-04 21:11:43 +08:00