659 lines
41 KiB
Plaintext
659 lines
41 KiB
Plaintext
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2022.2 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="61" Path="D:/project/hdl/ultrasonic_phase_array/Vivado/project_1/project_1.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="1def3724869b4eaa88597cfa1958bb83"/>
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<Option Name="Part" Val="xc7z020clg400-1"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorInstallDirQuesta" Val=""/>
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<Option Name="SimulatorInstallDirXcelium" Val=""/>
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<Option Name="SimulatorInstallDirVCS" Val=""/>
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<Option Name="SimulatorInstallDirRiviera" Val=""/>
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<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
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<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
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<Option Name="SimulatorGccInstallDirVCS" Val=""/>
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<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorVersionXsim" Val="2022.2"/>
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<Option Name="SimulatorVersionModelSim" Val="2022.2"/>
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<Option Name="SimulatorVersionQuesta" Val="2022.2"/>
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<Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
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<Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
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<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
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<Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
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<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
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<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
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<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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<Option Name="BoardPart" Val=""/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../ip_repo"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../../../hardware/Ultrasonic_Phased_Array/Vivado/ip_repo"/>
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
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<Option Name="IPCachePermission" Val="read"/>
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<Option Name="IPCachePermission" Val="write"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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<Option Name="EnableResourceEstimation" Val="FALSE"/>
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<Option Name="SimCompileState" Val="TRUE"/>
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<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="WTXSimLaunchSim" Val="1"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="38"/>
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<Option Name="WTModelSimExportSim" Val="38"/>
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<Option Name="WTQuestaExportSim" Val="38"/>
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<Option Name="WTIesExportSim" Val="0"/>
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<Option Name="WTVcsExportSim" Val="38"/>
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<Option Name="WTRivieraExportSim" Val="38"/>
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<Option Name="WTActivehdlExportSim" Val="38"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="XSimArrayDisplayLimit" Val="1024"/>
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<Option Name="XSimTraceLimit" Val="65536"/>
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<Option Name="SimTypes" Val="rtl"/>
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<Option Name="SimTypes" Val="bfm"/>
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<Option Name="SimTypes" Val="tlm"/>
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<Option Name="SimTypes" Val="tlm_dpi"/>
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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<Option Name="DcpsUptoDate" Val="TRUE"/>
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<Option Name="ClassicSocBoot" Val="FALSE"/>
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<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
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</Configuration>
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/../hdl_sources/serializer.vhd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/delay_wrap/delay_wrap.bd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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<CompFileExtendedInfo CompFileName="delay_wrap.bd" FileRelPathName="ip/delay_wrap_Serializer_0_0/delay_wrap_Serializer_0_0.xci">
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<Proxy FileSetName="delay_wrap_Serializer_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="delay_wrap.bd" FileRelPathName="ip/delay_wrap_axi_delay_generator_0_0/delay_wrap_axi_delay_generator_0_0.xci">
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<Proxy FileSetName="delay_wrap_axi_delay_generator_0_0"/>
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</CompFileExtendedInfo>
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</File>
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<File Path="$PGENDIR/sources_1/bd/delay_wrap/hdl/delay_wrap_wrapper.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/divider.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/paraller.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/axi_jtag_test/axi_jtag_test.bd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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<CompFileExtendedInfo CompFileName="axi_jtag_test.bd" FileRelPathName="ip/axi_jtag_test_ila_0_0/axi_jtag_test_ila_0_0.xci">
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<Proxy FileSetName="axi_jtag_test_ila_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="axi_jtag_test.bd" FileRelPathName="ip/axi_jtag_test_serial_to_parallel_0_0/axi_jtag_test_serial_to_parallel_0_0.xci">
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<Proxy FileSetName="axi_jtag_test_serial_to_parallel_0_0"/>
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</CompFileExtendedInfo>
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</File>
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<File Path="$PGENDIR/sources_1/bd/axi_jtag_test/hdl/axi_jtag_test_wrapper.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci">
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<Proxy FileSetName="design_1_processing_system7_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
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<Proxy FileSetName="design_1_clk_wiz_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xci">
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<Proxy FileSetName="design_1_clk_wiz_0_1"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xci">
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<Proxy FileSetName="design_1_axi_gpio_0_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_rst_ps7_0_50M_0/design_1_rst_ps7_0_50M_0.xci">
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<Proxy FileSetName="design_1_rst_ps7_0_50M_0"/>
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</CompFileExtendedInfo>
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<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xbar_0/design_1_xbar_0.xci">
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<Proxy FileSetName="design_1_xbar_0"/>
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</CompFileExtendedInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="axi_jtag_test_wrapper"/>
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<Option Name="dataflowViewerSettings" Val="min_width=16"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
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<Filter Type="Constrs"/>
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<File Path="$PSRCDIR/constrs_1/new/all.xdc">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/all.xdc"/>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
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<Filter Type="Srcs"/>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="delay_wrap_wrapper"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopRTLFile" Val="$PGENDIR/sources_1/bd/delay_wrap/hdl/delay_wrap_wrapper.v"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="SelectedSimModel" Val="rtl"/>
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<Option Name="PamDesignTestbench" Val=""/>
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<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
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<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
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<Option Name="PamPseudoTop" Val="pseudo_tb"/>
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<Option Name="SrcSet" Val="sources_1"/>
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<Option Name="xsim.simulate.runtime" Val="100ms"/>
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</Config>
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||
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</FileSet>
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||
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
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<Filter Type="Utils"/>
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||
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<File Path="$PSRCDIR/utils_1/imports/synth_1/axi_jtag_test_wrapper.dcp">
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||
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<FileInfo>
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||
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<Attr Name="UsedIn" Val="synthesis"/>
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||
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedInSteps" Val="synth_1"/>
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<Attr Name="AutoDcp" Val="1"/>
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||
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</FileInfo>
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||
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</File>
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||
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<Config>
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||
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<Option Name="TopAutoSet" Val="TRUE"/>
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||
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</Config>
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||
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|
</FileSet>
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||
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<FileSet Name="delay_wrap_axi_delay_generator_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/delay_wrap_axi_delay_generator_0_0" RelGenDir="$PGENDIR/delay_wrap_axi_delay_generator_0_0">
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||
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<Config>
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||
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<Option Name="TopModule" Val="delay_wrap_axi_delay_generator_0_0"/>
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||
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<Option Name="dataflowViewerSettings" Val="min_width=16"/>
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||
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<Option Name="UseBlackboxStub" Val="1"/>
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||
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</Config>
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||
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</FileSet>
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||
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<FileSet Name="delay_wrap_Serializer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/delay_wrap_Serializer_0_0" RelGenDir="$PGENDIR/delay_wrap_Serializer_0_0">
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||
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<Config>
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||
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<Option Name="TopModule" Val="delay_wrap_Serializer_0_0"/>
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<Option Name="dataflowViewerSettings" Val="min_width=16"/>
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||
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<Option Name="UseBlackboxStub" Val="1"/>
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||
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|
</Config>
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||
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|
</FileSet>
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||
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<FileSet Name="design_1_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_processing_system7_0_0" RelGenDir="$PGENDIR/design_1_processing_system7_0_0">
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||
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<Config>
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||
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|
<Option Name="TopModule" Val="design_1_processing_system7_0_0"/>
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||
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<Option Name="dataflowViewerSettings" Val="min_width=16"/>
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||
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<Option Name="UseBlackboxStub" Val="1"/>
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||
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</Config>
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||
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|
</FileSet>
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||
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<FileSet Name="design_1_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_xbar_0" RelGenDir="$PGENDIR/design_1_xbar_0">
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||
|
|
<Config>
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||
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|
<Option Name="TopModule" Val="design_1_xbar_0"/>
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||
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<Option Name="dataflowViewerSettings" Val="min_width=16"/>
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||
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|
<Option Name="UseBlackboxStub" Val="1"/>
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||
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|
</Config>
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||
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</FileSet>
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||
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<FileSet Name="design_1_rst_ps7_0_50M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_rst_ps7_0_50M_0" RelGenDir="$PGENDIR/design_1_rst_ps7_0_50M_0">
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||
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<Config>
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||
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|
<Option Name="TopModule" Val="design_1_rst_ps7_0_50M_0"/>
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||
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<Option Name="dataflowViewerSettings" Val="min_width=16"/>
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||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
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||
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|
</Config>
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||
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|
</FileSet>
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||
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<FileSet Name="design_1_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_clk_wiz_0_0" RelGenDir="$PGENDIR/design_1_clk_wiz_0_0">
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||
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<Config>
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||
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|
<Option Name="TopModule" Val="design_1_clk_wiz_0_0"/>
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||
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<Option Name="dataflowViewerSettings" Val="min_width=16"/>
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||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
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</Config>
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||
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</FileSet>
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||
|
|
<FileSet Name="design_1_clk_wiz_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_clk_wiz_0_1" RelGenDir="$PGENDIR/design_1_clk_wiz_0_1">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_clk_wiz_0_1"/>
|
||
|
|
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="design_1_axi_gpio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axi_gpio_0_0" RelGenDir="$PGENDIR/design_1_axi_gpio_0_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="design_1_axi_gpio_0_0"/>
|
||
|
|
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="axi_jtag_test_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_jtag_test_ila_0_0" RelGenDir="$PGENDIR/axi_jtag_test_ila_0_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="axi_jtag_test_ila_0_0"/>
|
||
|
|
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
<FileSet Name="axi_jtag_test_serial_to_parallel_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_jtag_test_serial_to_parallel_0_0" RelGenDir="$PGENDIR/axi_jtag_test_serial_to_parallel_0_0">
|
||
|
|
<Config>
|
||
|
|
<Option Name="TopModule" Val="axi_jtag_test_serial_to_parallel_0_0"/>
|
||
|
|
<Option Name="dataflowViewerSettings" Val="min_width=16"/>
|
||
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||
|
|
</Config>
|
||
|
|
</FileSet>
|
||
|
|
</FileSets>
|
||
|
|
<Simulators>
|
||
|
|
<Simulator Name="XSim">
|
||
|
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||
|
|
<Option Name="CompiledLib" Val="0"/>
|
||
|
|
</Simulator>
|
||
|
|
<Simulator Name="ModelSim">
|
||
|
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||
|
|
</Simulator>
|
||
|
|
<Simulator Name="Questa">
|
||
|
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||
|
|
</Simulator>
|
||
|
|
<Simulator Name="Riviera">
|
||
|
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||
|
|
</Simulator>
|
||
|
|
<Simulator Name="ActiveHDL">
|
||
|
|
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||
|
|
</Simulator>
|
||
|
|
</Simulators>
|
||
|
|
<Runs Version="1" Minor="19">
|
||
|
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/axi_jtag_test_wrapper.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="delay_wrap_axi_delay_generator_0_0_synth_1" Type="Ft3:Synth" SrcSet="delay_wrap_axi_delay_generator_0_0" Part="xc7z020clg400-1" ConstrsSet="delay_wrap_axi_delay_generator_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/delay_wrap_axi_delay_generator_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/delay_wrap_axi_delay_generator_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/delay_wrap_axi_delay_generator_0_0_synth_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="delay_wrap_Serializer_0_0_synth_1" Type="Ft3:Synth" SrcSet="delay_wrap_Serializer_0_0" Part="xc7z020clg400-1" ConstrsSet="delay_wrap_Serializer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/delay_wrap_Serializer_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/delay_wrap_Serializer_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/delay_wrap_Serializer_0_0_synth_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_processing_system7_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_processing_system7_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_synth_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_xbar_0" Part="xc7z020clg400-1" ConstrsSet="design_1_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_xbar_0_synth_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_rst_ps7_0_50M_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_rst_ps7_0_50M_0" Part="xc7z020clg400-1" ConstrsSet="design_1_rst_ps7_0_50M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_rst_ps7_0_50M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_50M_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_50M_0_synth_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_wiz_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_clk_wiz_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_0_synth_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_clk_wiz_0_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_wiz_0_1" Part="xc7z020clg400-1" ConstrsSet="design_1_clk_wiz_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_clk_wiz_0_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_synth_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_axi_gpio_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axi_gpio_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axi_gpio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axi_gpio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_gpio_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_gpio_0_0_synth_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="axi_jtag_test_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="axi_jtag_test_ila_0_0" Part="xc7z020clg400-1" ConstrsSet="axi_jtag_test_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_jtag_test_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_jtag_test_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_jtag_test_ila_0_0_synth_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
|
||
|
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||
|
|
</StratHandle>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="axi_jtag_test_serial_to_parallel_0_0_synth_1" Type="Ft3:Synth" SrcSet="axi_jtag_test_serial_to_parallel_0_0" Part="xc7z020clg400-1" ConstrsSet="axi_jtag_test_serial_to_parallel_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_jtag_test_serial_to_parallel_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_jtag_test_serial_to_parallel_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_jtag_test_serial_to_parallel_0_0_synth_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
|
||
|
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||
|
|
</StratHandle>
|
||
|
|
<Step Id="synth_design"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="delay_wrap_axi_delay_generator_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="delay_wrap_axi_delay_generator_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="delay_wrap_axi_delay_generator_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/delay_wrap_axi_delay_generator_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/delay_wrap_axi_delay_generator_0_0_impl_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="delay_wrap_Serializer_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="delay_wrap_Serializer_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="delay_wrap_Serializer_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/delay_wrap_Serializer_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/delay_wrap_Serializer_0_0_impl_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_processing_system7_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_processing_system7_0_0_impl_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_xbar_0_impl_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_rst_ps7_0_50M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_rst_ps7_0_50M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_rst_ps7_0_50M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_50M_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_rst_ps7_0_50M_0_impl_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_clk_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_clk_wiz_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_0_impl_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_clk_wiz_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_clk_wiz_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_clk_wiz_0_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_impl_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="design_1_axi_gpio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axi_gpio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axi_gpio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axi_gpio_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axi_gpio_0_0_impl_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="axi_jtag_test_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="axi_jtag_test_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_jtag_test_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_jtag_test_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_jtag_test_ila_0_0_impl_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
|
||
|
|
<Desc>Default settings for Implementation.</Desc>
|
||
|
|
</StratHandle>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
<Run Id="axi_jtag_test_serial_to_parallel_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="axi_jtag_test_serial_to_parallel_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_jtag_test_serial_to_parallel_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_jtag_test_serial_to_parallel_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_jtag_test_serial_to_parallel_0_0_impl_1">
|
||
|
|
<Strategy Version="1" Minor="2">
|
||
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022">
|
||
|
|
<Desc>Default settings for Implementation.</Desc>
|
||
|
|
</StratHandle>
|
||
|
|
<Step Id="init_design"/>
|
||
|
|
<Step Id="opt_design"/>
|
||
|
|
<Step Id="power_opt_design"/>
|
||
|
|
<Step Id="place_design"/>
|
||
|
|
<Step Id="post_place_power_opt_design"/>
|
||
|
|
<Step Id="phys_opt_design"/>
|
||
|
|
<Step Id="route_design"/>
|
||
|
|
<Step Id="post_route_phys_opt_design"/>
|
||
|
|
<Step Id="write_bitstream"/>
|
||
|
|
</Strategy>
|
||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
|
||
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||
|
|
<RQSFiles/>
|
||
|
|
</Run>
|
||
|
|
</Runs>
|
||
|
|
<Board/>
|
||
|
|
<DashboardSummary Version="1" Minor="0">
|
||
|
|
<Dashboards>
|
||
|
|
<Dashboard Name="default_dashboard">
|
||
|
|
<Gadgets>
|
||
|
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||
|
|
</Gadget>
|
||
|
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||
|
|
</Gadget>
|
||
|
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||
|
|
</Gadget>
|
||
|
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||
|
|
</Gadget>
|
||
|
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||
|
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||
|
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||
|
|
</Gadget>
|
||
|
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||
|
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||
|
|
</Gadget>
|
||
|
|
</Gadgets>
|
||
|
|
</Dashboard>
|
||
|
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||
|
|
</Dashboards>
|
||
|
|
</DashboardSummary>
|
||
|
|
</Project>
|