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added documentation

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Dylan Missuwe 2022-10-11 19:17:00 +02:00
parent af0c7719bb
commit 953858d739
1564 changed files with 2039 additions and 470737 deletions
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README.md
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@ -9141,3 +9141,9 @@ java.lang.Error
at org.eclipse.tcf.core.AbstractChannel$1$1.run(AbstractChannel.java:371)
at org.eclipse.tcf.EventQueue.run(EventQueue.java:98)
at java.base/java.lang.Thread.run(Thread.java:829)
!ENTRY com.xilinx.sdk.utils 0 0 2022-10-11 18:46:18.100
!MESSAGE XSCT Command: [disconnect tcfchan#5], Thread: Thread-259
!ENTRY com.xilinx.sdk.utils 0 0 2022-10-11 18:46:18.181
!MESSAGE XSCT command with result: [disconnect tcfchan#5], Result: [null, ]. Thread: Thread-259

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<?xml version="1.0" encoding="UTF-8"?>
<section name="Workbench">
<item key="devices_info_Local" value="{&quot;cables&quot;:[{&quot;name&quot;:&quot;Digilent Zybo Z7 210351B104CCA&quot;,&quot;indexContextMap&quot;:{&quot;2&quot;:&quot;jsn-Zybo Z7-210351B104CCA-4ba00477-0&quot;,&quot;3&quot;:&quot;jsn-Zybo Z7-210351B104CCA-23727093-0&quot;}}]}"/>
</section>

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*** SESSION Oct 01, 2022 17:30:32.37 -------------------------------------------
*** SESSION Oct 01, 2022 18:12:01.54 -------------------------------------------
*** SESSION Oct 03, 2022 21:08:29.07 -------------------------------------------
*** SESSION Oct 07, 2022 15:02:57.97 -------------------------------------------

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<?xml version="1.0" encoding="UTF-8"?>
<section name="Workbench">
<section name="completion_proposal_size">
</section>
<section name="org.eclipse.cdt.ui.text.hover.CMacroExpansionExploration">
</section>
</section>

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/******************************************************************************
* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_standalone.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
* used under Xilinx standalone BSP.
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a rmm 03/21/02 First release
* 1.00a wgr 03/22/07 Converted to new coding style.
* 1.00a rpm 06/29/07 Added udelay macro for standalone
* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
* to in MICROBLAZE section
* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
*
* </pre>
*
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XENV_STANDALONE_H
#define XENV_STANDALONE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/******************************************************************************
*
* Get the processor dependent includes
*
******************************************************************************/
#include <string.h>
#if defined __MICROBLAZE__
# include "mb_interface.h"
# include "xparameters.h" /* XPAR constants used below in MB section */
#elif defined __PPC__
# include "sleep.h"
# include "xcache_l.h" /* also include xcache_l.h for caching macros */
#endif
/******************************************************************************
*
* MEMCPY / MEMSET related macros.
*
* The following are straight forward implementations of memset and memcpy.
*
* NOTE: memcpy may not work if source and target memory area are overlapping.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
* @note
* This implementation MAY BREAK work if source and target memory
* area are overlapping.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
/******************************************************************************
*
* TIME related macros
*
******************************************************************************/
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef s32 XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds. Not implemented without OS
* support.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#ifdef __PPC__
#define XENV_USLEEP(delay) usleep(delay)
#define udelay(delay) usleep(delay)
#else
#define XENV_USLEEP(delay)
#define udelay(delay)
#endif
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* Processor independent macros
*
******************************************************************************/
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
/******************************************************************************
*
* MicroBlaze case
*
* NOTE: Currently the following macros will only work on systems that contain
* only ONE MicroBlaze processor. Also, the macros will only be enabled if the
* system is built using a xparameters.h file.
*
******************************************************************************/
#if defined __MICROBLAZE__
/* Check if MicroBlaze data cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
#else
# define XCACHE_ENABLE_DCACHE()
# define XCACHE_DISABLE_DCACHE()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
/* Check if MicroBlaze instruction cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_ENABLE_ICACHE()
# define XCACHE_DISABLE_ICACHE()
#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
/******************************************************************************
*
* PowerPC case
*
* Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
* specific memory region (0x80000001). Each bit (0-30) in the regions
* bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
* range.
*
* regions --> cached address range
* ------------|--------------------------------------------------
* 0x80000000 | [0, 0x7FFFFFF]
* 0x00000001 | [0xF8000000, 0xFFFFFFFF]
* 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
*
******************************************************************************/
#elif defined __PPC__
#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifndef XENV_STANDALONE_H */
/**
*@endcond
*/

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/******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xparameters_ps.h
*
* This file contains the address definitions for the hard peripherals
* attached to the ARM Cortex A53 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _XPARAMETERS_PS_H_
#define _XPARAMETERS_PS_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
*@cond nocomments
*/
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/*
* This block contains constant declarations for the peripherals
* within the hardblock
*/
/* Canonical definitions for DDR MEMORY */
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
/* Canonical definitions for Interrupts */
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID
#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID
#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
#define XPAR_XWDTPS_0_INTR XPS_LPD_SWDT_INT_ID
#define XPAR_XWDTPS_1_INTR XPS_FPD_SWDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID
#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID
#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID
#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID
#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID
#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID
#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID
#define XPAR_PSU_ADMA_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_PSU_ADMA_1_INTR XPS_ADMA_CH1_INT_ID
#define XPAR_PSU_ADMA_2_INTR XPS_ADMA_CH2_INT_ID
#define XPAR_PSU_ADMA_3_INTR XPS_ADMA_CH3_INT_ID
#define XPAR_PSU_ADMA_4_INTR XPS_ADMA_CH4_INT_ID
#define XPAR_PSU_ADMA_5_INTR XPS_ADMA_CH5_INT_ID
#define XPAR_PSU_ADMA_6_INTR XPS_ADMA_CH6_INT_ID
#define XPAR_PSU_ADMA_7_INTR XPS_ADMA_CH7_INT_ID
#define XPAR_PSU_CSUDMA_INTR XPS_CSU_DMA_INT_ID
#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID
#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID
#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID
#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID
#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID
#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID
#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID
#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID
#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID
#define XPAR_PSU_GDMA_0_INTR XPS_ZDMA_CH0_INT_ID
#define XPAR_PSU_GDMA_1_INTR XPS_ZDMA_CH1_INT_ID
#define XPAR_PSU_GDMA_2_INTR XPS_ZDMA_CH2_INT_ID
#define XPAR_PSU_GDMA_3_INTR XPS_ZDMA_CH3_INT_ID
#define XPAR_PSU_GDMA_4_INTR XPS_ZDMA_CH4_INT_ID
#define XPAR_PSU_GDMA_5_INTR XPS_ZDMA_CH5_INT_ID
#define XPAR_PSU_GDMA_6_INTR XPS_ZDMA_CH6_INT_ID
#define XPAR_PSU_GDMA_7_INTR XPS_ZDMA_CH7_INT_ID
#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID
#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID
#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID
#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID
#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID
#define XPAR_XUSBPS_0_WAKE_INTR XPS_USB3_0_WAKE_INT_ID
#define XPAR_XUSBPS_1_WAKE_INTR XPS_USB3_1_WAKE_INT_ID
#define XPAR_XRTCPSU_ALARM_INTR XPS_RTC_ALARM_INT_ID
#define XPAR_XRTCPSU_SECONDS_INTR XPS_RTC_SEC_INT_ID
#define XPAR_XAPMPS_0_INTR XPS_APM0_INT_ID
#define XPAR_XAPMPS_1_INTR XPS_APM1_INT_ID
#define XPAR_XAPMPS_2_INTR XPS_APM2_INT_ID
#define XPAR_XAPMPS_5_INTR XPS_APM5_INT_ID
#define XPAR_XSYSMONPSU_INTR XPS_AMS_INT_ID
/* Canonical definitions for SCU GIC */
#define XPAR_SCUGIC_NUM_INSTANCES 1U
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
/*
* This block contains constant declarations for the peripherals
* within the hardblock. These have been put for backwards compatibility
*/
#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
#define XPS_SCU_PERIPH_BASE 0xF9000000U
/* Shared Peripheral Interrupts (SPI) */
#define XPS_FPGA0_INT_ID 121U
#define XPS_FPGA1_INT_ID 122U
#define XPS_FPGA2_INT_ID 123U
#define XPS_FPGA3_INT_ID 124U
#define XPS_FPGA4_INT_ID 125U
#define XPS_FPGA5_INT_ID 126U
#define XPS_FPGA6_INT_ID 127U
#define XPS_FPGA7_INT_ID 128U
#define XPS_FPGA8_INT_ID 136U
#define XPS_FPGA9_INT_ID 137U
#define XPS_FPGA10_INT_ID 138U
#define XPS_FPGA11_INT_ID 139U
#define XPS_FPGA12_INT_ID 140U
#define XPS_FPGA13_INT_ID 141U
#define XPS_FPGA14_INT_ID 142U
#define XPS_FPGA15_INT_ID 143U
/* Updated Interrupt-IDs */
#define XPS_OCMINTR_INT_ID (10U + 32U)
#define XPS_NAND_INT_ID (14U + 32U)
#define XPS_QSPI_INT_ID (15U + 32U)
#define XPS_GPIO_INT_ID (16U + 32U)
#define XPS_I2C0_INT_ID (17U + 32U)
#define XPS_I2C1_INT_ID (18U + 32U)
#define XPS_SPI0_INT_ID (19U + 32U)
#define XPS_SPI1_INT_ID (20U + 32U)
#define XPS_UART0_INT_ID (21U + 32U)
#define XPS_UART1_INT_ID (22U + 32U)
#define XPS_CAN0_INT_ID (23U + 32U)
#define XPS_CAN1_INT_ID (24U + 32U)
#define XPS_RTC_ALARM_INT_ID (26U + 32U)
#define XPS_RTC_SEC_INT_ID (27U + 32U)
#define XPS_LPD_SWDT_INT_ID (52U + 32U)
#define XPS_FPD_SWDT_INT_ID (113U + 32U)
#define XPS_TTC0_0_INT_ID (36U + 32U)
#define XPS_TTC0_1_INT_ID (37U + 32U)
#define XPS_TTC0_2_INT_ID (38U + 32U)
#define XPS_TTC1_0_INT_ID (39U + 32U)
#define XPS_TTC1_1_INT_ID (40U + 32U)
#define XPS_TTC1_2_INT_ID (41U + 32U)
#define XPS_TTC2_0_INT_ID (42U + 32U)
#define XPS_TTC2_1_INT_ID (43U + 32U)
#define XPS_TTC2_2_INT_ID (44U + 32U)
#define XPS_TTC3_0_INT_ID (45U + 32U)
#define XPS_TTC3_1_INT_ID (46U + 32U)
#define XPS_TTC3_2_INT_ID (47U + 32U)
#define XPS_SDIO0_INT_ID (48U + 32U)
#define XPS_SDIO1_INT_ID (49U + 32U)
#define XPS_AMS_INT_ID (56U + 32U)
#define XPS_GEM0_INT_ID (57U + 32U)
#define XPS_GEM0_WAKE_INT_ID (58U + 32U)
#define XPS_GEM1_INT_ID (59U + 32U)
#define XPS_GEM1_WAKE_INT_ID (60U + 32U)
#define XPS_GEM2_INT_ID (61U + 32U)
#define XPS_GEM2_WAKE_INT_ID (62U + 32U)
#define XPS_GEM3_INT_ID (63U + 32U)
#define XPS_GEM3_WAKE_INT_ID (64U + 32U)
#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U)
#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U)
#define XPS_USB3_0_WAKE_INT_ID (75U + 32U)
#define XPS_USB3_1_WAKE_INT_ID (76U + 32U)
#define XPS_ADMA_CH0_INT_ID (77U + 32U)
#define XPS_ADMA_CH1_INT_ID (78U + 32U)
#define XPS_ADMA_CH2_INT_ID (79U + 32U)
#define XPS_ADMA_CH3_INT_ID (80U + 32U)
#define XPS_ADMA_CH4_INT_ID (81U + 32U)
#define XPS_ADMA_CH5_INT_ID (82U + 32U)
#define XPS_ADMA_CH6_INT_ID (83U + 32U)
#define XPS_ADMA_CH7_INT_ID (84U + 32U)
#define XPS_CSU_DMA_INT_ID (86U + 32U)
#define XPS_XMPU_LPD_INT_ID (88U + 32U)
#define XPS_ZDMA_CH0_INT_ID (124U + 32U)
#define XPS_ZDMA_CH1_INT_ID (125U + 32U)
#define XPS_ZDMA_CH2_INT_ID (126U + 32U)
#define XPS_ZDMA_CH3_INT_ID (127U + 32U)
#define XPS_ZDMA_CH4_INT_ID (128U + 32U)
#define XPS_ZDMA_CH5_INT_ID (129U + 32U)
#define XPS_ZDMA_CH6_INT_ID (130U + 32U)
#define XPS_ZDMA_CH7_INT_ID (131U + 32U)
#define XPS_XMPU_FPD_INT_ID (134U + 32U)
#define XPS_FPD_CCI_INT_ID (154U + 32U)
#define XPS_FPD_SMMU_INT_ID (155U + 32U)
#define XPS_APM0_INT_ID (123U + 32U)
#define XPS_APM1_INT_ID (25U + 32U)
#define XPS_APM2_INT_ID (25U + 32U)
#define XPS_APM5_INT_ID (123U + 32U)
/* REDEFINES for TEST APP */
#define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PSU_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PSU_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PSU_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PSU_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PSU_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PSU_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PSU_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PSU_CAN_0_INTR XPS_CAN0_INT_ID
#define XPAR_PSU_CAN_1_INTR XPS_CAN1_INT_ID
#define XPAR_PSU_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PSU_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PSU_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PSU_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_2_INTR XPS_GEM2_INT_ID
#define XPAR_PSU_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
#define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID
#define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PSU_WDT_0_INTR XPS_LPD_SWDT_INT_ID
#define XPAR_PSU_WDT_1_INTR XPS_FPD_SWDT_INT_ID
#define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PSU_TTC_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_PSU_TTC_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_PSU_TTC_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_PSU_TTC_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_PSU_TTC_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_PSU_TTC_6_INTR XPS_TTC2_0_INT_ID
#define XPAR_PSU_TTC_7_INTR XPS_TTC2_1_INT_ID
#define XPAR_PSU_TTC_8_INTR XPS_TTC2_2_INT_ID
#define XPAR_PSU_TTC_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_PSU_TTC_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_PSU_TTC_11_INTR XPS_TTC3_2_INT_ID
#define XPAR_PSU_AMS_INTR XPS_AMS_INT_ID
#define XPAR_XADCPS_NUM_INSTANCES 1U
#define XPAR_XADCPS_0_DEVICE_ID 0U
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
/* For backwards compatibility */
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
#ifdef XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
#endif
#ifdef XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
#endif
#define XPAR_SCUWDT_DEVICE_ID 0U
/**
*@endcond
*/
#ifdef __cplusplus
}
#endif
#endif /* protection macro */

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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpseudo_asm_rvct.h
*
* This header file contains macros for using __inline assembler code. It is
* written specifically for RVCT.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sdm 11/18/09 First Release
* 7.2 asa 04/03/20 Renamed the str macro to strw.
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XPSEUDO_ASM_RVCT_H /* prevent circular inclusions */
#define XPSEUDO_ASM_RVCT_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
#define mtcpsr(v) { volatile register u32 Reg __asm("cpsr");\
Reg = v; }
/* general purpose register read/write */
/*#define mfgpr(rn) ({ unsigned int val; \
register unsigned int Reg __asm("r" stringify(rn));\
val = Reg; \
val;})*/
#define mtgpr(rn, v) { volatile register u32 Reg __asm("r" stringify(rn));\
Reg = v; }
/* CP15 operations */
/*#define mfcp(rn) ({ unsigned int val; \
val = register unsigned int Reg __asm(rn); \
val;})*/
#define mtcp(rn, v) { volatile register u32 Reg __asm(rn); \
Reg = v; }
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
__asm void cpsiei(void);
__asm void cpsidi(void);
__asm void cpsief(void);
__asm void cpsidf(void);
/* memory synchronization operations */
/* Instruction Synchronization Barrier */
__asm void isb(void);
/* Data Synchronization Barrier */
__asm void dsb(void);
/* Data Memory Barrier */
__asm void dmb(void);
/* Memory Operations */
__asm u32 ldr(u32 adr);
__asm u32 ldrb(u32 adr);
__asm void strw(u32 adr, u32 val);
__asm void strb(u32 adr, u32 val);
/* Count leading zeroes (clz) */
__asm u32 clz(u32 arg);
__asm u32 mfcpsr(void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XPSEUDO_ASM_RVCT_H */
/**
*@endcond
*/

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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache_vxworks.h
*
* Contains the cache related functions for VxWorks that is wrapped by
* xil_cache.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 12/11/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_CACHE_VXWORKS_H
#define XIL_CACHE_VXWORKS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "vxWorks.h"
#include "vxLib.h"
#include "sysLibExtra.h"
#include "cacheLib.h"
#if (CPU_FAMILY==PPC)
#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
#define Xil_DCacheInvalidateRange(Addr, Len) \
cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_DCacheFlushRange(Addr, Len) \
cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
#define Xil_ICacheInvalidateRange(Addr, Len) \
cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
#else
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#endif
#ifdef __cplusplus
}
#endif
#endif
/**
*@endcond
*/

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/*******************************************************************************
* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
#ifndef __XPMC_XIOU_SECURE_SLCR_H__
#define __XPMC_XIOU_SECURE_SLCR_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
*@cond nocomments
*/
/**
* XpmcXiouSecureSlcr Base Address
*/
#define XPMC_XIOU_SECURE_SLCR_BASEADDR 0xF1070000UL
/**
* Register: XpmcXiouSecureSlcrAxiWprtcnSd0
*/
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0 ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_WIDTH 3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_MASK 0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_DEFVAL 0x0UL
/**
* Register: XpmcXiouSecureSlcrAxiRprtcnSd0
*/
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0 ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_WIDTH 3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_MASK 0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_DEFVAL 0x0UL
/**
* Register: XpmcXiouSecureSlcrAxiWprtcnSd1
*/
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1 ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000010UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_WIDTH 3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_MASK 0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_DEFVAL 0x0UL
/**
* Register: XpmcXiouSecureSlcrAxiRprtcnSd1
*/
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1 ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000014UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_WIDTH 3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_MASK 0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_DEFVAL 0x0UL
/**
* Register: XpmcXiouSecureSlcrAxiWprtcnQspi
*/
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000020UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_WIDTH 3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_MASK 0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL
/**
* Register: XpmcXiouSecureSlcrAxiWprtcnOspi
*/
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000030UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_WIDTH 3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_MASK 0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_DEFVAL 0x0UL
/**
* Register: XpmcXiouSecureSlcrCtrl
*/
#define XPMC_XIOU_SECURE_SLCR_CTRL ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
#define XPMC_XIOU_SECURE_SLCR_CTRL_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XpmcXiouSecureSlcrIsr
*/
#define XPMC_XIOU_SECURE_SLCR_ISR ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
#define XPMC_XIOU_SECURE_SLCR_ISR_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_WIDTH 1UL
#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_MASK 0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_DEFVAL 0x0UL
/**
* Register: XpmcXiouSecureSlcrImr
*/
#define XPMC_XIOU_SECURE_SLCR_IMR ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
#define XPMC_XIOU_SECURE_SLCR_IMR_RSTVAL 0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_WIDTH 1UL
#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_MASK 0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_DEFVAL 0x1UL
/**
* Register: XpmcXiouSecureSlcrIer
*/
#define XPMC_XIOU_SECURE_SLCR_IER ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
#define XPMC_XIOU_SECURE_SLCR_IER_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_WIDTH 1UL
#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_MASK 0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_DEFVAL 0x0UL
/**
* Register: XpmcXiouSecureSlcrIdr
*/
#define XPMC_XIOU_SECURE_SLCR_IDR ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
#define XPMC_XIOU_SECURE_SLCR_IDR_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_WIDTH 1UL
#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_MASK 0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_DEFVAL 0x0UL
/**
* Register: XpmcXiouSecureSlcrItr
*/
#define XPMC_XIOU_SECURE_SLCR_ITR ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
#define XPMC_XIOU_SECURE_SLCR_ITR_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_WIDTH 1UL
#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_MASK 0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_DEFVAL 0x0UL
/**
* Register: XpmcXiouSecureSlcrTzprot
*/
#define XPMC_XIOU_SECURE_SLCR_TZPROT ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x0000006CUL )
#define XPMC_XIOU_SECURE_SLCR_TZPROT_RSTVAL 0x00000000UL
#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_SHIFT 0UL
#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_WIDTH 1UL
#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_MASK 0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_DEFVAL 0x0UL
/**
*@endcond
*/
#ifdef __cplusplus
}
#endif
#endif /* __XPMC_XIOU_SECURE_SLCR_H__ */

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/******************************************************************************
* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/******************************************************************************
*
* microblaze_invalidate_dcache()
*
* Invalidate the entire L1 DCache
*
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
#endif
#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
#define MB_VERSION_LT_v720
#endif
.text
.globl microblaze_invalidate_dcache
.ent microblaze_invalidate_dcache
.align 2
microblaze_invalidate_dcache:
#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
mfs r9, rmsr
andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
mts rmsr, r10
#endif
ADDIK r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
ADDIK r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
L_start:
wdc r5, r0 /* Invalidate the Cache */
CMPU r18, r5, r6 /* Are we at the end? */
BLEI r18, L_done
#if defined (__arch64__ )
addlik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */
breai L_start
#else
brid L_start /* Branch to the beginning of the loop */
addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */
#endif
L_done:
rtsd r15, 8 /* Return */
#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
mts rmsr, r9
#else
nop
#endif
#else
rtsd r15, 8 /* Return */
nop
#endif
.end microblaze_invalidate_dcache

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/******************************************************************************
* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xadcps_sinit.c
* @addtogroup xadcps_v2_6
* @{
*
* This file contains the implementation of the XAdcPs driver's static
* initialization functionality.
*
* @note None.
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a ssb 12/22/11 First release based on the XPS/AXI XADC driver
* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xadcps.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern XAdcPs_Config XAdcPs_ConfigTable[];
/*****************************************************************************/
/**
*
* This function looks up the device configuration based on the unique device ID.
* The table XAdcPs_ConfigTable contains the configuration info for each device
* in the system.
*
* @param DeviceId contains the ID of the device for which the
* device configuration pointer is to be returned.
*
* @return
* - A pointer to the configuration found.
* - NULL if the specified device ID was not found.
*
* @note None.
*
******************************************************************************/
XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId)
{
XAdcPs_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; Index < 1U; Index++) {
if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XAdcPs_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
/** @} */

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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspips.h
* @addtogroup qspips_v3_9
* @{
* @details
*
* This file contains the implementation of the XQspiPs driver. It supports only
* master mode. User documentation for the driver functions is contained in this
* file in the form of comment blocks at the front of each function.
*
* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
* between one master and one slave. The device is always full-duplex,
* which means that for every byte sent, one is received, and vice-versa.
* The master controls the clock, so it can regulate when it wants to
* send or receive data. The slave is under control of the master, it must
* respond quickly since it has no control of the clock and must send/receive
* data as fast or as slow as the master does.
*
* <b> Linear Mode </b>
* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller<65>s
* functionality by adding a linear addressing scheme that allows the SPI flash
* memory subsystem to behave like a typical ROM device. The new feature hides
* the normal SPI protocol from a master reading from the SPI flash memory. The
* feature improves both the user friendliness and the overall read memory
* throughput over that of the current Quad-SPI Controller by lessening the
* amount of software overheads required and by the use of the faster AXI
* interface.
*
* <b>Initialization & Configuration</b>
*
* The XQspiPs_Config structure is used by the driver to configure itself. This
* configuration structure is typically created by the tool-chain based on HW
* build properties.
*
* To support multiple runtime loading and initialization strategies employed by
* various operating systems, the driver instance can be initialized in the
* following way:
* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
* static configuration structure defined in xqspips_g.c. This is setup
* by the tools. For some operating systems the config structure will be
* initialized by the software and this call is not needed.
* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* <b>Multiple Masters</b>
*
* More than one master can exist, but arbitration is the responsibility of
* the higher layer software. The device driver does not perform any type of
* arbitration.
*
* <b>Modes of Operation</b>
*
* There are four modes to perform a data transfer and the selection of a mode
* is based on Chip Select(CS) and Start. These two options individually, can
* be controlled either by software(Manual) or hardware(Auto).
* - Auto CS: Chip select is automatically asserted as soon as the first word
* is written into the TXFIFO and de asserted when the TXFIFO becomes
* empty
* - Manual CS: Software must assert and de assert CS.
* - Auto Start: Data transmission starts as soon as there is data in the
* TXFIFO and stalls when the TXFIFO is empty
* - Manual Start: Software must start data transmission at the beginning of
* the transaction or whenever the TXFIFO has become empty
*
* The preferred combination is Manual CS and Auto Start.
* In this combination, the software asserts CS before loading any data into
* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
* data is available. If no further data, software disables CS.
*
* Risks/challenges of other combinations:
* - Manual CS and Manual Start: Manual Start bit should be set after each
* TXFIFO write otherwise there could be a race condition where the TXFIFO
* becomes empty before the new word is written. In that case the
* transmission stops.
* - Auto CS with Manual or Auto Start: It is very difficult for software to
* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
* This results in a single transaction to be split into multiple pieces each
* with its own chip select. This will result in garbage data to be sent.
*
* <b>Interrupts</b>
*
* The user must connect the interrupt handler of the driver,
* XQspiPs_InterruptHandler, to an interrupt system such that it will be
* called when an interrupt occurs. This function does not save and restore
* the processor context such that the user must provide this processing.
*
* The driver handles the following interrupts:
* - Data Transmit Register/FIFO Underflow
* - Data Receive Register/FIFO Not Empty
* - Data Transmit Register/FIFO Overwater
* - Data Receive Register/FIFO Overrun
*
* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
* QSPI device has transmitted the data available to transmit, and now its data
* register and FIFO is ready to accept more data. The driver uses this
* interrupt to indicate progress while sending data. The driver may have
* more data to send, in which case the data transmit register and FIFO is
* filled for subsequent transmission. When this interrupt arrives and all
* the data has been sent, the driver invokes the status callback with a
* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
* all data has been sent.
*
* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
* as slave, the QSPI device was required to transmit but there was no data
* available to transmit in the transmit register (or FIFO). This may not
* be an error if the master is not expecting data. But in the case where
* the master is expecting data, this serves as a notification of such a
* condition. The driver reports this condition to the upper layer
* software through the status handler.
*
* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
* device received data and subsequently dropped the data because the data
* receive register and FIFO was full. The driver reports this condition to the
* upper layer software through the status handler. This likely indicates a
* problem with the higher layer protocol, or a problem with the slave
* performance.
*
*
* <b>Polled Operation</b>
*
* Transfer in polled mode is supported through a separate interface function
* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
* this function blocks until all data has been sent/received.
*
* <b>Device Busy</b>
*
* Some operations are disallowed when the device is busy. The driver tracks
* whether a device is busy. The device is considered busy when a data transfer
* request is outstanding, and is considered not busy only when that transfer
* completes (or is aborted with a mode fault error).
*
* <b>Device Configuration</b>
*
* The device can be configured in various ways during the FPGA implementation
* process. Configuration parameters are stored in the xqspips_g.c file or
* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
* contains configuration information for an QSPI device, including the base
* address for the device.
*
* <b>RTOS Independence</b>
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads or
* thread mutual exclusion, virtual memory, or cache control must be satisfied
* by the layer above this driver.
*
* NOTE: This driver was always tested with endianness set to little-endian.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
* in xparameters.h
* 2.00a kka 07/25/12 Added a few register defines for CR 670297
* Removed code related to mode fault for CR 671468
* The XQspiPs_SetSlaveSelect has been modified to remove
* the argument of the slave select as the QSPI controller
* only supports one slave.
* XQspiPs_GetSlaveSelect API has been removed
* Added a flag ShiftReadData to the instance structure
*. and is used in the XQspiPs_GetReadData API.
* The ShiftReadData Flag indicates whether the data
* read from the Rx FIFO needs to be shifted
* in cases where the data is less than 4 bytes
* Removed the selection for the following options:
* Master mode (XQSPIPS_MASTER_OPTION) and
* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
* as the QSPI driver supports the Master mode
* and Flash Interface mode and doesnot support
* Slave mode or the legacy mode.
* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
* APIs so that the last argument (IsInst) specifying whether
* it is instruction or data has been removed. The first byte
* in the SendBufPtr argument of these APIs specify the
* instruction to be sent to the Flash Device.
* This version of the driver fixes CRs 670197/663787/
* 670297/671468.
* Added the option for setting the Holdb_dr bit in the
* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
* is the option to be used for setting this bit in the
* configuration register.
* The XQspiPs_PolledTransfer function has been updated
* to fill the data to fifo depth.
* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
* Added macros for Set/Get Rx Watermark. Changed QSPI
* Enable/Disable macro argument from BaseAddress to
* Instance Pointer. Added DelayNss argument to SetDelays
* and GetDelays API's.
* Created macros XQspiPs_IsManualStart and
* XQspiPs_IsManualChipSelect.
* Changed QSPI transfer logic for polled and interrupt
* modes to be based on filled tx fifo count and receive
* based on it. RXNEMPTY interrupt is not used.
* Added assertions to XQspiPs_LqspiRead function.
* SetDelays and GetDelays API's include DelayNss parameter.
* Added defines for DelayNss,Rx Watermark,Interrupts
* which need write to clear. Removed Read zeros mask from
* LQSPI Config register. Renamed Fixed burst error to
* data FSM error in LQSPI Status register.
*
* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
* Added enable and disable to the XQspiPs_LqspiRead() function
* Removed XQspi_Reset() in Set_Options() function when
* LQSPI_MODE_OPTION is set.
* Added instructions for bank selection, die erase and
* flag status register to the flash instruction table
* Handling for instructions not in flash instruction
* table added. Checking for Tx FIFO empty when switching from
* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
* byte count 3 (spansion), instruction size and TXD register
* changed accordingly. CR# 712502 and 703869.
* Added prefix to constant definitions for ConnectionMode
* Added (\#ifdef linear base address) in the Linear read function.
* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
* XQspiPs_LqspiRead function. Fix for CR#718141.
*
* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
* thresholds. This is to improve performance.
* Added API's for QSPI reset and
* linear mode initialization for boot.
* Added RX and TX threshold reset to one in XQspiPs_Abort.
* Added RX threshold reset(1) after transfer in polled and
* interrupt transfers. Made changes to make sure threshold
* change is done only when no transfer is in progress.
* Updated linear init API for parallel and stacked modes.
* CR#737760.
* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
* required bits leaving reserved bits untouched. CR# 796813.
* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
* controller does not update FIFO status flags as expected
* when thresholds are used.
* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
* to remove compilation warnings. CR# 868893.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Modified Comment lines in functions of qspips
* examples to recognize it as documentation block
* and modified filename tag in
* xqspips_dual_flash_stack_lqspi_example.c to include it in
* doxygen examples.
* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
* 3.6 akm 04/15/19 Modified FlashQuadEnable, FlashWrie and FlashErase APIs,
* to wait for the on going operation to complete before
* performing the next operation.
* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
* configuration register values of both the Flashes in dual
* parellel connection.
* 3.7 akm 11/19/19 Fixed Coverity unused value warning in XQspiPs_PolledTransfer()
* and XQspiPs_Transfer() APIs.
* 3.7 akm 03/19/20 Modified XQspiPs_PolledTransfer(), XQspiPs_Transfer() and
* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid
* data when RX buffer is not NULL.
* 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution.
*
* </pre>
*
******************************************************************************/
#ifndef XQSPIPS_H /* prevent circular inclusions */
#define XQSPIPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xqspips_hw.h"
#include <string.h>
/************************** Constant Definitions *****************************/
/** @name Configuration options
*
* The following options are supported to enable/disable certain features of
* an QSPI device. Each of the options is a bit mask, so more than one may be
* specified.
*
*
* The <b>Active Low Clock option</b> configures the device's clock polarity.
* Setting this option means the clock is active low and the SCK signal idles
* high. By default, the clock is active high and SCK idles low.
*
* The <b>Clock Phase option</b> configures the QSPI device for one of two
* transfer formats. A clock phase of 0, the default, means data is valid on
* the first SCK edge (rising or falling) after the slave select (SS) signal
* has been asserted. A clock phase of 1 means data is valid on the second SCK
* edge (rising or falling) after SS has been asserted.
*
*
* The <b>QSPI Force Slave Select option</b> is used to enable manual control of
* the slave select signal.
* 0: The SPI_SS signal is controlled by the QSPI controller during
* transfers. (Default)
* 1: The SPI_SS signal is forced active (driven low) regardless of any
* transfers in progress.
*
* NOTE: The driver will handle setting and clearing the Slave Select when
* the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
* QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
* processor cannot empty and refill the FIFOs before the TX FIFO is empty
* When the QSPI hardware is controlling the Slave Select signals, this
* will cause slave to be de-selected and terminate the transfer.
*
* The <b>Manual Start option</b> is used to enable manual control of
* the Start command to perform data transfer.
* 0: The Start command is controlled by the QSPI controller during
* transfers(Default). Data transmission starts as soon as there is data in
* the TXFIFO and stalls when the TXFIFO is empty
* 1: The Start command must be issued by software to perform data transfer.
* Bit 15 of Configuration register is used to issue Start command. This bit
* must be set whenever TXFIFO is filled with new data.
*
* NOTE: The driver will set the Manual Start Enable bit in Configuration
* Register, if Manual Start option is selected. Software will issue
* Manual Start command whenever TXFIFO is filled with data. When there is
* no further data, driver will clear the Manual Start Enable bit.
*
* @{
*/
#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
/*@}*/
/** @name QSPI Clock Prescaler options
* The QSPI Clock Prescaler Configuration bits are used to program master mode
* bit rate. The bit rate can be programmed in divide-by-two decrements from
* pclk/2 to pclk/256.
*
* @{
*/
#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
/*@}*/
/** @name Callback events
*
* These constants specify the handler events that are passed to
* a handler from the driver. These constants are not bit masks such that
* only one will be passed at a time to the handler.
*
* @{
*/
#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
* RX FIFO full
*/
/*@}*/
/** @name Flash commands
*
* The following constants define most of the commands supported by flash
* devices. Users can add more commands supported by the flash devices
*
* @{
*/
#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
/* Extende Address Register Write - Micron's equivalent of Bank Register */
#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
/* Extende Address Register Read - Micron's equivalent of Bank Register */
#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
/*@}*/
/** @name Instruction size
*
* The following constants define numbers 1 to 4.
* Used to identify whether TXD0,1,2 or 3 is to be used.
*
* @{
*/
#define XQSPIPS_SIZE_ONE 1
#define XQSPIPS_SIZE_TWO 2
#define XQSPIPS_SIZE_THREE 3
#define XQSPIPS_SIZE_FOUR 4
/*@}*/
/** @name ConnectionMode
*
* The following constants are the possible values of ConnectionMode in
* Config structure.
*
* @{
*/
#define XQSPIPS_CONNECTION_MODE_SINGLE 0
#define XQSPIPS_CONNECTION_MODE_STACKED 1
#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
/*@}*/
/** @name FIFO threshold value
*
* This is the Rx FIFO threshold (in words) that was found to be most
* optimal in terms of performance
*
* @{
*/
#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
/*@}*/
/**************************** Type Definitions *******************************/
/**
* The handler data type allows the user to define a callback function to
* handle the asynchronous processing for the QSPI device. The application
* using this driver is expected to define a handler of this type to support
* interrupt driven mode. The handler executes in an interrupt context, so
* only minimal processing should be performed.
*
* @param CallBackRef is the callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* not important to the driver, so it is a void pointer.
* @param StatusEvent holds one or more status events that have occurred.
* See the XQspiPs_SetStatusHandler() for details on the status
* events that can be passed in the callback.
* @param ByteCount indicates how many bytes of data were successfully
* transferred. This may be less than the number of bytes
* requested if the status event indicates an error.
*/
typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
unsigned ByteCount);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
} XQspiPs_Config;
/**
* The XQspiPs driver instance data. The user is required to allocate a
* variable of this type for every QSPI device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XQspiPs_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
u8 *SendBufferPtr; /**< Buffer to send (state) */
u8 *RecvBufferPtr; /**< Buffer to receive (state) */
int RequestedBytes; /**< Number of bytes to transfer (state) */
int RemainingBytes; /**< Number of bytes left to transfer(state) */
u32 IsBusy; /**< A transfer is in progress (state) */
XQspiPs_StatusHandler StatusHandler;
void *StatusRef; /**< Callback reference for status handler */
u32 ShiftReadData; /**< Flag to indicate whether the data
* read from the Rx FIFO needs to be shifted
* in cases where the data is less than 4
* bytes
*/
} XQspiPs;
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/*
*
* Check in OptionsTable if Manual Start Option is enabled or disabled.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return
* - TRUE if option is set
* - FALSE if option is not set
*
* @note C-Style signature:
* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
*
*****************************************************************************/
#define XQspiPs_IsManualStart(InstancePtr) \
((XQspiPs_GetOptions(InstancePtr) & \
XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
/****************************************************************************/
/*
*
* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
*
* @return
* - TRUE if option is set
* - FALSE if option is not set
*
* @note C-Style signature:
* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
*
*****************************************************************************/
#define XQspiPs_IsManualChipSelect(InstancePtr) \
((XQspiPs_GetOptions(InstancePtr) & \
XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
/****************************************************************************/
/**
*
* Set the contents of the slave idle count register.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
* @param RegisterValue is the value to be written, valid values are
* 0-255.
*
* @return None
*
* @note C-Style signature:
* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
* u32 RegisterValue)
*
*****************************************************************************/
#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_SICR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
*
* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
* constants defined in xqspips_hw.h to interpret the bit-mask returned.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return An 8-bit value representing Slave Idle Count.
*
* @note C-Style signature:
* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_GetSlaveIdle(InstancePtr) \
XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_SICR_OFFSET)
/****************************************************************************/
/**
*
* Set the contents of the transmit FIFO watermark register.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
* @param RegisterValue is the value to be written, valid values are 1-63.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
* u32 RegisterValue)
*
*****************************************************************************/
#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_TXWR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
*
* Get the contents of the transmit FIFO watermark register.
* Valid values are in the range 1-63.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return A 6-bit value representing Tx Watermark level.
*
* @note C-Style signature:
* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_GetTXWatermark(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
/****************************************************************************/
/**
*
* Set the contents of the receive FIFO watermark register.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
* @param RegisterValue is the value to be written, valid values are 1-63.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
* u32 RegisterValue)
*
*****************************************************************************/
#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_RXWR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
*
* Get the contents of the receive FIFO watermark register.
* Valid values are in the range 1-63.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return A 6-bit value representing Rx Watermark level.
*
* @note C-Style signature:
* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_GetRXWatermark(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
/****************************************************************************/
/**
*
* Enable the device and uninhibit master transactions.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPs_Enable(XQspiPs *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_Enable(InstancePtr) \
XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
XQSPIPS_ER_ENABLE_MASK)
/****************************************************************************/
/**
*
* Disable the device.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPs_Disable(XQspiPs *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_Disable(InstancePtr) \
XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
/****************************************************************************/
/**
*
* Set the contents of the Linear QSPI Configuration register.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
* @param RegisterValue is the value to be written to the Linear QSPI
* configuration register.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
* u32 RegisterValue)
*
*****************************************************************************/
#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
*
* Get the contents of the Linear QSPI Configuration register.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return A 32-bit value representing the contents of the LQSPI Config
* register.
*
* @note C-Style signature:
* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
XQSPIPS_LQSPI_CR_OFFSET)
/************************** Function Prototypes ******************************/
/*
* Initialization function, implemented in xqspips_sinit.c
*/
XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
/*
* Functions implemented in xqspips.c
*/
int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
u32 EffectiveAddr);
void XQspiPs_Reset(XQspiPs *InstancePtr);
void XQspiPs_Abort(XQspiPs *InstancePtr);
s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
u32 ByteCount);
s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
u8 *RecvBufPtr, u32 ByteCount);
int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
u32 Address, unsigned ByteCount);
int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
XQspiPs_StatusHandler FuncPtr);
void XQspiPs_InterruptHandler(void *InstancePtr);
/*
* Functions for selftest, in xqspips_selftest.c
*/
int XQspiPs_SelfTest(XQspiPs *InstancePtr);
/*
* Functions for options, in xqspips_options.c
*/
s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
u8 DelayAfter, u8 DelayInit);
void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
u8 *DelayAfter, u8 *DelayInit);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

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/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xdevcfg_hw.c
* @addtogroup devcfg_v3_7
* @{
*
* This file contains the implementation of the interface reset functionality
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 2.04a kpc 10/07/13 First release
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xdevcfg_hw.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* This function perform the reset sequence to the given devcfg interface by
* configuring the appropriate control bits in the devcfg specifc registers
* the devcfg reset squence involves the following steps
* Disable all the interuupts
* Clear the status
* Update relevant config registers with reset values
* Disbale the looopback mode and pcap rate enable
*
* @param BaseAddress of the interface
*
* @return N/A
*
* @note
* This function will not modify the slcr registers that are relavant for
* devcfg controller
******************************************************************************/
void XDcfg_ResetHw(u32 BaseAddr)
{
u32 Regval = 0;
/* Mask the interrupts */
XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
XDCFG_IXR_ALL_MASK);
/* Clear the interuupt status */
Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
/* Clear the source address register */
XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0);
/* Clear the destination address register */
XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0);
/* Clear the source length register */
XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0);
/* Clear the destination length register */
XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0);
/* Clear the loopback enable bit */
Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET);
Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK;
XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
/*Reset the configuration register to reset value */
XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
XDCFG_CONFIG_RESET_VALUE);
/*Disable the PCAP rate enable bit */
Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;
XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval);
}
/** @} */

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/******************************************************************************
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_errata.h
*
* @addtogroup a53_errata Cortex A53 64 bit Processor Errata Support
* @{
* Various ARM errata are handled in the standalone BSP. The implementation for
* errata handling follows ARM guidelines and is based on the open source Linux
* support for these errata.
*
* @note
* The errata handling is enabled by default. To disable handling of all the
* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
* disable errata on a per-erratum basis, un-define relevant macros in
* xil_errata.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 6.4 mus 08/11/17 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_ERRATA_H
#define XIL_ERRATA_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name errata_definitions
*
* The errata conditions handled in the standalone BSP are listed below
* @{
*/
#define ENABLE_ARM_ERRATA 1
#ifdef ENABLE_ARM_ERRATA
/**
* Errata No: 855873
* Description: An eviction might overtake a cache clean operation
*/
#define CONFIG_ARM_ERRATA_855873 1
/*@}*/
#endif /* ENABLE_ARM_ERRATA */
#ifdef __cplusplus
}
#endif
#endif /* XIL_ERRATA_H */
/**
* @} End of "addtogroup a53_errata".
*/

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/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include <stdlib.h>
#include <unistd.h>
/*
* abort -- go out via exit...
*/
__attribute__((weak)) void abort(void)
{
_exit(1);
}

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/******************************************************************************
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcoresightpsdcc.h
* @addtogroup coresightps_dcc_v1_8
* @{
* @details
*
* CoreSight driver component.
*
* The coresight is a part of debug communication channel (DCC) group. Jtag UART
* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
* ARM target in XSDB console before running the jtag terminal command. Using the
* coresight driver component, the output stream can be directed to a log file.
*
* @note None.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00 kvn 02/14/15 First release
* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
* kvn 08/18/15 Modified Makefile according to compiler changes.
* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
* for MB BSPs. Instead it throws up a warning. This
* fixes the CR#953056.
* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */
#define XCORESIGHTPSDCC_H /* by using protection macros */
#ifndef __MICROBLAZE__
#include <xil_types.h>
void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
#endif
#endif
/** @} */

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/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_clocking.c
*
* The xil_clocking.c file contains clocking related functions and macros.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 7.2 sd 02/06/20 First release of clocking
* 7.2 sd 03/20/20 Added checking for isolation case
* </pre>
*
******************************************************************************/
#include "xil_clocking.h"
/************************** Variable Definitions *****************************/
#if defined (XPAR_XCRPSU_0_DEVICE_ID) && defined (XCLOCKING)
XClock ClockInstance; /* Instance of clock Controller */
XClockPs_Config *ConfigPtr;
XStatus Xil_ClockInit(void)
{
XStatus Status = XST_FAILURE;
/* Lookup clock configurations */
ConfigPtr = XClock_LookupConfig(XPAR_XCLOCKPS_DEVICE_ID);
/* Initialize the Clock controller driver */
Status = XClock_CfgInitialize(&ClockInstance, ConfigPtr);
return Status;
}
XStatus Xil_ClockEnable(XClock_OutputClks ClockId)
{
XStatus Status = XST_FAILURE;
Status = XClock_EnableClock(ClockId);
return Status;
}
XStatus Xil_ClockDisable(XClock_OutputClks ClockId)
{
XStatus Status = XST_FAILURE;
Status = XClock_DisableClock(ClockId);
return Status;
}
XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate)
{
XStatus Status = XST_FAILURE;
Xil_AssertNonvoid(Rate != NULL);
Status = XClock_GetRate(ClockId, Rate);
if (XST_SUCCESS == Status) {
xdbg_printf(XDBG_DEBUG_GENERAL, "Operating rate = %lx\n",*Rate);
} else {
xdbg_printf(XDBG_DEBUG_ERROR, "Failed: Fetching rate\r\n");
}
return Status;
}
XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate,
XClockRate *SetRate)
{
XStatus Status = XST_FAILURE;
Xil_AssertNonvoid(SetRate != NULL);
if (Rate == 0) {
return XST_FAILURE;
}
Status = XClock_SetRate(ClockId, Rate, SetRate);
if (XST_SUCCESS != Status) {
xdbg_printf(XDBG_DEBUG_ERROR, "Failed Setting rate\n");
}
return Status;
}
#else
XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate)
{
(void) ClockId;
(void) Rate;
return XST_FAILURE;
}
XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate,
XClockRate *SetRate) {
(void) ClockId;
(void) Rate;
(void) SetRate;
return XST_FAILURE;
}
XStatus Xil_ClockInit(void)
{
return XST_SUCCESS;
}
XStatus Xil_ClockEnable(XClock_OutputClks ClockId)
{
(void) ClockId;
return XST_SUCCESS;
}
XStatus Xil_ClockDisable(XClock_OutputClks ClockId)
{
(void) ClockId;
return XST_SUCCESS;
}
#endif /* XCLOCKING */

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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testio.c
* @addtogroup common_test_utils
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 08/25/09 First release
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xil_testio.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions ****************************/
/************************** Function Prototypes *****************************/
/**
*
* Endian swap a 16-bit word.
* @param Data is the 16-bit word to be swapped.
* @return The endian swapped value.
*
*/
static u16 Swap16(u16 Data)
{
return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
}
/**
*
* Endian swap a 32-bit word.
* @param Data is the 32-bit word to be swapped.
* @return The endian swapped value.
*
*/
static u32 Swap32(u32 Data)
{
u16 Lo16;
u16 Hi16;
u16 Swap16Lo;
u16 Swap16Hi;
Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
Lo16 = (u16)(Data & 0x0000FFFFU);
Swap16Lo = Swap16(Lo16);
Swap16Hi = Swap16(Hi16);
return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
}
/*****************************************************************************/
/**
*
* @brief Perform a destructive 8-bit wide register IO test where the
* register is accessed using Xil_Out8 and Xil_In8, and comparing
* the written values by reading them back.
*
* @param Addr: a pointer to the region of memory to be tested.
* @param Length: Length of the block.
* @param Value: constant used for writing the memory.
*
* @return
* - -1 is returned for a failure
* - 0 is returned for a pass
*
*****************************************************************************/
s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
{
u8 ValueIn;
s32 Index;
s32 Status = 0;
for (Index = 0; Index < Length; Index++) {
Xil_Out8((INTPTR)Addr, Value);
ValueIn = Xil_In8((INTPTR)Addr);
if ((Value != ValueIn) && (Status == 0)) {
Status = -1;
break;
}
}
return Status;
}
/*****************************************************************************/
/**
*
* @brief Perform a destructive 16-bit wide register IO test. Each location
* is tested by sequentially writing a 16-bit wide register, reading
* the register, and comparing value. This function tests three kinds
* of register IO functions, normal register IO, little-endian register
* IO, and big-endian register IO. When testing little/big-endian IO,
* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
* Compare In-Out values. Whether to swap the read-in value before
* comparing is controlled by the 5th argument.
*
* @param Addr: a pointer to the region of memory to be tested.
* @param Length: Length of the block.
* @param Value: constant used for writing the memory.
* @param Kind: Type of test. Acceptable values are:
* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
* @param Swap: indicates whether to byte swap the read-in value.
*
* @return
* - -1 is returned for a failure
* - 0 is returned for a pass
*
*****************************************************************************/
s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
{
u16 *TempAddr16;
u16 ValueIn = 0U;
s32 Index;
TempAddr16 = Addr;
Xil_AssertNonvoid(TempAddr16 != NULL);
for (Index = 0; Index < Length; Index++) {
switch (Kind) {
case XIL_TESTIO_LE:
Xil_Out16LE((INTPTR)TempAddr16, Value);
break;
case XIL_TESTIO_BE:
Xil_Out16BE((INTPTR)TempAddr16, Value);
break;
default:
Xil_Out16((INTPTR)TempAddr16, Value);
break;
}
ValueIn = Xil_In16((INTPTR)TempAddr16);
if ((Kind != 0) && (Swap != 0)) {
ValueIn = Swap16(ValueIn);
}
if (Value != ValueIn) {
return -1;
}
/* second round */
Xil_Out16((INTPTR)TempAddr16, Value);
switch (Kind) {
case XIL_TESTIO_LE:
ValueIn = Xil_In16LE((INTPTR)TempAddr16);
break;
case XIL_TESTIO_BE:
ValueIn = Xil_In16BE((INTPTR)TempAddr16);
break;
default:
ValueIn = Xil_In16((INTPTR)TempAddr16);
break;
}
if ((Kind != 0) && (Swap != 0)) {
ValueIn = Swap16(ValueIn);
}
if (Value != ValueIn) {
return -1;
}
TempAddr16 += sizeof(u16);
}
return 0;
}
/*****************************************************************************/
/**
*
* @brief Perform a destructive 32-bit wide register IO test. Each location
* is tested by sequentially writing a 32-bit wide register, reading
* the register, and comparing value. This function tests three kinds
* of register IO functions, normal register IO, little-endian register IO,
* and big-endian register IO. When testing little/big-endian IO,
* the function perform the following sequence, Xil_Out32LE/
* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
* Whether to swap the read-in value *before comparing is controlled
* by the 5th argument.
* @param Addr: a pointer to the region of memory to be tested.
* @param Length: Length of the block.
* @param Value: constant used for writing the memory.
* @param Kind: type of test. Acceptable values are:
* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
* @param Swap: indicates whether to byte swap the read-in value.
*
* @return
* - -1 is returned for a failure
* - 0 is returned for a pass
*
*****************************************************************************/
s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
{
u32 *TempAddr;
u32 ValueIn = 0U;
s32 Index;
TempAddr = Addr;
Xil_AssertNonvoid(TempAddr != NULL);
for (Index = 0; Index < Length; Index++) {
switch (Kind) {
case XIL_TESTIO_LE:
Xil_Out32LE((INTPTR)TempAddr, Value);
break;
case XIL_TESTIO_BE:
Xil_Out32BE((INTPTR)TempAddr, Value);
break;
default:
Xil_Out32((INTPTR)TempAddr, Value);
break;
}
ValueIn = Xil_In32((INTPTR)TempAddr);
if ((Kind != 0) && (Swap != 0)) {
ValueIn = Swap32(ValueIn);
}
if (Value != ValueIn) {
return -1;
}
/* second round */
Xil_Out32((INTPTR)TempAddr, Value);
switch (Kind) {
case XIL_TESTIO_LE:
ValueIn = Xil_In32LE((INTPTR)TempAddr);
break;
case XIL_TESTIO_BE:
ValueIn = Xil_In32BE((INTPTR)TempAddr);
break;
default:
ValueIn = Xil_In32((INTPTR)TempAddr);
break;
}
if ((Kind != 0) && (Swap != 0)) {
ValueIn = Swap32(ValueIn);
}
if (Value != ValueIn) {
return -1;
}
TempAddr += sizeof(u32);
}
return 0;
}

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/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xscutimer_selftest.c
* @addtogroup scutimer_v2_3
* @{
*
* Contains diagnostic self-test functions for the XScuTimer driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a nm 03/10/10 First release
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xscutimer.h"
/************************** Constant Definitions *****************************/
#define XSCUTIMER_SELFTEST_VALUE 0xA55AF00FU
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
*
* Run a self-test on the timer. This test clears the timer enable bit in
* the control register, writes to the timer load register and verifies the
* value read back matches the value written and restores the control register
* and the timer load register.
*
* @param InstancePtr is a pointer to the XScuTimer instance.
*
* @return
* - XST_SUCCESS if self-test was successful.
* - XST_FAILURE if self test was not successful.
*
* @note None.
*
******************************************************************************/
s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
{
u32 Register;
u32 CtrlOrig;
u32 LoadOrig;
s32 Status;
/*
* Assert to ensure the inputs are valid and the instance has been
* initialized.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Save the contents of the Control Register and stop the timer.
*/
CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET);
Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET, Register);
/*
* Save the contents of the Load Register.
* Load a new test value in the Load Register, read it back and
* compare it with the written value.
*/
LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
XSCUTIMER_LOAD_OFFSET);
XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
XSCUTIMER_LOAD_OFFSET);
/*
* Restore the contents of the Load Register and Control Register.
*/
XScuTimer_LoadTimer(InstancePtr, LoadOrig);
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
/*
* Return a Failure if the contents of the Load Register do not
* match with the value written to it.
*/
if (Register != XSCUTIMER_SELFTEST_VALUE) {
Status = (s32)XST_FAILURE;
}
else {
Status = (s32)XST_SUCCESS;
}
return Status;
}
/** @} */

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/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xdevcfg_hw.h
* @addtogroup devcfg_v3_7
* @{
*
* This file contains the hardware interface to the Device Config Interface.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a hvm 02/07/11 First release
* 2.01a nm 08/01/12 Added defines for the PS Version bits,
* removed the FIFO Flush bits from the
* Miscellaneous Control Reg
* 2.03a nm 04/19/13 Fixed CR# 703728.
* Updated the register definitions as per the latest TRM
* version UG585 (v1.4) November 16, 2012.
* 2.04a kpc 10/07/13 Added function prototype.
* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
* </pre>
*
******************************************************************************/
#ifndef XDCFG_HW_H /* prevent circular inclusions */
#define XDCFG_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
* Offsets of registers from the start of the device
* @{
*/
#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
/* @} */
/** @name Control Register Bit definitions
* @{
*/
#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
* Secure Reset
*/
#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
* Reset FPGA
*/
#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
* to FPGA every 4 PCAP
* cycles
*/
#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
* Status mask
*/
#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
* Debug Enable
*/
#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
* Debug Enable
*/
#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
* Enable
*/
#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
* Enable
*/
#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
/* @} */
/** @name Lock register bit definitions
* @{
*/
#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
* USER_MODE
*/
#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
* security config
* including: DAP_En,
* DBGEN,,
* NIDEN, SPNIEN
*/
/*@}*/
/** @name Config Register Bit definitions
* @{
*/
#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
* Threshold Mask
*/
#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
* Mask
*/
#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
* clock edge
*/
#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
* clock edge
*/
#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
* increment mask
*/
#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
* address increment
* mask
*/
/* @} */
/** @name Interrupt Status/Mask Register Bit definitions
* @{
*/
#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
* HIZ
*/
#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
* done
*/
#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
* configuration
*/
#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
* reset
*/
#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
* or Data or response
* timeout
*/
#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
* error
*/
#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
* response timeout
*/
#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
* error
*/
#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
* threshold */
#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
* threshold */
#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
* overflow
*/
#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
* transfers Done
*/
#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
* length error
*/
#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
* of Init Signal
*/
#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
* of Init Signal
*/
#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
XDCFG_IXR_AXI_WERR_MASK | \
XDCFG_IXR_AXI_RTO_MASK | \
XDCFG_IXR_AXI_RERR_MASK | \
XDCFG_IXR_RX_FIFO_OV_MASK | \
XDCFG_IXR_DMA_CMD_ERR_MASK |\
XDCFG_IXR_DMA_Q_OV_MASK | \
XDCFG_IXR_P2D_LEN_ERR_MASK |\
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
/* @} */
/** @name Status Register Bit definitions
* @{
*/
#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
* Queue full
*/
#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
* Queue empty
*/
#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
* completed DMA
* transfers
*/
#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
* during HIZ
*/
#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
* done
*/
#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
* config
*/
#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
* POR Status
*/
#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
* access
*/
#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
* reset status
*/
#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
* Status
*/
#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
/**< BBRAM key
* disable
*/
#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
* Enable Status
*/
#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
* Disable
* status
*/
/* @} */
/** @name DMA Source/Destination Transfer Length Register Bit definitions
* @{
*/
#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
/*@}*/
/** @name Miscellaneous Control Register Bit definitions
* @{
*/
#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
/* @} */
/** @name FIFO Threshold Bit definitions
* @{
*/
#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
/* @}*/
/* Miscellaneous constant values */
#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
* address
*/
#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Read the given register.
*
* @param BaseAddr is the base address of the device
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note C-style signature:
* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
*
*****************************************************************************/
#define XDcfg_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (RegOffset))
/****************************************************************************/
/**
*
* Write to the given register.
*
* @param BaseAddr is the base address of the device
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note C-style signature:
* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (RegOffset), (Data))
/************************** Function Prototypes ******************************/
/*
* Perform reset operation to the devcfg interface
*/
void XDcfg_ResetHw(u32 BaseAddr);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

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/******************************************************************************
* xen.h
*
* Guest OS interface to Xen.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Copyright (c) 2004, K A Fraser
*/
/*
Copyright DornerWorks 2016
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
following disclaimer.
THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __XEN_H_
#define __XEN_H_
/*
* HYPERCALLS
*/
/* `incontents 100 hcalls List of hypercalls
* ` enum hypercall_num { // __HYPERVISOR_* => HYPERVISOR_*()
*/
#define __HYPERVISOR_set_trap_table 0
#define __HYPERVISOR_mmu_update 1
#define __HYPERVISOR_set_gdt 2
#define __HYPERVISOR_stack_switch 3
#define __HYPERVISOR_set_callbacks 4
#define __HYPERVISOR_fpu_taskswitch 5
#define __HYPERVISOR_sched_op_compat 6 /* compat since 0x00030101 */
#define __HYPERVISOR_platform_op 7
#define __HYPERVISOR_set_debugreg 8
#define __HYPERVISOR_get_debugreg 9
#define __HYPERVISOR_update_descriptor 10
#define __HYPERVISOR_memory_op 12
#define __HYPERVISOR_multicall 13
#define __HYPERVISOR_update_va_mapping 14
#define __HYPERVISOR_set_timer_op 15
#define __HYPERVISOR_event_channel_op_compat 16 /* compat since 0x00030202 */
#define __HYPERVISOR_xen_version 17
#define __HYPERVISOR_console_io 18
#define __HYPERVISOR_physdev_op_compat 19 /* compat since 0x00030202 */
#define __HYPERVISOR_grant_table_op 20
#define __HYPERVISOR_vm_assist 21
#define __HYPERVISOR_update_va_mapping_otherdomain 22
#define __HYPERVISOR_iret 23 /* x86 only */
#define __HYPERVISOR_vcpu_op 24
#define __HYPERVISOR_set_segment_base 25 /* x86/64 only */
#define __HYPERVISOR_mmuext_op 26
#define __HYPERVISOR_xsm_op 27
#define __HYPERVISOR_nmi_op 28
#define __HYPERVISOR_sched_op 29
#define __HYPERVISOR_callback_op 30
#define __HYPERVISOR_xenoprof_op 31
#define __HYPERVISOR_event_channel_op 32
#define __HYPERVISOR_physdev_op 33
#define __HYPERVISOR_hvm_op 34
#define __HYPERVISOR_sysctl 35
#define __HYPERVISOR_domctl 36
#define __HYPERVISOR_kexec_op 37
#define __HYPERVISOR_tmem_op 38
#define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */
/* Architecture-specific hypercall definitions. */
#define __HYPERVISOR_arch_0 48
#define __HYPERVISOR_arch_1 49
#define __HYPERVISOR_arch_2 50
#define __HYPERVISOR_arch_3 51
#define __HYPERVISOR_arch_4 52
#define __HYPERVISOR_arch_5 53
#define __HYPERVISOR_arch_6 54
#define __HYPERVISOR_arch_7 55
/* ` } */
/*
* Commands to HYPERVISOR_console_io().
*/
#define CONSOLEIO_write 0
#define CONSOLEIO_read 1
/*
* Commands to HYPERVISOR_hvm_op
*/
#define HVMOP_set_param 0
#define HVMOP_get_param 1
/* DOMID_SELF is used in certain contexts to refer to oneself. */
#define DOMID_SELF (0x7FF0U)
#define XENMEM_add_to_physmap 7
/* Console debug shared memory ring and event channel */
#define HVM_PARAM_CONSOLE_PFN 17
#define HVM_PARAM_CONSOLE_EVTCHN 18
#endif /* __XEN_PUBLIC_XEN_H__ */

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>phased_array</name>
<comment>Created by Vitis v2021.2</comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdx.sdk.core.SdkProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

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/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xscutimer_hw.h
* @addtogroup scutimer_v2_3
* @{
*
* This file contains the hardware interface to the Timer.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a nm 03/10/10 First release
* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
* and interrupt registers
* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
* when the xstatus.h in the common driver overwrites
* the xstatus.h of the standalone BSP during the
* libgen.
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
#define XSCUTIMER_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_io.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
* Offsets of registers from the start of the device
* @{
*/
#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
Status Register */
/* @} */
/** @name Timer Control register
* This register bits control the prescaler, Intr enable,
* auto-reload and timer enable.
* @{
*/
#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
/* @} */
/** @name Interrupt Status register
* This register indicates the Timer counter register has reached zero.
* @{
*/
#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Write to the timer load register. This will also update the
* timer counter register with the new value. This macro can be used to
* change the time-out value.
*
* @param BaseAddr is the base address of the scu timer.
* @param Value is the count to be loaded in to the load register.
*
* @return None.
*
* @note C-style signature:
* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
*
******************************************************************************/
#define XScuTimer_SetLoadReg(BaseAddr, Value) \
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
/****************************************************************************/
/**
*
* Returns the current timer load register value.
*
* @param BaseAddr is the base address of the scu timer.
*
* @return Contents of the timer load register.
*
* @note C-style signature:
* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
*
******************************************************************************/
#define XScuTimer_GetLoadReg(BaseAddr) \
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
/****************************************************************************/
/**
*
* Write to the timer counter register.
*
* @param BaseAddr is the base address of the scu timer.
* @param Value is the count to be loaded in to the counter register.
*
* @return None.
*
* @note C-style signature:
* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
*
******************************************************************************/
#define XScuTimer_SetCounterReg(BaseAddr, Value) \
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
/****************************************************************************/
/**
*
* Returns the current timer counter register value.
*
* @param BaseAddr is the base address of the scu timer.
*
* @return Contents of the timer counter register.
*
* @note C-style signature:
u32 XScuTimer_GetCounterReg(u32 BaseAddr)
*
******************************************************************************/
#define XScuTimer_GetCounterReg(BaseAddr) \
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
/****************************************************************************/
/**
*
* Write to the timer load register. This will also update the
* timer counter register with the new value. This macro can be used to
* change the time-out value.
*
* @param BaseAddr is the base address of the scu timer.
* @param Value is the count to be loaded in to the load register.
*
* @return None.
*
* @note C-style signature:
* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
*
******************************************************************************/
#define XScuTimer_SetControlReg(BaseAddr, Value) \
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
/****************************************************************************/
/**
*
* Returns the current timer load register value.
*
* @param BaseAddr is the base address of the scu timer.
*
* @return Contents of the timer load register.
*
* @note C-style signature:
u32 XScuTimer_GetControlReg(u32 BaseAddr)
*
******************************************************************************/
#define XScuTimer_GetControlReg(BaseAddr) \
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
/****************************************************************************/
/**
*
* Write to the timer counter register.
*
* @param BaseAddr is the base address of the scu timer.
* @param Value is the count to be loaded in to the counter register.
*
* @return None.
*
* @note C-style signature:
* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
*
******************************************************************************/
#define XScuTimer_SetIntrReg(BaseAddr, Value) \
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
/****************************************************************************/
/**
*
* Returns the current timer counter register value.
*
* @param BaseAddr is the base address of the scu timer.
*
* @return Contents of the timer counter register.
*
* @note C-style signature:
u32 XScuTimer_GetIntrReg(u32 BaseAddr)
*
******************************************************************************/
#define XScuTimer_GetIntrReg(BaseAddr) \
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
/****************************************************************************/
/**
*
* Read from the given Timer register.
*
* @param BaseAddr is the base address of the device
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note C-style signature:
* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
*
*****************************************************************************/
#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (RegOffset))
/****************************************************************************/
/**
*
* Write to the given Timer register.
*
* @param BaseAddr is the base address of the device
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note C-style signature:
* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (RegOffset), (Data))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

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/******************************************************************************/
/**
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
* @file xil_util.h
* @addtogroup common_utilities Common Utility APIs
* @{
* @details
*
* This file contains xil utility functions declaration
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.4 mmd 04/21/19 First release.
* 6.5 kal 02/29/20 Added Xil_ConvertStringToHexBE API
* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API
* rpo 08/19/20 Added function for read, modify and write
* bsv 08/21/20 Added XSECURE_TEMPORAL_CHECK macro to add
* redundancy in security critical functions, to avoid
* glitches from altering the return values of security
* critical functions. The macro requires a label to be
* passed to "go to" in case of error.
* kpt 09/03/20 Added XSECURE_TEMPORAL_IMPL macro for redundancy
* kal 09/22/20 Changed the param type from const char to const char*
* to avoid copying key onto stack
* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
* Xil_MemCmp functions
* am 10/13/20 Resolved Coverity warning
* td 11/19/20 Updated XSECURE_TEMPORAL_CHECK and
* XSECURE_TEMPORAL_IMPL to fix MISRA C Rule 15.3
* 7.4 am 11/26/20 Added Xil_StrCpyRange function
* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
*
* </pre>
*
*****************************************************************************/
#ifndef XIL_UTIL_H_
#define XIL_UTIL_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_types.h"
#include "xil_io.h"
#include "xstatus.h"
/*************************** Constant Definitions *****************************/
#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U
#define XIL_SIZE_OF_BYTE_IN_BITS 8U
/* Maximum string length handled by Xil_ValidateHexStr function */
#define XIL_MAX_HEX_STR_LEN 512U
/****************** Macros (Inline Functions) Definitions *********************/
#ifdef __GNUC__
/******************************************************************************/
/**
*
* Updates the return value of the called function into Var and VarTmp variables
* for redundancy. This is to avoid glitches from altering the return values of
* security critical functions.
*
* @param Var is the variable which holds the return value of function
* executed
* @param VarTmp is the variable which holds the value stored in Var
* @param Function is the function to be executed
* @param Other params are arguments to the called function
*
* @return None
*
******************************************************************************/
#define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \
{ \
Var = XST_FAILURE; \
VarTmp = XST_FAILURE; \
Var = Function(__VA_ARGS__); \
VarTmp = Var; \
}
/******************************************************************************/
/**
*
* Adds redundancy while checking the status of the called function.
* This is to avoid glitches from altering the return values of security
* critical functions. The macro requires a label to be passed to "go to"
* in case of error.
*
* @param Label is the label defined in function and the control
* will jump to the label in case of XST_FAILURE
* @param Status is the variable which holds the return value of
* function executed
* @param Function is the function to be executed
* @param Other params are arguments to the called function
*
* @return None
*
******************************************************************************/
#define XSECURE_TEMPORAL_CHECK(Label, Status, Function, ...) \
{ \
volatile int StatusTmp = XST_FAILURE; \
XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \
if ((Status != XST_SUCCESS) || \
(StatusTmp != XST_SUCCESS)) { \
Status |= StatusTmp;\
goto Label; \
} \
}
#endif
/*************************** Function Prototypes ******************************/
/* Ceils the provided float value */
int Xil_Ceil(float Value);
/* Converts input character to nibble */
u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
/* Convert input hex string to array of 32-bits integers */
u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
/* Waits for specified event */
u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout);
/* Waits for specified events */
u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
u32 Timeout, u32* Events);
/* Validate input hex character */
u32 Xil_IsValidHexChar(const char *Ch);
/* Validate the input string contains only hexadecimal characters */
u32 Xil_ValidateHexStr(const char *HexStr);
/* Convert string to hex numbers in little enidian format */
u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len);
/* Returns length of the input string */
u32 Xil_Strnlen(const char *Str, u32 MaxLen);
/* Convert string to hex numbers in big endian format */
u32 Xil_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len);
/*Read, Modify and Write to an address*/
void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value);
/* Copies source string to destination string */
int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size);
/* Copies specified range from source string to destination string */
int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
u32 MaxDstLen);
/* Appends string2 to string1 */
int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size);
/* Copies Len bytes from source memory to destination memory */
int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len);
/* Compares Len bytes from memory1 and memory2 */
int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len);
/* Zeroizes the memory of given length */
int Xil_SecureZeroize(u8 *DataPtr, const u32 Length);
#ifdef __cplusplus
}
#endif
#endif /* XIL_UTIL_H_ */
/**
* @} End of "addtogroup common_utilities".
*/

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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2021.2
* DO NOT EDIT.
*
* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xscugic.h"
/*
* The configuration table for devices
*/
XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] =
{
{
XPAR_PS7_SCUGIC_0_DEVICE_ID,
XPAR_PS7_SCUGIC_0_BASEADDR,
XPAR_PS7_SCUGIC_0_DIST_BASEADDR,
{{0}} /**< Initialize the HandlerTable to 0 */
}
};

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/******************************************************************************
* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: MIT
*
******************************************************************************/
#include "xil_types.h"
/* Stub for iserror() function */
__attribute__((weak)) s32 _sys_iserror(s32 status)
{
if (status < 0) {
return 1;
}
return 0;
}

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/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xdevcfg_intr.c
* @addtogroup devcfg_v3_7
* @{
*
* Contains the implementation of interrupt related functions of the XDcfg
* driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a hvm 02/07/11 First release
* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
* set the mask instead of oring it with the
* value read from the interrupt status register
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xdevcfg.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
*
* This function enables the specified interrupts in the device.
*
* @param InstancePtr is a pointer to the XDcfg instance.
* @param Mask is the bit-mask of the interrupts to be enabled.
* Bit positions of 1 will be enabled. Bit positions of 0 will
* keep the previous setting. This mask is formed by OR'ing
* XDCFG_INT_* bits defined in xdevcfg_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
{
u32 RegValue;
/*
* Assert the arguments.
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Enable the specified interrupts in the Interrupt Mask Register.
*/
RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET);
RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET,
RegValue);
}
/****************************************************************************/
/**
*
* This function disables the specified interrupts in the device.
*
* @param InstancePtr is a pointer to the XDcfg instance.
* @param Mask is the bit-mask of the interrupts to be disabled.
* Bit positions of 1 will be disabled. Bit positions of 0 will
* keep the previous setting. This mask is formed by OR'ing
* XDCFG_INT_* bits defined in xdevcfg_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
{
u32 RegValue;
/*
* Assert the arguments.
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Disable the specified interrupts in the Interrupt Mask Register.
*/
RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET);
RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET,
RegValue);
}
/****************************************************************************/
/**
*
* This function returns the enabled interrupts read from the Interrupt Mask
* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
* to interpret the returned value.
*
* @param InstancePtr is a pointer to the XDcfg instance.
*
* @return A 32-bit value representing the contents of the IMR.
*
* @note None.
*
*****************************************************************************/
u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr)
{
/*
* Assert the arguments.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Return the value read from the Interrupt Mask Register.
*/
return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET));
}
/****************************************************************************/
/**
*
* This function returns the interrupt status read from Interrupt Status
* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
* to interpret the returned value.
*
* @param InstancePtr is a pointer to the XDcfg instance.
*
* @return A 32-bit value representing the contents of the Interrupt
* Status register.
*
* @note None.
*
*****************************************************************************/
u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
{
/*
* Assert the arguments.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Return the value read from the Interrupt Status register.
*/
return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET);
}
/****************************************************************************/
/**
*
* This function clears the specified interrupts in the Interrupt Status
* Register.
*
* @param InstancePtr is a pointer to the XDcfg instance.
* @param Mask is the bit-mask of the interrupts to be cleared.
* Bit positions of 1 will be cleared. Bit positions of 0 will not
* change the previous interrupt status. This mask is formed by
* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
{
/*
* Assert the arguments.
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET,
Mask);
}
/*****************************************************************************/
/**
* The interrupt handler for the Device Config Interface.
*
* Events are signaled to upper layer for proper handling.
*
*
* @param InstancePtr is a pointer to the XDcfg instance.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XDcfg_InterruptHandler(XDcfg *InstancePtr)
{
u32 IntrStatusReg;
/*
* Assert validates the input arguments.
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Read the Interrupt status register.
*/
IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET);
/*
* Write the status back to clear the interrupts so that no
* subsequent interrupts are missed while processing this interrupt.
* This also does the DMA acknowledgment automatically.
*/
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET, IntrStatusReg);
/*
* Signal application that there are events to handle.
*/
InstancePtr->StatusHandler(InstancePtr->CallBackRef,
IntrStatusReg);
}
/****************************************************************************/
/**
*
* This function sets the handler that will be called when an event (interrupt)
* occurs that needs application's attention.
*
* @param InstancePtr is a pointer to the XDcfg instance
* @param CallBackFunc is the address of the callback function.
* @param CallBackRef is a user data item that will be passed to the
* callback function when it is invoked.
*
* @return None.
*
* @note None.
*
*
*****************************************************************************/
void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
void *CallBackRef)
{
/*
* Asserts validate the input arguments
* CallBackRef not checked, no way to know what is valid
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(CallBackFunc != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc;
InstancePtr->CallBackRef = CallBackRef;
}
/** @} */

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/******************************************************************************
* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xil_misc_psreset_api.h
*
* This file contains the various register definitions and function prototypes for
* implementing the reset functionality of zynq ps devices
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b kpc 03/07/13 First release.
* </pre>
*
******************************************************************************/
#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
#define XIL_MISC_RESET_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/**
*@cond nocomments
*/
#define XDDRC_CTRL_BASEADDR 0xF8006000U
#define XSLCR_BASEADDR 0xF8000000U
/**< OCM configuration register */
#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
/**< SLCR unlock register */
#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
/**< SLCR GEM0 rx clock control register */
#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
/**< SLCR GEM1 rx clock control register */
#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
/**< SLCR GEM0 clock control register */
#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
/**< SLCR GEM1 clock control register */
#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
/**< SLCR SMC clock control register */
#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
/**< SLCR GEM reset control register */
#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
/**< SLCR USB0 clock control register */
#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
/**< SLCR USB1 clock control register */
#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
/**< SLCR USB1 reset control register */
#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
/**< SLCR SMC reset control register */
#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
/**< SLCR Level shifter enable register */
#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
/**< SLCR ARM pll control register */
#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
/**< SLCR DDR pll control register */
#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
/**< SLCR IO pll control register */
#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
/**< SLCR ARM pll configuration register */
#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
/**< SLCR DDR pll configuration register */
#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
/**< SLCR IO pll configuration register */
#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
/**< SLCR ARM clock control register */
#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
/**< SLCR DDR clock control register */
#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
/**< SLCR MIO pin address register */
#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
/**< SLCR DMAC reset control address register */
#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
/**< SLCR USB reset control address register */
/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
/**< SLCR GEM reset control address register */
/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
/**< SLCR SDIO reset control address register */
#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
/**< SLCR SPI reset control address register */
#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
/**< SLCR CAN reset control address register */
#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
/**< SLCR I2C reset control address register */
#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
/**< SLCR UART reset control address register */
#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
/**< SLCR GPIO reset control address register */
#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
/**< SLCR LQSPI reset control address register */
#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
/**< SLCR SMC reset control address register */
/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
/**< SLCR OCM reset control address register */
#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
/**< SMC mem controller clear config register */
#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
/**< SMC idlecount configuration register */
#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
/**< SMC ECC configuration register */
#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
/**< SMC ECC command 1 register */
#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
/**< SMC ECC command 2 register */
#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
/**< SLCR unlock code */
#define XSLCR_UNLOCK_CODE 0x0000DF0DU
/**< SMC mem clear configuration mask */
#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
/**< SMC ECC memconfig 1 reset value */
#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
/**< SMC ECC memcommand 1 reset value */
#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
/**< SMC ECC memcommand 2 reset value */
#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
/**< DDR controller reset bit mask */
#define XDDRPS_CTRL_RESET_MASK 0x00000001U
/**< SLCR OCM configuration reset value*/
#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
/**< SLCR OCM bank selection mask*/
#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
/**< SLCR level shifter enable mask*/
#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
/**< SLCR PLL register reset values */
#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
/**< SLCR MIO register default values */
#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
/**< SLCR Reset control registers default values */
#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
/**
*@endcond
*/
/**************************** Type Definitions *******************************/
/* the following data type is used to hold a null terminated version string
* consisting of the following format, "X.YYX"
*/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Performs reset operation to the ddr interface
*/
void XDdr_ResetHw(void);
/*
* Map the ocm region to post bootrom state
*/
void XOcm_Remap(void);
/*
* Performs the smc interface reset
*/
void XSmc_ResetHw(u32 BaseAddress);
/*
* updates the MIO registers with reset values
*/
void XSlcr_MioWriteResetValues(void);
/*
* updates the PLL and clock registers with reset values
*/
void XSlcr_PllWriteResetValues(void);
/*
* Disables the level shifters
*/
void XSlcr_DisableLevelShifters(void);
/*
* provides softreset to the GPIO interface
*/
void XSlcr_GpioPsReset(void);
/*
* provides softreset to the DMA interface
*/
void XSlcr_DmaPsReset(void);
/*
* provides softreset to the SMC interface
*/
void XSlcr_SmcPsReset(void);
/*
* provides softreset to the CAN interface
*/
void XSlcr_CanPsReset(void);
/*
* provides softreset to the Uart interface
*/
void XSlcr_UartPsReset(void);
/*
* provides softreset to the I2C interface
*/
void XSlcr_I2cPsReset(void);
/*
* provides softreset to the SPI interface
*/
void XSlcr_SpiPsReset(void);
/*
* provides softreset to the QSPI interface
*/
void XSlcr_QspiPsReset(void);
/*
* provides softreset to the USB interface
*/
void XSlcr_UsbPsReset(void);
/*
* provides softreset to the GEM interface
*/
void XSlcr_EmacPsReset(void);
/*
* provides softreset to the OCM interface
*/
void XSlcr_OcmReset(void);
#ifdef __cplusplus
}
#endif
#endif /* XIL_MISC_RESET_H */

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;/******************************************************************************
;* Copyright (c) 2020 - 2021 Xilinx, Inc. All rights reserved.
;*
;* SPDX-License-Identifier: MIT
;*
;******************************************************************************/
;/*****************************************************************************/
;/**
;* @file asm_vectors.S
;*
;* This file contains the initial vector table for the Cortex R5 processor
;* as per armclang compiler
;*
;* <pre>
;* MODIFICATION HISTORY:
;*
;* Ver Who Date Changes
;* ----- ------- -------- ---------------------------------------------------
;* 7.3 dp 06/25/20 Initial version for armclang
;* </pre>
;*
;* @note
;*
;* None.
;*
;******************************************************************************/
EXPORT _vector_table
IMPORT _boot
IMPORT FIQInterrupt
IMPORT IRQInterrupt
IMPORT SWInterrupt
IMPORT DataAbortInterrupt
IMPORT PrefetchAbortInterrupt
IMPORT UndefinedExceptionAddr
IMPORT UndefinedException
IMPORT DataAbortAddr
IMPORT PrefetchAbortAddr
EXPORT IRQHandler
AREA |vectors|, CODE
REQUIRE8 {TRUE}
PRESERVE8 {TRUE}
ENTRY ; Define this an entry point
_vector_table
ldr pc, =_boot
ldr pc, =Undefined
ldr pc, =SVCHandler
ldr pc, =PrefetchAbortHandler
ldr pc, =DataAbortHandler
NOP ;Placeholder for address exception vector
ldr pc, =IRQHandler
ldr pc, =FIQHandler
IRQHandler ;IRQ vector handler
stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
#ifndef __SOFTFP__
vpush {d0-d7} ;Store floating point registers/
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
#endif
bl IRQInterrupt ;IRQ vector
#ifndef __SOFTFP__
pop {r1} ;Restore floating point registers
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d0-d7}
#endif
ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
subs pc, lr, #4 ;adjust return
FIQHandler ;FIQ vector handler
stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
FIQLoop
bl FIQInterrupt ;FIQ vector
ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
subs pc, lr, #4 ;adjust return
Undefined ;Undefined handler
stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
ldr r0, =UndefinedExceptionAddr
sub r1, lr, #4
str r1, [r0] ;Store address of instruction causing undefined exception
bl UndefinedException ;UndefinedException: call C function here
ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
movs pc, lr
SVCHandler ;SWI handler
stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
tst r0, #0x20 ;check the T bit
ldrneh r0, [lr,#-2] ;Thumb mode
bicne r0, r0, #0xff00 ;Thumb mode
ldreq r0, [lr,#-4] ;ARM mode
biceq r0, r0, #0xff000000 ;ARM mode
bl SWInterrupt ;SWInterrupt: call C function here
ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
movs pc, lr ;adjust return
DataAbortHandler ;Data Abort handler
stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
ldr r0, =DataAbortAddr
sub r1, lr, #8
str r1, [r0] ;Stores instruction causing data abort
bl DataAbortInterrupt ;ataAbortInterrupt :call C function here
ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
subs pc, lr, #8 ;adjust return
PrefetchAbortHandler ;Prefetch Abort handler
stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
ldr r0, =PrefetchAbortAddr
sub r1, lr, #4
str r1, [r0] ;Stores instruction causing prefetch abort
bl PrefetchAbortInterrupt ;PrefetchAbortInterrupt: call C function here
ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
subs pc, lr, #4 ;adjust return
END

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/******************************************************************************
* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_standalone.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
* used under Xilinx standalone BSP.
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a rmm 03/21/02 First release
* 1.00a wgr 03/22/07 Converted to new coding style.
* 1.00a rpm 06/29/07 Added udelay macro for standalone
* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
* to in MICROBLAZE section
* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
*
* </pre>
*
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XENV_STANDALONE_H
#define XENV_STANDALONE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/******************************************************************************
*
* Get the processor dependent includes
*
******************************************************************************/
#include <string.h>
#if defined __MICROBLAZE__
# include "mb_interface.h"
# include "xparameters.h" /* XPAR constants used below in MB section */
#elif defined __PPC__
# include "sleep.h"
# include "xcache_l.h" /* also include xcache_l.h for caching macros */
#endif
/******************************************************************************
*
* MEMCPY / MEMSET related macros.
*
* The following are straight forward implementations of memset and memcpy.
*
* NOTE: memcpy may not work if source and target memory area are overlapping.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
* @note
* This implementation MAY BREAK work if source and target memory
* area are overlapping.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
/******************************************************************************
*
* TIME related macros
*
******************************************************************************/
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef s32 XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds. Not implemented without OS
* support.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#ifdef __PPC__
#define XENV_USLEEP(delay) usleep(delay)
#define udelay(delay) usleep(delay)
#else
#define XENV_USLEEP(delay)
#define udelay(delay)
#endif
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* Processor independent macros
*
******************************************************************************/
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
/******************************************************************************
*
* MicroBlaze case
*
* NOTE: Currently the following macros will only work on systems that contain
* only ONE MicroBlaze processor. Also, the macros will only be enabled if the
* system is built using a xparameters.h file.
*
******************************************************************************/
#if defined __MICROBLAZE__
/* Check if MicroBlaze data cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
#else
# define XCACHE_ENABLE_DCACHE()
# define XCACHE_DISABLE_DCACHE()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
/* Check if MicroBlaze instruction cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_ENABLE_ICACHE()
# define XCACHE_DISABLE_ICACHE()
#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
/******************************************************************************
*
* PowerPC case
*
* Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
* specific memory region (0x80000001). Each bit (0-30) in the regions
* bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
* range.
*
* regions --> cached address range
* ------------|--------------------------------------------------
* 0x80000000 | [0, 0x7FFFFFF]
* 0x00000001 | [0xF8000000, 0xFFFFFFFF]
* 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
*
******************************************************************************/
#elif defined __PPC__
#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifndef XENV_STANDALONE_H */
/**
*@endcond
*/

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/******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_io.h
*
* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
*
* The xil_io.h file contains the interface for the general I/O component, which
* encapsulates the Input/Output functions for the processors that do not
* require any special I/O handling.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
* ARM processors
* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
* CR-1049218
* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
* xil_io.h and made them as static inline
* am 10/13/20 Changed the return type of Xil_SecureOut32 function
* from u32 to int
* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
* when -Werror=conversion compiler flag is enabled
* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
*
* </pre>
******************************************************************************/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_printf.h"
#include "xstatus.h"
#if defined (__MICROBLAZE__)
#include "mb_interface.h"
#else
#include "xpseudo_asm.h"
#endif
/************************** Function Prototypes ******************************/
#ifdef ENABLE_SAFETY
extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
#endif
/***************** Macros (Inline Functions) Definitions *********************/
#if defined __GNUC__
#if defined (__MICROBLAZE__)
# define INST_SYNC mbar(0)
# define DATA_SYNC mbar(1)
# else
# define SYNCHRONIZE_IO dmb()
# define INST_SYNC isb()
# define DATA_SYNC dsb()
# endif
#else
# define SYNCHRONIZE_IO
# define INST_SYNC
# define DATA_SYNC
# define INST_SYNC
# define DATA_SYNC
#endif
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
#define INLINE inline
#else
#define INLINE __inline
#endif
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading
* from the specified address and returning the 8 bit Value read from
* that address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 8 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u8 Xil_In8(UINTPTR Addr)
{
return *(volatile u8 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading from
* the specified address and returning the 16 bit Value read from that
* address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 16 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u16 Xil_In16(UINTPTR Addr)
{
return *(volatile u16 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by
* reading from the specified address and returning the 32 bit Value
* read from that address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 32 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u32 Xil_In32(UINTPTR Addr)
{
return *(volatile u32 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading the
* 64 bit Value read from that address.
*
*
* @param Addr: contains the address to perform the input operation
*
* @return The 64 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u64 Xil_In64(UINTPTR Addr)
{
return *(volatile u64 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for an memory location by
* writing the 8 bit Value to the the specified address.
*
* @param Addr: contains the address to perform the output operation
* @param Value: contains the 8 bit Value to be written at the specified
* address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
{
/* write 8 bit value to specified address */
volatile u8 *LocalAddr = (volatile u8 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 16 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains the Value to be written at the specified address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
{
/* write 16 bit value to specified address */
volatile u16 *LocalAddr = (volatile u16 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 32 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains the 32 bit Value to be written at the specified
* address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
{
/* write 32 bit value to specified address */
#ifndef ENABLE_SAFETY
volatile u32 *LocalAddr = (volatile u32 *)Addr;
*LocalAddr = Value;
#else
XStl_RegUpdate(Addr, Value);
#endif
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 64 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains 64 bit Value to be written at the specified address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
{
/* write 64 bit value to specified address */
volatile u64 *LocalAddr = (volatile u64 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 32 bit Value to the the specified address and then reading it
* back to verify the value written in the register.
*
* @param Addr contains the address to perform the output operation
* @param Value contains 32 bit Value to be written at the specified address
*
* @return Returns Status
* - XST_SUCCESS on success
* - XST_FAILURE on failure
*
*****************************************************************************/
static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
{
int Status = XST_FAILURE;
u32 ReadReg;
u32 ReadRegTemp;
/* writing 32 bit value to specified address */
Xil_Out32(Addr, Value);
/* verify value written to specified address with multiple reads */
ReadReg = Xil_In32(Addr);
ReadRegTemp = Xil_In32(Addr);
if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
Status = XST_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/**
*
* @brief Perform a 16-bit endian conversion.
*
* @param Data: 16 bit value to be converted
*
* @return 16 bit Data with converted endianness
*
******************************************************************************/
static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
{
return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
}
/*****************************************************************************/
/**
*
* @brief Perform a 32-bit endian conversion.
*
* @param Data: 32 bit value to be converted
*
* @return 32 bit data with converted endianness
*
******************************************************************************/
static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
{
u16 LoWord;
u16 HiWord;
/* get each of the half words from the 32 bit word */
LoWord = (u16) (Data & 0x0000FFFFU);
HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
/* byte swap each of the 16 bit half words */
LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
/* swap the half words before returning the value */
return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
# else
# define Xil_In16BE Xil_In16
# define Xil_In32BE Xil_In32
# define Xil_Out16BE Xil_Out16
# define Xil_Out32BE Xil_Out32
# define Xil_Htons(Data) (Data)
# define Xil_Htonl(Data) (Data)
# define Xil_Ntohs(Data) (Data)
# define Xil_Ntohl(Data) (Data)
#endif
#else
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
#endif
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u16 Xil_In16BE(UINTPTR Addr)
#else
static INLINE u16 Xil_In16LE(UINTPTR Addr)
#endif
#else
static INLINE u16 Xil_In16BE(UINTPTR Addr)
#endif
{
u16 value = Xil_In16(Addr);
return Xil_EndianSwap16(value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#else
static INLINE u32 Xil_In32LE(UINTPTR Addr)
#endif
#else
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#endif
{
u32 value = Xil_In32(Addr);
return Xil_EndianSwap32(value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#else
static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
#endif
#else
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#endif
{
Value = Xil_EndianSwap16(Value);
Xil_Out16(Addr, Value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#else
static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
#endif
#else
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#endif
{
Value = Xil_EndianSwap32(Value);
Xil_Out32(Addr, Value);
}
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_io_interfacing_apis".
*/

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<?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="phased_array" location="/home/dylan/workspace/phased_array" platform="/home/dylan/workspace/phased_array_platform/export/phased_array_platform/phased_array_platform.xpfm" platformUID="xilinx:zybo-z7-20::0.0(custom)" systemProject="phased_array_system" sysConfig="phased_array_platform" runtime="C/C++" cpu="standalone_domain" cpuInstance="ps7_cortexa9_0" os="standalone" dimmRepoPath="" mssSignature="dd66451c26ba4b25b4502d5912a040ac">
<configuration name="Debug" id="xilinx.gnu.armv7.exe.debug.1531516350">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
</configuration>
<configuration name="Release" id="xilinx.gnu.armv7.exe.release.32331858" dirty="true">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
</configuration>
<template appTemplateName="hello_world"/>
</sdkproject:SdkProject>

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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xtime_l.c
*
* This file contains low level functions to get/set time from the Global Timer
* register in the ARM Cortex A9 MP core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------------
* 1.00a rp/sdm 11/03/09 Initial release.
* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
* displaying same warnings multiple times. It fixes CR#1090562.
* </pre>
*
* @note None.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xtime_l.h"
#include "xpseudo_asm.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
#pragma message ("For the sleep routines, Global timer is being used")
#endif
/****************************************************************************/
/**
* @brief Set the time in the Global Timer Counter Register.
*
* @param Xtime_Global: 64-bit Value to be written to the Global Timer
* Counter Register.
*
* @return None.
*
* @note When this function is called by any one processor in a multi-
* processor environment, reference time will reset/lost for all
* processors.
*
****************************************************************************/
void XTime_SetTime(XTime Xtime_Global)
{
/* Disable Global Timer */
Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
/* Updating Global Timer Counter Register */
Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
(u32)((u32)(Xtime_Global>>32U)));
/* Enable Global Timer */
Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
}
/****************************************************************************/
/**
* @brief Get the time from the Global Timer Counter Register.
*
* @param Xtime_Global: Pointer to the 64-bit location which will be
* updated with the current timer value.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XTime_GetTime(XTime *Xtime_Global)
{
u32 low;
u32 high;
/* Reading Global Timer Counter Register */
do
{
high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
} while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
*Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
}

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/******************************************************************************
* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_smc.h
*
* @addtogroup a53_64_smc_api Cortex A53 64bit EL1 Non-secure SMC Call
*
* Cortex A53 64bit EL1 Non-secure SMC Call provides a C wrapper for calling
* SMC from EL1 Non-secure application to request Secure monitor for secure
* services. SMC calling conventions should be followed.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.2 pkp 02/16/17 First release
* 6.4 mus 08/17/17 Added constant define for SMC ID , which is
* intended to read the version/idcode of the
* platform
* 7.1 mus 07/31/19 Added support for Versal
*
*
* </pre>
*
******************************************************************************/
#ifndef XIL_SMC_H /* prevent circular inclusions */
#define XIL_SMC_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "bspconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#if EL1_NONSECURE
/************************** Constant Definitions ****************************/
#define SMC_FID_START 0xF2000000
#define SMC_FID_END 0xFF00FFFF
#define XILSP_INIT_DONE 0xF2000000
#define ARITH_SMC_FID 0xF2000001
#define PM_IOCTL_SMC_FID 0xC2000022U
#define PM_IOCTL_OSPI_MUX_SELECT 0x15U
#define PIN_CONFIG_SCHMITT_CMOS 0x3U
#define PIN_CONFIG_TRI_STATE 0x6U
#define PM_OSPI_MUX_SEL_DMA 0x0
#define PM_OSPI_MUX_SEL_LINEAR 0x1
#define OSPI_NODE_ID 0x1822402a
#define PMC_GPIO_NODE_12_ID 0x14108027
#define PIN_REQUEST_SMC_FID 0xC200001CU
#define PIN_RELEASE_SMC_FID 0xC200001DU
#define PIN_SET_CONFIG_SMC_FID 0xC2000021U
#define PM_REQUEST_DEVICE_SMC_FID 0xC200000DU
#define PM_RELEASE_DEVICE_SMC_FID 0xC200000EU
#define PM_ASSERT_SMC_FID 0xC2000011U
#define PM_GETSTATUS_SMC_FID 0xC2000012U
#define MMIO_WRITE_SMC_FID 0xC2000013U
#define MMIO_READ_SMC_FID 0xC2000014U
#define GET_CHIPID_SMC_FID 0xC2000018U
/* GEM device IDs */
#define DEV_GEM_0 0x18224019
#define DEV_GEM_1 0x1822401a
/* GEM reference clock IDs */
#define CLK_GEM0_REF 0x8208058
#define CLK_GEM1_REF 0x8208059
/* PM API for setting clock divider */
#define PM_SET_DIVIDER_SMC_FID 0xC2000027U
/**************************** Type Definitions ******************************/
typedef struct {
u64 Arg0;
u64 Arg1;
u64 Arg2;
u64 Arg3;
} XSmc_OutVar;
/***************** Macros (Inline Functions) Definitions ********************/
#define XSave_X8toX17() \
__asm__ __volatile__ ("stp X8, X9, [sp,#-0x10]!");\
__asm__ __volatile__ ("stp X10, X11, [sp,#-0x10]!");\
__asm__ __volatile__ ("stp X12, X13, [sp,#-0x10]!");\
__asm__ __volatile__ ("stp X14, X15, [sp,#-0x10]!");\
__asm__ __volatile__ ("stp X16, X17, [sp,#-0x10]!");
#define XRestore_X8toX17() \
__asm__ __volatile__ ("ldp X16, X17, [sp], #0x10");\
__asm__ __volatile__ ("ldp X14, X15, [sp], #0x10");\
__asm__ __volatile__ ("ldp X12, X13, [sp], #0x10");\
__asm__ __volatile__ ("ldp X10, X11, [sp], #0x10");\
__asm__ __volatile__ ("ldp X8, X9, [sp], #0x10");
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
XSmc_OutVar Xil_Smc(u64 FunctionID, u64 Arg1, u64 Arg2, u64 Arg3, u64 Arg4,
u64 Arg5, u64 Arg6, u64 Arg7);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_SMC_H */
/**
* @} End of "addtogroup a53_64_smc_api".
*/

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########################################################################
# This is file which used to generate QEMU(which emulates A9 core)
# commandline(start_qemu.sh script) which used in Zynq HW-EMU.
# This is a template file which is packaged in platform and it gets
# processed by Vitis tool to generate meaningful file.
#
# This file contains flag and value pairs and they must be seperated
# into two lines value followed by flag. Below are the common/mandated
# flag and value pairs used for emulating Zynq. User can add more
# commandline args to this file depends on requirements.
#
# For more details on the QEMU commandline, please refer to
# the QEMU user guide UG1169.
########################################################################
#
#
# selects emulated machine
-M
arm-generic-fdt-7series
#
#
# redirect the serial port to specified char dev (i.e stdio, tcp port, file etc)
-serial
/dev/null
-serial
mon:stdio
#
#
# Register writes to SLCR block, to set PLL and CLK_CTRL regs (required for linux)
-device
loader,addr=0xf8000008,data=0xDF0D,data-len=4
-device
loader,addr=0xf8000140,data=0x00500801,data-len=4
-device
loader,addr=0xf800012c,data=0x1ed044d,data-len=4
-device
loader,addr=0xf8000108,data=0x0001e008,data-len=4
-device
loader,addr=0xF800025C,data=0x00000005,data-len=4
-device
loader,addr=0xF8000240,data=0x00000000,data-len=4
#
#
# Boot device selection
-boot
mode=5
#
#
# Guest software to load during boot up
-kernel
<elf>

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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file asm_vectors.S
*
* This file contains the initial vector table for the Cortex A9 processor
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 10/20/09 Initial version
* 3.05a sdm 02/02/12 Save lr when profiling is enabled
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
* 'xil_errata.h' for errata description
* 4.00a pkp 22/01/14 Modified return addresses for interrupt
* handlers (DataAbortHandler and SVCHandler)
* to fix CR#767251
* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
* abort and prefetch abort into DataAbortAddr and
* PrefetchAbortAddr for further use to fix CR#854523
* 5.4 pkp 12/03/15 Added handler for undefined exception
* 6.8 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now,
* saving/restoring of of HW floating point register
* would be done through newly introduced flag
* FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be
* configured based on the -mfpu-abi option in extra
* compiler flags.
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#include "xil_errata.h"
#include "bspconfig.h"
.org 0
.text
.globl _vector_table
.section .vectors
_vector_table:
B _boot
B Undefined
B SVCHandler
B PrefetchAbortHandler
B DataAbortHandler
NOP /* Placeholder for address exception vector*/
B IRQHandler
B FIQHandler
IRQHandler: /* IRQ vector handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
#if FPU_HARD_FLOAT_ABI_ENABLED
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
#endif
#ifdef PROFILING
ldr r2, =prof_pc
subs r3, lr, #0
str r3, [r2]
#endif
bl IRQInterrupt /* IRQ vector */
#if FPU_HARD_FLOAT_ABI_ENABLED
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
#endif
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
FIQHandler: /* FIQ vector handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
#if FPU_HARD_FLOAT_ABI_ENABLED
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
#endif
FIQLoop:
bl FIQInterrupt /* FIQ vector */
#if FPU_HARD_FLOAT_ABI_ENABLED
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
#endif
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* adjust return */
Undefined: /* Undefined handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
ldr r0, =UndefinedExceptionAddr
sub r1, lr, #4
str r1, [r0] /* Store address of instruction causing undefined exception */
bl UndefinedException /* UndefinedException: call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
movs pc, lr
SVCHandler: /* SWI handler */
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
tst r0, #0x20 /* check the T bit */
ldrneh r0, [lr,#-2] /* Thumb mode */
bicne r0, r0, #0xff00 /* Thumb mode */
ldreq r0, [lr,#-4] /* ARM mode */
biceq r0, r0, #0xff000000 /* ARM mode */
bl SWInterrupt /* SWInterrupt: call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
movs pc, lr /*return to the next instruction after the SWI instruction */
DataAbortHandler: /* Data Abort handler */
#ifdef CONFIG_ARM_ERRATA_775420
dsb
#endif
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
ldr r0, =DataAbortAddr
sub r1, lr, #8
str r1, [r0] /* Stores instruction causing data abort */
bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */
PrefetchAbortHandler: /* Prefetch Abort handler */
#ifdef CONFIG_ARM_ERRATA_775420
dsb
#endif
stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
ldr r0, =PrefetchAbortAddr
sub r1, lr, #4
str r1, [r0] /* Stores instruction causing prefetch abort */
bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
.end

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/******************************************************************************
* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache.h
*
* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
*
* Cache functions provide access to cache related operations such as flush
* and invalidate for instruction and data caches. It gives option to perform
* the cache operations on a single cacheline, a range of memory and an entire
* cache.
*
* @{
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 01/29/10 First release
* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
* APIs.
* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_CACHE_H
#define XIL_CACHE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __GNUC__
#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
#elif defined (__ICCARM__)
#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
#endif
/**
*@endcond
*/
void Xil_DCacheEnable(void);
void Xil_DCacheDisable(void);
void Xil_DCacheInvalidate(void);
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
void Xil_DCacheFlush(void);
void Xil_DCacheFlushRange(INTPTR adr, u32 len);
void Xil_ICacheEnable(void);
void Xil_ICacheDisable(void);
void Xil_ICacheInvalidate(void);
void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
#ifdef __cplusplus
}
#endif
#endif
/**
* @} End of "addtogroup a9_cache_apis".
*/

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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_exception.c
*
* This file contains implementation of exception related driver functions.
*
* @addtogroup microblaze_exception_apis Microblaze exception APIs
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 hbm 07/28/09 Initial release
* 6.2 ms 02/20/17 Fixed compilation warning. This is a fix for CR-969126.
*
* </pre>
*
******************************************************************************/
#include "xil_types.h"
#include "xil_exception.h"
#include "microblaze_exceptions_g.h"
#include "microblaze_interrupts_i.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*@cond nocomments
*/
extern void microblaze_enable_exceptions(void);
extern void microblaze_disable_exceptions(void);
extern void microblaze_enable_interrupts(void);
extern void microblaze_disable_interrupts(void);
/**
* Currently HAL is an augmented part of standalone BSP, so the old definition
* of MB_ExceptionVectorTableEntry is used here.
*/
typedef struct {
Xil_ExceptionHandler Handler;
void *CallBackRef;
} MB_ExceptionVectorTableEntry;
#ifdef __cplusplus
}
#endif
/**
* @endcond
*/
/************************** Variable Definitions *****************************/
extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[XIL_EXCEPTION_ID_INT];
extern MB_InterruptVectorTableEntry MB_InterruptVectorTable[MB_INTERRUPT_VECTOR_TABLE_ENTRIES];
/****************************************************************************/
/**
* @brief This function is a stub handler that is the default handler that gets
* called if the application has not setup a handler for a specific
* exception. The function interface has to match the interface
* specified for a handler even though none of the arguments are used.
*
* @param Data: unused by this function.
*
*****************************************************************************/
static void Xil_ExceptionNullHandler(void *Data)
{
(void) Data;
}
/****************************************************************************/
/**
* @brief Initialize exception handling for the processor. The exception
* vector table is setup with the stub handler for all exceptions.
*
*****************************************************************************/
void Xil_ExceptionInit(void)
{
/*
* there is no need to setup the exception table here
*/
}
/****************************************************************************/
/**
* @brief Enable Exceptions.
*
******************************************************************************/
void Xil_ExceptionEnable(void)
{
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
microblaze_enable_exceptions();
#endif
microblaze_enable_interrupts();
}
/****************************************************************************/
/**
* @brief Disable Exceptions.
*
******************************************************************************/
void Xil_ExceptionDisable(void)
{
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
microblaze_disable_exceptions();
#endif
microblaze_disable_interrupts();
}
/*****************************************************************************/
/**
*@brief Makes the connection between the Id of the exception source and the
* associated handler that is to run when the exception is recognized.
* The argument provided in this call as the DataPtr is used as the
* argument for the handler when it is called.
*
* @param Id: contains the 32 bit ID of the exception source and should
* be XIL_EXCEPTION_INT or be in the range of 0 to XIL_EXCEPTION_LAST.
* See xil_mach_exception.h for further information.
* @param Handler: handler function to be registered for exception
* @param Data: a reference to data that will be passed to the handler
* when it gets called.
*
****************************************************************************/
void Xil_ExceptionRegisterHandler(u32 Id, Xil_ExceptionHandler Handler,
void *Data)
{
if (Id == XIL_EXCEPTION_ID_INT) {
MB_InterruptVectorTable[0].Handler = Handler;
MB_InterruptVectorTable[0].CallBackRef = Data;
}
else {
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
MB_ExceptionVectorTable[Id].Handler = Handler;
MB_ExceptionVectorTable[Id].CallBackRef = Data;
#endif
}
}
/*****************************************************************************/
/**
* @brief Removes the handler for a specific exception Id. The stub handler
* is then registered for this exception Id.
*
* @param Id: contains the 32 bit ID of the exception source and should
* be XIL_EXCEPTION_INT or in the range of 0 to XIL_EXCEPTION_LAST.
* See xexception_l.h for further information.
*
****************************************************************************/
void Xil_ExceptionRemoveHandler(u32 Id)
{
if (Id == XIL_EXCEPTION_ID_INT) {
MB_InterruptVectorTable[0].Handler = Xil_ExceptionNullHandler;
MB_InterruptVectorTable[0].CallBackRef = NULL;
}
else {
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
MB_ExceptionVectorTable[Id].Handler =
Xil_ExceptionNullHandler;
MB_ExceptionVectorTable[Id].CallBackRef = NULL;
#endif
}
}
/**
* @} End of "addtogroup microblaze_exception_apis".
*/

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/******************************************************************************
* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcpu_cortexa9.h
* @addtogroup cpu_cortexa9_v2_11
* @{
* @details
*
* dummy file
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
* parameter of cpu_cortexa9 in xparameters.h
# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into
# extra compiler flags. Now, user can remove default flags
# from extra compiler flags. It fixes CR#998768.
******************************************************************************/
/** @} */

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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xtime_l.h
* @addtogroup a9_time_apis Cortex A9 Time Functions
*
* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
* counter increases by one at every two processor cycles. These functions can
* be used to get/set time in the global timer.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------------
* 1.00a rp/sdm 11/03/09 Initial release.
* 3.06a sgd 05/15/12 Updated get/set time functions to make use Global Timer
* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
* implementation
* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
* displaying same warnings multiple times. It fixes CR#1090562.
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XTIME_H /* prevent circular inclusions */
#define XTIME_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xparameters.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
typedef u64 XTime;
/************************** Constant Definitions *****************************/
#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
#define GTIMER_CONTROL_OFFSET 0x08U
#if defined (SLEEP_TIMER_BASEADDR)
#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
#else
/* Global Timer is always clocked at half of the CPU frequency */
#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
#endif
/************************** Variable Definitions *****************************/
/**
*@endcond
*/
/************************** Function Prototypes ******************************/
void XTime_SetTime(XTime Xtime_Global);
void XTime_GetTime(XTime *Xtime_Global);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XTIME_H */
/**
* @} End of "addtogroup a9_time_apis".
*/

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/*******************************************************************************
* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
#ifndef __XLPD_SLCR_H__
#define __XLPD_SLCR_H__
#ifdef __cplusplus
extern "C" {
#endif
/**
*@cond nocomments
*/
/**
* XlpdSlcr Base Address
*/
#define XLPD_SLCR_BASEADDR 0xFF410000UL
/**
* Register: XlpdSlcrWprot0
*/
#define XLPD_SLCR_WPROT0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000000UL )
#define XLPD_SLCR_WPROT0_RSTVAL 0x00000000UL
#define XLPD_SLCR_WPROT0_ACT_SHIFT 0UL
#define XLPD_SLCR_WPROT0_ACT_WIDTH 1UL
#define XLPD_SLCR_WPROT0_ACT_MASK 0x00000001UL
#define XLPD_SLCR_WPROT0_ACT_DEFVAL 0x0UL
/**
* Register: XlpdSlcrCtrl
*/
#define XLPD_SLCR_CTRL ( ( XLPD_SLCR_BASEADDR ) + 0x00000004UL )
#define XLPD_SLCR_CTRL_RSTVAL 0x00000000UL
#define XLPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
#define XLPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
#define XLPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
#define XLPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
/**
* Register: XlpdSlcrIsr
*/
#define XLPD_SLCR_ISR ( ( XLPD_SLCR_BASEADDR ) + 0x00000008UL )
#define XLPD_SLCR_ISR_RSTVAL 0x00000000UL
#define XLPD_SLCR_ISR_ADDR_DECODE_ERR_SHIFT 0UL
#define XLPD_SLCR_ISR_ADDR_DECODE_ERR_WIDTH 1UL
#define XLPD_SLCR_ISR_ADDR_DECODE_ERR_MASK 0x00000001UL
#define XLPD_SLCR_ISR_ADDR_DECODE_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrImr
*/
#define XLPD_SLCR_IMR ( ( XLPD_SLCR_BASEADDR ) + 0x0000000CUL )
#define XLPD_SLCR_IMR_RSTVAL 0x00000001UL
#define XLPD_SLCR_IMR_ADDR_DECODE_ERR_SHIFT 0UL
#define XLPD_SLCR_IMR_ADDR_DECODE_ERR_WIDTH 1UL
#define XLPD_SLCR_IMR_ADDR_DECODE_ERR_MASK 0x00000001UL
#define XLPD_SLCR_IMR_ADDR_DECODE_ERR_DEFVAL 0x1UL
/**
* Register: XlpdSlcrIer
*/
#define XLPD_SLCR_IER ( ( XLPD_SLCR_BASEADDR ) + 0x00000010UL )
#define XLPD_SLCR_IER_RSTVAL 0x00000000UL
#define XLPD_SLCR_IER_ADDR_DECODE_ERR_SHIFT 0UL
#define XLPD_SLCR_IER_ADDR_DECODE_ERR_WIDTH 1UL
#define XLPD_SLCR_IER_ADDR_DECODE_ERR_MASK 0x00000001UL
#define XLPD_SLCR_IER_ADDR_DECODE_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrIdr
*/
#define XLPD_SLCR_IDR ( ( XLPD_SLCR_BASEADDR ) + 0x00000014UL )
#define XLPD_SLCR_IDR_RSTVAL 0x00000000UL
#define XLPD_SLCR_IDR_ADDR_DECODE_ERR_SHIFT 0UL
#define XLPD_SLCR_IDR_ADDR_DECODE_ERR_WIDTH 1UL
#define XLPD_SLCR_IDR_ADDR_DECODE_ERR_MASK 0x00000001UL
#define XLPD_SLCR_IDR_ADDR_DECODE_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrItr
*/
#define XLPD_SLCR_ITR ( ( XLPD_SLCR_BASEADDR ) + 0x00000018UL )
#define XLPD_SLCR_ITR_RSTVAL 0x00000000UL
#define XLPD_SLCR_ITR_ADDR_DECODE_ERR_SHIFT 0UL
#define XLPD_SLCR_ITR_ADDR_DECODE_ERR_WIDTH 1UL
#define XLPD_SLCR_ITR_ADDR_DECODE_ERR_MASK 0x00000001UL
#define XLPD_SLCR_ITR_ADDR_DECODE_ERR_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSafetyChk0
*/
#define XLPD_SLCR_SAFETY_CHK0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000060UL )
#define XLPD_SLCR_SAFETY_CHK0_RSTVAL 0x00000000UL
#define XLPD_SLCR_SAFETY_CHK0_CHK_VAL_SHIFT 0UL
#define XLPD_SLCR_SAFETY_CHK0_CHK_VAL_WIDTH 32UL
#define XLPD_SLCR_SAFETY_CHK0_CHK_VAL_MASK 0xffffffffUL
#define XLPD_SLCR_SAFETY_CHK0_CHK_VAL_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSafetyChk1
*/
#define XLPD_SLCR_SAFETY_CHK1 ( ( XLPD_SLCR_BASEADDR ) + 0x00000064UL )
#define XLPD_SLCR_SAFETY_CHK1_RSTVAL 0x00000000UL
#define XLPD_SLCR_SAFETY_CHK1_CHK_VAL_SHIFT 0UL
#define XLPD_SLCR_SAFETY_CHK1_CHK_VAL_WIDTH 32UL
#define XLPD_SLCR_SAFETY_CHK1_CHK_VAL_MASK 0xffffffffUL
#define XLPD_SLCR_SAFETY_CHK1_CHK_VAL_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSafetyChk2
*/
#define XLPD_SLCR_SAFETY_CHK2 ( ( XLPD_SLCR_BASEADDR ) + 0x00000068UL )
#define XLPD_SLCR_SAFETY_CHK2_RSTVAL 0x00000000UL
#define XLPD_SLCR_SAFETY_CHK2_CHK_VAL_SHIFT 0UL
#define XLPD_SLCR_SAFETY_CHK2_CHK_VAL_WIDTH 32UL
#define XLPD_SLCR_SAFETY_CHK2_CHK_VAL_MASK 0xffffffffUL
#define XLPD_SLCR_SAFETY_CHK2_CHK_VAL_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSafetyChk3
*/
#define XLPD_SLCR_SAFETY_CHK3 ( ( XLPD_SLCR_BASEADDR ) + 0x0000006CUL )
#define XLPD_SLCR_SAFETY_CHK3_RSTVAL 0x00000000UL
#define XLPD_SLCR_SAFETY_CHK3_CHK_VAL_SHIFT 0UL
#define XLPD_SLCR_SAFETY_CHK3_CHK_VAL_WIDTH 32UL
#define XLPD_SLCR_SAFETY_CHK3_CHK_VAL_MASK 0xffffffffUL
#define XLPD_SLCR_SAFETY_CHK3_CHK_VAL_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSmidCfgAdma0
*/
#define XLPD_SLCR_SMID_CFG_ADMA0 ( ( XLPD_SLCR_BASEADDR ) + 0x00000074UL )
#define XLPD_SLCR_SMID_CFG_ADMA0_RSTVAL 0x00000000UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH7_SHIFT 7UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH7_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH7_MASK 0x00000080UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH7_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH6_SHIFT 6UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH6_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH6_MASK 0x00000040UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH6_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH5_SHIFT 5UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH5_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH5_MASK 0x00000020UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH5_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH4_SHIFT 4UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH4_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH4_MASK 0x00000010UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH4_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH3_SHIFT 3UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH3_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH3_MASK 0x00000008UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH3_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH2_SHIFT 2UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH2_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH2_MASK 0x00000004UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH2_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH1_SHIFT 1UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH1_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH1_MASK 0x00000002UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH1_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH0_SHIFT 0UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH0_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH0_MASK 0x00000001UL
#define XLPD_SLCR_SMID_CFG_ADMA0_CH0_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSmidCfgAdma1
*/
#define XLPD_SLCR_SMID_CFG_ADMA1 ( ( XLPD_SLCR_BASEADDR ) + 0x00000078UL )
#define XLPD_SLCR_SMID_CFG_ADMA1_RSTVAL 0x00000000UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH7_SHIFT 7UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH7_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH7_MASK 0x00000080UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH7_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH6_SHIFT 6UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH6_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH6_MASK 0x00000040UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH6_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH5_SHIFT 5UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH5_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH5_MASK 0x00000020UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH5_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH4_SHIFT 4UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH4_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH4_MASK 0x00000010UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH4_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH3_SHIFT 3UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH3_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH3_MASK 0x00000008UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH3_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH2_SHIFT 2UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH2_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH2_MASK 0x00000004UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH2_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH1_SHIFT 1UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH1_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH1_MASK 0x00000002UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH1_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH0_SHIFT 0UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH0_WIDTH 1UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH0_MASK 0x00000001UL
#define XLPD_SLCR_SMID_CFG_ADMA1_CH0_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSmidCfgRpu0
*/
#define XLPD_SLCR_SMID_CFG_RPU0 ( ( XLPD_SLCR_BASEADDR ) + 0x0000007CUL )
#define XLPD_SLCR_SMID_CFG_RPU0_RSTVAL 0x00000000UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH3_SHIFT 6UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH3_WIDTH 2UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH3_MASK 0x000000c0UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH3_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH2_SHIFT 4UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH2_WIDTH 2UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH2_MASK 0x00000030UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH2_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH1_SHIFT 2UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH1_WIDTH 2UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH1_MASK 0x0000000cUL
#define XLPD_SLCR_SMID_CFG_RPU0_CH1_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH0_SHIFT 0UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH0_WIDTH 2UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH0_MASK 0x00000003UL
#define XLPD_SLCR_SMID_CFG_RPU0_CH0_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSmidCfgRpu1
*/
#define XLPD_SLCR_SMID_CFG_RPU1 ( ( XLPD_SLCR_BASEADDR ) + 0x00000080UL )
#define XLPD_SLCR_SMID_CFG_RPU1_RSTVAL 0x00000000UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH3_SHIFT 6UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH3_WIDTH 2UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH3_MASK 0x000000c0UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH3_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH2_SHIFT 4UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH2_WIDTH 2UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH2_MASK 0x00000030UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH2_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH1_SHIFT 2UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH1_WIDTH 2UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH1_MASK 0x0000000cUL
#define XLPD_SLCR_SMID_CFG_RPU1_CH1_DEFVAL 0x0UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH0_SHIFT 0UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH0_WIDTH 2UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH0_MASK 0x00000003UL
#define XLPD_SLCR_SMID_CFG_RPU1_CH0_DEFVAL 0x0UL
/**
* Register: XlpdSlcrHsdpCfg
*/
#define XLPD_SLCR_HSDP_CFG ( ( XLPD_SLCR_BASEADDR ) + 0x00000088UL )
#define XLPD_SLCR_HSDP_CFG_RSTVAL 0x00000000UL
#define XLPD_SLCR_HSDP_CFG_LINK_REACH_SHIFT 3UL
#define XLPD_SLCR_HSDP_CFG_LINK_REACH_WIDTH 1UL
#define XLPD_SLCR_HSDP_CFG_LINK_REACH_MASK 0x00000008UL
#define XLPD_SLCR_HSDP_CFG_LINK_REACH_DEFVAL 0x0UL
#define XLPD_SLCR_HSDP_CFG_AURORA_XPIPE_SEL_SHIFT 2UL
#define XLPD_SLCR_HSDP_CFG_AURORA_XPIPE_SEL_WIDTH 1UL
#define XLPD_SLCR_HSDP_CFG_AURORA_XPIPE_SEL_MASK 0x00000004UL
#define XLPD_SLCR_HSDP_CFG_AURORA_XPIPE_SEL_DEFVAL 0x0UL
#define XLPD_SLCR_HSDP_CFG_SEL_AUR_PCIE_SHIFT 1UL
#define XLPD_SLCR_HSDP_CFG_SEL_AUR_PCIE_WIDTH 1UL
#define XLPD_SLCR_HSDP_CFG_SEL_AUR_PCIE_MASK 0x00000002UL
#define XLPD_SLCR_HSDP_CFG_SEL_AUR_PCIE_DEFVAL 0x0UL
#define XLPD_SLCR_HSDP_CFG_SEL_AUR_PL_SHIFT 0UL
#define XLPD_SLCR_HSDP_CFG_SEL_AUR_PL_WIDTH 1UL
#define XLPD_SLCR_HSDP_CFG_SEL_AUR_PL_MASK 0x00000001UL
#define XLPD_SLCR_HSDP_CFG_SEL_AUR_PL_DEFVAL 0x0UL
/**
* Register: XlpdSlcrXocm2Cfg
*/
#define XLPD_SLCR_XOCM2_CFG ( ( XLPD_SLCR_BASEADDR ) + 0x0000008CUL )
#define XLPD_SLCR_XOCM2_CFG_RSTVAL 0x00000000UL
#define XLPD_SLCR_XOCM2_CFG_PRESENT_SHIFT 0UL
#define XLPD_SLCR_XOCM2_CFG_PRESENT_WIDTH 1UL
#define XLPD_SLCR_XOCM2_CFG_PRESENT_MASK 0x00000001UL
#define XLPD_SLCR_XOCM2_CFG_PRESENT_DEFVAL 0x0UL
/**
* Register: XlpdSlcrAdmaCfg
*/
#define XLPD_SLCR_ADMA_CFG ( ( XLPD_SLCR_BASEADDR ) + 0x0000200CUL )
#define XLPD_SLCR_ADMA_CFG_RSTVAL 0x00000048UL
#define XLPD_SLCR_ADMA_CFG_BUS_WIDTH_SHIFT 5UL
#define XLPD_SLCR_ADMA_CFG_BUS_WIDTH_WIDTH 2UL
#define XLPD_SLCR_ADMA_CFG_BUS_WIDTH_MASK 0x00000060UL
#define XLPD_SLCR_ADMA_CFG_BUS_WIDTH_DEFVAL 0x2UL
#define XLPD_SLCR_ADMA_CFG_NUM_CH_SHIFT 0UL
#define XLPD_SLCR_ADMA_CFG_NUM_CH_WIDTH 5UL
#define XLPD_SLCR_ADMA_CFG_NUM_CH_MASK 0x0000001fUL
#define XLPD_SLCR_ADMA_CFG_NUM_CH_DEFVAL 0x8UL
/**
* Register: XlpdSlcrAfiFs
*/
#define XLPD_SLCR_AFI_FS ( ( XLPD_SLCR_BASEADDR ) + 0x00009000UL )
#define XLPD_SLCR_AFI_FS_RSTVAL 0x00000200UL
#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT 8UL
#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH 2UL
#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_MASK 0x00000300UL
#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL 0x2UL
/**
* Register: XlpdSlcrCciCfg0
*/
#define XLPD_SLCR_CCI_CFG_0 ( ( XLPD_SLCR_BASEADDR ) + 0x0000A000UL )
#define XLPD_SLCR_CCI_CFG_0_RSTVAL 0x00030fc0UL
#define XLPD_SLCR_CCI_CFG_0_SPR_SHIFT 28UL
#define XLPD_SLCR_CCI_CFG_0_SPR_WIDTH 4UL
#define XLPD_SLCR_CCI_CFG_0_SPR_MASK 0xf0000000UL
#define XLPD_SLCR_CCI_CFG_0_SPR_DEFVAL 0x0UL
#define XLPD_SLCR_CCI_CFG_0_ACCHANNEL_EN_MSB_SHIFT 12UL
#define XLPD_SLCR_CCI_CFG_0_ACCHANNEL_EN_MSB_WIDTH 6UL
#define XLPD_SLCR_CCI_CFG_0_ACCHANNEL_EN_MSB_MASK 0x0003f000UL
#define XLPD_SLCR_CCI_CFG_0_ACCHANNEL_EN_MSB_DEFVAL 0x30UL
#define XLPD_SLCR_CCI_CFG_0_ACCHANNEL_EN_LSB_SHIFT 6UL
#define XLPD_SLCR_CCI_CFG_0_ACCHANNEL_EN_LSB_WIDTH 6UL
#define XLPD_SLCR_CCI_CFG_0_ACCHANNEL_EN_LSB_MASK 0x00000fc0UL
#define XLPD_SLCR_CCI_CFG_0_ACCHANNEL_EN_LSB_DEFVAL 0x3fUL
#define XLPD_SLCR_CCI_CFG_0_QOS_OVERRIDE_SHIFT 0UL
#define XLPD_SLCR_CCI_CFG_0_QOS_OVERRIDE_WIDTH 6UL
#define XLPD_SLCR_CCI_CFG_0_QOS_OVERRIDE_MASK 0x0000003fUL
#define XLPD_SLCR_CCI_CFG_0_QOS_OVERRIDE_DEFVAL 0x0UL
/**
* Register: XlpdSlcrCciCfg1
*/
#define XLPD_SLCR_CCI_CFG_1 ( ( XLPD_SLCR_BASEADDR ) + 0x0000A004UL )
#define XLPD_SLCR_CCI_CFG_1_RSTVAL 0x000023c0UL
#define XLPD_SLCR_CCI_CFG_1_MST_DEPEND_ON_SL_SHIFT 12UL
#define XLPD_SLCR_CCI_CFG_1_MST_DEPEND_ON_SL_WIDTH 6UL
#define XLPD_SLCR_CCI_CFG_1_MST_DEPEND_ON_SL_MASK 0x0003f000UL
#define XLPD_SLCR_CCI_CFG_1_MST_DEPEND_ON_SL_DEFVAL 0x2UL
#define XLPD_SLCR_CCI_CFG_1_BRST_SPLIT_ALL_SHIFT 6UL
#define XLPD_SLCR_CCI_CFG_1_BRST_SPLIT_ALL_WIDTH 6UL
#define XLPD_SLCR_CCI_CFG_1_BRST_SPLIT_ALL_MASK 0x00000fc0UL
#define XLPD_SLCR_CCI_CFG_1_BRST_SPLIT_ALL_DEFVAL 0xfUL
#define XLPD_SLCR_CCI_CFG_1_ORDERED_WR_OBSERVE_SHIFT 0UL
#define XLPD_SLCR_CCI_CFG_1_ORDERED_WR_OBSERVE_WIDTH 6UL
#define XLPD_SLCR_CCI_CFG_1_ORDERED_WR_OBSERVE_MASK 0x0000003fUL
#define XLPD_SLCR_CCI_CFG_1_ORDERED_WR_OBSERVE_DEFVAL 0x0UL
/**
* Register: XlpdSlcrCci
*/
#define XLPD_SLCR_CCI ( ( XLPD_SLCR_BASEADDR ) + 0x0000A008UL )
#define XLPD_SLCR_CCI_RSTVAL 0x00000000UL
#define XLPD_SLCR_CCI_ADDRMAP_SHIFT 0UL
#define XLPD_SLCR_CCI_ADDRMAP_WIDTH 25UL
#define XLPD_SLCR_CCI_ADDRMAP_MASK 0x01ffffffUL
#define XLPD_SLCR_CCI_ADDRMAP_DEFVAL 0x0UL
/**
* Register: XlpdSlcrSmmu
*/
#define XLPD_SLCR_SMMU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A020UL )
#define XLPD_SLCR_SMMU_RSTVAL 0x0000007fUL
#define XLPD_SLCR_SMMU_CFG_NORMIZE_SHIFT 9UL
#define XLPD_SLCR_SMMU_CFG_NORMIZE_WIDTH 1UL
#define XLPD_SLCR_SMMU_CFG_NORMIZE_MASK 0x00000200UL
#define XLPD_SLCR_SMMU_CFG_NORMIZE_DEFVAL 0x0UL
#define XLPD_SLCR_SMMU_INTEG_SEC_OVERRIDE_SHIFT 8UL
#define XLPD_SLCR_SMMU_INTEG_SEC_OVERRIDE_WIDTH 1UL
#define XLPD_SLCR_SMMU_INTEG_SEC_OVERRIDE_MASK 0x00000100UL
#define XLPD_SLCR_SMMU_INTEG_SEC_OVERRIDE_DEFVAL 0x0UL
#define XLPD_SLCR_SMMU_CFG_CTTW_SHIFT 7UL
#define XLPD_SLCR_SMMU_CFG_CTTW_WIDTH 1UL
#define XLPD_SLCR_SMMU_CFG_CTTW_MASK 0x00000080UL
#define XLPD_SLCR_SMMU_CFG_CTTW_DEFVAL 0x0UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU6_SHIFT 6UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU6_WIDTH 1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU6_MASK 0x00000040UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU6_DEFVAL 0x1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU5_SHIFT 5UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU5_WIDTH 1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU5_MASK 0x00000020UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU5_DEFVAL 0x1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU4_SHIFT 4UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU4_WIDTH 1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU4_MASK 0x00000010UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU4_DEFVAL 0x1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU3_SHIFT 3UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU3_WIDTH 1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU3_MASK 0x00000008UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU3_DEFVAL 0x1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU2_SHIFT 2UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU2_WIDTH 1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU2_MASK 0x00000004UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU2_DEFVAL 0x1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU1_SHIFT 1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU1_WIDTH 1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU1_MASK 0x00000002UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU1_DEFVAL 0x1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU0_SHIFT 0UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU0_WIDTH 1UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU0_MASK 0x00000001UL
#define XLPD_SLCR_SMMU_SYSBARDISABLE_TBU0_DEFVAL 0x1UL
/**
* Register: XlpdSlcrApu
*/
#define XLPD_SLCR_APU ( ( XLPD_SLCR_BASEADDR ) + 0x0000A040UL )
#define XLPD_SLCR_APU_RSTVAL 0x00000001UL
#define XLPD_SLCR_APU_BRDC_BARRIER_SHIFT 3UL
#define XLPD_SLCR_APU_BRDC_BARRIER_WIDTH 1UL
#define XLPD_SLCR_APU_BRDC_BARRIER_MASK 0x00000008UL
#define XLPD_SLCR_APU_BRDC_BARRIER_DEFVAL 0x0UL
#define XLPD_SLCR_APU_BRDC_CMNT_SHIFT 2UL
#define XLPD_SLCR_APU_BRDC_CMNT_WIDTH 1UL
#define XLPD_SLCR_APU_BRDC_CMNT_MASK 0x00000004UL
#define XLPD_SLCR_APU_BRDC_CMNT_DEFVAL 0x0UL
#define XLPD_SLCR_APU_BRDC_INNER_SHIFT 1UL
#define XLPD_SLCR_APU_BRDC_INNER_WIDTH 1UL
#define XLPD_SLCR_APU_BRDC_INNER_MASK 0x00000002UL
#define XLPD_SLCR_APU_BRDC_INNER_DEFVAL 0x0UL
#define XLPD_SLCR_APU_BRDC_OUTER_SHIFT 0UL
#define XLPD_SLCR_APU_BRDC_OUTER_WIDTH 1UL
#define XLPD_SLCR_APU_BRDC_OUTER_MASK 0x00000001UL
#define XLPD_SLCR_APU_BRDC_OUTER_DEFVAL 0x1UL
/**
*@endcond
*/
#ifdef __cplusplus
}
#endif
#endif /* __XLPD_SLCR_H__ */

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/******************************************************************************
* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/* The errno variable is stored in the reentrancy structure. This
function returns its address for use by the macro errno defined in
errno.h. */
#include <errno.h>
#include <reent.h>
#include "xil_types.h"
sint32 * __errno (void);
sint32 *
__errno (void)
{
return &_REENT->_errno;
}

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/******************************************************************************
* Copyright (c) 2004 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file mb_interface.h
*
* @addtogroup microblaze_pseudo_asm_macro Microblaze Pseudo-asm Macros and Interrupt Handling APIs
*
* Microblaze BSP includes macros to provide convenient access to various registers
* in the MicroBlaze processor. Some of these macros are very useful within
* exception handlers for retrieving information about the exception.Also,
* the interrupt handling functions help manage interrupt handling on MicroBlaze
* processor devices.To use these functions, include the header file
* mb_interface.h in your source code
*
* @{
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef _MICROBLAZE_INTERFACE_H_
#define _MICROBLAZE_INTERFACE_H_
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_exception.h"
#ifdef __cplusplus
extern "C" {
#endif
extern void microblaze_enable_interrupts(void); /* Enable Interrupts */
extern void microblaze_disable_interrupts(void); /* Disable Interrupts */
extern void microblaze_enable_icache(void); /* Enable Instruction Cache */
extern void microblaze_disable_icache(void); /* Disable Instruction Cache */
extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */
extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */
extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */
extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */
/**
*@endcond
*/
extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); /* Register exception handler */
/**
*@cond nocomments
*/
extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
extern void microblaze_invalidate_icache_range(UINTPTR cacheaddr, u32 len); /* Invalidate a part of the icache */
extern void microblaze_invalidate_dcache_range(UINTPTR cacheaddr, u32 len); /* Invalidate a part of the dcache */
extern void microblaze_flush_dcache_range(UINTPTR cacheaddr, u32 len); /* Flush a part of the dcache */
extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */
extern void microblaze_flush_cache_ext(void); /* Flush cache ext */
extern void microblaze_flush_cache_ext_range(UINTPTR cacheaddr,
u32 len); /* Flush cache ext range */
extern void microblaze_invalidate_cache_ext_range(UINTPTR cacheaddr,
u32 len); /* Invalidate cache ext range */
/* Deprecated */
extern void microblaze_update_icache (s32 , s32 , s32 ) __attribute__((deprecated));
extern void microblaze_init_icache_range (s32 , s32 ) __attribute__((deprecated));
extern void microblaze_update_dcache (s32 , s32 , s32 ) __attribute__((deprecated));
extern void microblaze_init_dcache_range (s32 , s32 ) __attribute__((deprecated));
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
/* FSL Access Macros */
/* Blocking Data Read and Write to FSL no. id */
#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Data Read and Write to FSL no. id */
#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
/* Blocking Control Read and Write to FSL no. id */
#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
/* Non-blocking Control Read and Write to FSL no. id */
#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
/* Polling versions of FSL access macros. This makes the FSL access interruptible */
#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")
#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
/* FSL valid and error check macros. */
#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
"andi\t%0,%0,0x10" : "=d" (error))
/* Pseudo assembler instructions */
#define clz(v) ({ u32 _rval = 0U; \
__asm__ __volatile__ ( \
"clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
); \
_rval; \
})
#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
#define mb_hibernate() ({ __asm__ __volatile__ ("hibernate\t"); })
#define mb_suspend() ({ __asm__ __volatile__ ("suspend\t"); })
#define mb_swapb(v) ({ u32 _rval = 0U; \
__asm__ __volatile__ ( \
"swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
#define mb_swaph(v) ({ u32 _rval = 0U; \
__asm__ __volatile__ ( \
"swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
); \
_rval; \
})
/** @name Microblaze pseudo-asm macros
*
* The following is a summary of the MicroBlaze processor pseudo-asm macros.
* @{
*/
/**
Return value from the general purpose register (GPR) rn.
@param rn General purpose register to be read.
*/
#define mfgpr(rn) ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the MSR.
*/
#define mfmsr() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rmsr\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the Exception Address Register (EAR).
*/
#define mfear() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rear\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfeare() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfse\t%0,rear\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the Exception Status Register (ESR).
*/
#define mfesr() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,resr\n" : "=d"(_rval) \
); \
_rval; \
})
/**
Return the current value of the Floating Point Status (FPS).
*/
#define mffsr() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rfsr\n" : "=d"(_rval) \
); \
_rval; \
})
/*@}*/
#define mfpvr(rn) ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpvre(rn) ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfse\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfbtr() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rbtr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfedr() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,redr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfpid() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rpid\n" : "=d"(_rval)\
); \
_rval; \
})
#define mfzpr() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rzpr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbx() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbx\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlblo() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlblo\n" : "=d"(_rval) \
); \
_rval; \
})
#define mftlbhi() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rtlbhi\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfslr() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rslr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mfshr() ({ UINTPTR _rval = 0U; \
__asm__ __volatile__ ( \
"mfs\t%0,rshr\n" : "=d"(_rval) \
); \
_rval; \
})
#define mtgpr(rn, v) ({ __asm__ __volatile__ ( \
"or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
); \
})
#define mtmsr(v) ({ __asm__ __volatile__ ( \
"mts\trmsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtfsr(v) ({ __asm__ __volatile__ ( \
"mts\trfsr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtpid(v) ({ __asm__ __volatile__ ( \
"mts\trpid,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtzpr(v) ({ __asm__ __volatile__ ( \
"mts\trzpr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlblo(v) ({ __asm__ __volatile__ ( \
"mts\trtlblo,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbhi(v) ({ __asm__ __volatile__ ( \
"mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mttlbsx(v) ({ __asm__ __volatile__ ( \
"mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtslr(v) ({ __asm__ __volatile__ ( \
"mts\trslr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define mtshr(v) ({ __asm__ __volatile__ ( \
"mts\trshr,%0\n\tnop\n" :: "d" (v) \
); \
})
#define lwx(address) ({ u32 _rval = 0U; \
__asm__ __volatile__ ( \
"lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lwr(address) ({ u32 _rval = 0U; \
__asm__ __volatile__ ( \
"lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lwea(lladdr) ({ u32 _rval = 0U; \
__asm__ __volatile__ ( \
"lwea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define lhur(address) ({ u32 _rval = 0U; \
__asm__ __volatile__ ( \
"lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lhuea(lladdr) ({ u32 _rval = 0U; \
__asm__ __volatile__ ( \
"lhuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define lbur(address) ({ u32 _rval = 0U; \
__asm__ __volatile__ ( \
"lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
); \
_rval; \
})
#define lbuea(lladdr) ({ u32 _rval = 0U; \
__asm__ __volatile__ ( \
"lbuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
); \
_rval; \
})
#define swx(address, data) ({ __asm__ __volatile__ ( \
"swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define swr(address, data) ({ __asm__ __volatile__ ( \
"swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define swea(lladdr, data) ({ __asm__ __volatile__ ( \
"swea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define shr(address, data) ({ __asm__ __volatile__ ( \
"shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define shea(lladdr, data) ({ __asm__ __volatile__ ( \
"shea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define sbr(address, data) ({ __asm__ __volatile__ ( \
"sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
); \
})
#define sbea(lladdr, data) ({ __asm__ __volatile__ ( \
"sbea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
); \
})
#define microblaze_getfpex_operand_a() ({ \
extern u32 mb_fpex_op_a; \
mb_fpex_op_a; \
})
#define microblaze_getfpex_operand_b() ({ \
extern u32 mb_fpex_op_b; \
mb_fpex_op_b; \
})
/* Deprecated MicroBlaze FSL macros */
#define microblaze_bread_datafsl(val, id) getfsl(val,id)
#define microblaze_bwrite_datafsl(val, id) putfsl(val,id)
#define microblaze_nbread_datafsl(val, id) ngetfsl(val,id)
#define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id)
#define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id)
#define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id)
#define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id)
#define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id)
#ifdef __cplusplus
}
#endif
#endif // _MICROBLAZE_INTERFACE_H_
/**
*@endcond
*/
/**
* @} End of "addtogroup microblaze_pseudo_asm_macro".
*/

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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops_intr.c
* @addtogroup gpiops_v3_9
* @{
*
* This file contains functions related to GPIO interrupt handling.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sv 01/18/10 First Release
* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
* passed to API's. CR# 822636
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* 3.1 aru 07/13/18 Ressolved doxygen reported warnings. CR# 1006331.
* 3.4 aru 08/09/18 Ressolved cppcheck warnings.
* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
* in safety mode and modified the code such as
* Use of mixed mode arithmetic,Declared the pointer param
* as Pointer to const,Casting operation to a pointer,
* Literal value requires a U suffix.
* 3.5 sne 03/14/19 Added Versal support.
* 3.5 sne 03/20/19 Fixed multiple interrupts problem CR#1024556.
* 3.6 sne 06/12/19 Fixed IAR compiler warning.
* 3.6 sne 08/14/19 Added interrupt handler support on versal.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xgpiops.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/****************************************************************************/
/**
*
* This function enables the interrupts for the specified pins in the specified
* bank.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
* @param Mask is the bit mask of the pins for which interrupts are to
* be enabled. Bit positions of 1 will be enabled. Bit positions
* of 0 will keep the previous setting.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertVoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTEN_OFFSET, Mask);
}
/****************************************************************************/
/**
*
* This function enables the interrupt for the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number for which the interrupt is to be enabled.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
u32 IntrReg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
IntrReg = ((u32)1 << (u32)PinNumber);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTEN_OFFSET, IntrReg);
}
/****************************************************************************/
/**
*
* This function disables the interrupts for the specified pins in the specified
* bank.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
* @param Mask is the bit mask of the pins for which interrupts are
* to be disabled. Bit positions of 1 will be disabled. Bit
* positions of 0 will keep the previous setting.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertVoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, Mask);
}
/****************************************************************************/
/**
*
* This function disables the interrupts for the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number for which the interrupt is to be disabled.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
u32 IntrReg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
IntrReg = ((u32)1 << (u32)PinNumber);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, IntrReg);
}
/****************************************************************************/
/**
*
* This function returns the interrupt enable status for a bank.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
*
* @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1
* indicate that the interrupt for that pin is enabled, bit
* positions with 0 indicate that the interrupt for that pin is
* disabled.
*
* @note None.
*
*****************************************************************************/
u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank)
{
u32 IntrMask;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTMASK_OFFSET);
return (~IntrMask);
}
/****************************************************************************/
/**
*
* This function returns whether interrupts are enabled for the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number for which the interrupt enable status
* is to be known.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
*
* @return
* - TRUE if the interrupt is enabled.
* - FALSE if the interrupt is disabled.
*
* @note None.
*
*****************************************************************************/
u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
u32 IntrReg;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTMASK_OFFSET);
return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? (u32)FALSE : (u32)TRUE);
}
/****************************************************************************/
/**
*
* This function returns interrupt status read from Interrupt Status Register.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
*
* @return The value read from Interrupt Status Register.
*
* @note None.
*
*****************************************************************************/
u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET);
}
/****************************************************************************/
/**
*
* This function returns interrupt enable status of the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number for which the interrupt enable status
* is to be known.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
*
* @return
* - TRUE if the interrupt has occurred.
* - FALSE if the interrupt has not occurred.
*
* @note None.
*
*****************************************************************************/
u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
u32 IntrReg;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET);
return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? (u32)TRUE : (u32)FALSE);
}
/****************************************************************************/
/**
*
* This function clears pending interrupt(s) with the provided mask. This
* function should be called after the software has serviced the interrupts
* that are pending.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
* @param Mask is the mask of the interrupts to be cleared. Bit positions
* of 1 will be cleared. Bit positions of 0 will not change the
* previous interrupt status.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertVoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
/* Clear the currently pending interrupts. */
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET, Mask);
}
/****************************************************************************/
/**
*
* This function clears the specified pending interrupt. This function should be
* called after the software has serviced the interrupts that are pending.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number for which the interrupt status is to be
* cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
u32 IntrReg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
/* Clear the specified pending interrupts. */
IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET);
IntrReg &= ((u32)1 << PinNumber);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET, IntrReg);
}
/****************************************************************************/
/**
*
* This function is used for setting the Interrupt Type, Interrupt Polarity and
* Interrupt On Any for the specified GPIO Bank pins.
*
* @param InstancePtr is a pointer to an XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
* @param IntrType is the 32 bit mask of the interrupt type.
* 0 means Level Sensitive and 1 means Edge Sensitive.
* @param IntrPolarity is the 32 bit mask of the interrupt polarity.
* 0 means Active Low or Falling Edge and 1 means Active High or
* Rising Edge.
* @param IntrOnAny is the 32 bit mask of the interrupt trigger for
* edge triggered interrupts. 0 means trigger on single edge using
* the configured interrupt polarity and 1 means trigger on both
* edges.
*
* @return None.
*
* @note This function is used for setting the interrupt related
* properties of all the pins in the specified bank. The previous
* state of the pins is not maintained.
* To change the Interrupt properties of a single GPIO pin, use the
* function XGpioPs_SetPinIntrType().
*
*****************************************************************************/
void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
u32 IntrPolarity, u32 IntrOnAny)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertVoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET, IntrType);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET, IntrPolarity);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET, IntrOnAny);
}
/****************************************************************************/
/**
*
* This function is used for getting the Interrupt Type, Interrupt Polarity and
* Interrupt On Any for the specified GPIO Bank pins.
*
* @param InstancePtr is a pointer to an XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
* @param IntrType returns the 32 bit mask of the interrupt type.
* 0 means Level Sensitive and 1 means Edge Sensitive.
* @param IntrPolarity returns the 32 bit mask of the interrupt
* polarity. 0 means Active Low or Falling Edge and 1 means
* Active High or Rising Edge.
* @param IntrOnAny returns the 32 bit mask of the interrupt trigger for
* edge triggered interrupts. 0 means trigger on single edge using
* the configured interrupt polarity and 1 means trigger on both
* edges.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
u32 *IntrPolarity, u32 *IntrOnAny)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertVoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
*IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET);
*IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET);
*IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET);
}
/****************************************************************************/
/**
*
* This function is used for setting the IRQ Type of a single GPIO pin.
*
* @param InstancePtr is a pointer to an XGpioPs instance.
* @param Pin is the pin number whose IRQ type is to be set.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
* @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
* defined in xgpiops.h to specify the IRQ type.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
{
u32 IntrTypeReg;
u32 IntrPolReg;
u32 IntrOnAnyReg;
u8 Bank;
u8 PinNumber;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET);
IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET);
IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET);
switch (IrqType) {
case XGPIOPS_IRQ_TYPE_EDGE_RISING:
IntrTypeReg |= ((u32)1 << (u32)PinNumber);
IntrPolReg |= ((u32)1 << (u32)PinNumber);
IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
break;
case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
IntrTypeReg |= ((u32)1 << (u32)PinNumber);
IntrPolReg &= ~((u32)1 << (u32)PinNumber);
IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
break;
case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
IntrTypeReg |= ((u32)1 << (u32)PinNumber);
IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
break;
case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
IntrPolReg |= ((u32)1 << (u32)PinNumber);
break;
case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
IntrPolReg &= ~((u32)1 << (u32)PinNumber);
break;
default:
/**< Default statement is added for MISRA C compliance. */
break;
}
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET, IntrPolReg);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
}
/****************************************************************************/
/**
*
* This function returns the IRQ Type of a given GPIO pin.
*
* @param InstancePtr is a pointer to an XGpioPs instance.
* @param Pin is the pin number whose IRQ type is to be obtained.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
*
* @return None.
*
* @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
* returned by this function.
*
*****************************************************************************/
u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin)
{
u32 IntrType;
u32 IntrPol;
u32 IntrOnAny;
u8 Bank;
u8 PinNumber;
u8 IrqType;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
if (IntrType == ((u32)1 << PinNumber)) {
IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
if (IntrOnAny == ((u32)1 << PinNumber)) {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
} else if (IntrPol == ((u32)1 << PinNumber)) {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
} else {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
}
} else {
IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
if (IntrPol == ((u32)1 << PinNumber)) {
IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
} else {
IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
}
}
return IrqType;
}
/*****************************************************************************/
/**
*
* This function sets the status callback function. The callback function is
* called by the XGpioPs_IntrHandler when an interrupt occurs.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param CallBackRef is the upper layer callback reference passed back
* when the callback function is invoked.
* @param FuncPointer is the pointer to the callback function.
*
*
* @return None.
*
* @note The handler is called within interrupt context, so it should do
* its work quickly and queue potentially time-consuming work to a
* task-level thread.
*
******************************************************************************/
void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
XGpioPs_Handler FuncPointer)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FuncPointer != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
InstancePtr->Handler = FuncPointer;
InstancePtr->CallBackRef = CallBackRef;
}
/*****************************************************************************/
/**
*
* This function is the interrupt handler for GPIO interrupts.It checks the
* interrupt status registers of all the banks to determine the actual bank in
* which an interrupt has been triggered. It then calls the upper layer callback
* handler set by the function XGpioPs_SetBankHandler(). The callback is called
* when an interrupt
*
* @param InstancePtr is a pointer to the XGpioPs instance.
*
* @return None.
*
* @note This function does not save and restore the processor context
* such that the user must provide this processing.
*
******************************************************************************/
void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
{
u8 Bank;
u32 IntrStatus;
u32 IntrEnabled;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
if(Bank == XGPIOPS_TWO) {
continue;
}
} else {
if((Bank == XGPIOPS_ONE) || (Bank == XGPIOPS_TWO)) {
continue;
}
}
#endif
IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank);
if ((IntrStatus & IntrEnabled) != (u32)0) {
XGpioPs_IntrClear(InstancePtr, Bank,
(IntrStatus & IntrEnabled));
InstancePtr->Handler(InstancePtr->
CallBackRef, Bank,
(IntrStatus & IntrEnabled));
}
}
}
/** @} */

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<?xml version="1.0" encoding="UTF-8"?>
<sdx:platform sdx:vendor="xilinx.com"
sdx:library="sdx"
sdx:name="phased_array_platform"
sdx:version="1.0"
sdx:schemaVersion="1.0"
xmlns:sdx="http://www.xilinx.com/sdx">
<sdx:description>
phased_array_platform
</sdx:description>
<sdx:systemConfigurations sdx:defaultConfiguration="phased_array_platform">
<sdx:configuration sdx:name="phased_array_platform"
sdx:displayName="phased_array_platform"
sdx:defaultProcessorGroup="standalone_domain"
sdx:runtimes="cpp">
<sdx:description>phased_array_platform</sdx:description>
<sdx:bootImages sdx:default="standard">
<sdx:image sdx:name="standard"
sdx:bif="phased_array_platform/boot/phased_array_platform.bif"
sdx:readme="phased_array_platform/boot/generic.readme"
sdx:qemuArguments="phased_array_platform/qemu/qemu_args.txt"
/>
<sdx:image sdx:name="standalone_domain"
sdx:bif="phased_array_platform/boot/phased_array_platform.bif"
sdx:readme="phased_array_platform/boot/generic.readme"
sdx:qemuArguments="phased_array_platform/standalone_domain/qemu/qemu_args.txt"
/>
</sdx:bootImages>
<sdx:processorGroup sdx:name="standalone_domain"
sdx:displayName="standalone on ps7_cortexa9_0"
sdx:cpuType="cortex-a9"
sdx:cpuInstance="ps7_cortexa9_0">
<sdx:os sdx:name="standalone"
sdx:displayName="standalone"
sdx:bspLibraryPaths="phased_array_platform/standalone_domain/bsplib/lib"
sdx:bspIncludePaths="phased_array_platform/standalone_domain/bspinclude/include"
sdx:bspConfig="phased_array_platform/standalone_domain/system.mss"
/>
</sdx:processorGroup>
</sdx:configuration>
</sdx:systemConfigurations>
</sdx:platform>

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@ -1,573 +0,0 @@
/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xreg_cortexa9.h
*
* This header file contains definitions for using inline assembler code. It is
* written specifically for the GNU, ARMCC compiler.
*
* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
* with the positions of the bits within the registers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 1.00a ecm/sdm 10/20/09 First release
* </pre>
*
******************************************************************************/
#ifndef XREG_CORTEXA9_H
#define XREG_CORTEXA9_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
*@cond nocomments
*/
/* GPRs */
#define XREG_GPR0 r0
#define XREG_GPR1 r1
#define XREG_GPR2 r2
#define XREG_GPR3 r3
#define XREG_GPR4 r4
#define XREG_GPR5 r5
#define XREG_GPR6 r6
#define XREG_GPR7 r7
#define XREG_GPR8 r8
#define XREG_GPR9 r9
#define XREG_GPR10 r10
#define XREG_GPR11 r11
#define XREG_GPR12 r12
#define XREG_GPR13 r13
#define XREG_GPR14 r14
#define XREG_GPR15 r15
#define XREG_CPSR cpsr
/* Coprocessor number defines */
#define XREG_CP0 0
#define XREG_CP1 1
#define XREG_CP2 2
#define XREG_CP3 3
#define XREG_CP4 4
#define XREG_CP5 5
#define XREG_CP6 6
#define XREG_CP7 7
#define XREG_CP8 8
#define XREG_CP9 9
#define XREG_CP10 10
#define XREG_CP11 11
#define XREG_CP12 12
#define XREG_CP13 13
#define XREG_CP14 14
#define XREG_CP15 15
/* Coprocessor control register defines */
#define XREG_CR0 cr0
#define XREG_CR1 cr1
#define XREG_CR2 cr2
#define XREG_CR3 cr3
#define XREG_CR4 cr4
#define XREG_CR5 cr5
#define XREG_CR6 cr6
#define XREG_CR7 cr7
#define XREG_CR8 cr8
#define XREG_CR9 cr9
#define XREG_CR10 cr10
#define XREG_CR11 cr11
#define XREG_CR12 cr12
#define XREG_CR13 cr13
#define XREG_CR14 cr14
#define XREG_CR15 cr15
/* Current Processor Status Register (CPSR) Bits */
#define XREG_CPSR_THUMB_MODE 0x20
#define XREG_CPSR_MODE_BITS 0x1F
#define XREG_CPSR_SYSTEM_MODE 0x1F
#define XREG_CPSR_UNDEFINED_MODE 0x1B
#define XREG_CPSR_DATA_ABORT_MODE 0x17
#define XREG_CPSR_SVC_MODE 0x13
#define XREG_CPSR_IRQ_MODE 0x12
#define XREG_CPSR_FIQ_MODE 0x11
#define XREG_CPSR_USER_MODE 0x10
#define XREG_CPSR_IRQ_ENABLE 0x80
#define XREG_CPSR_FIQ_ENABLE 0x40
#define XREG_CPSR_N_BIT 0x80000000
#define XREG_CPSR_Z_BIT 0x40000000
#define XREG_CPSR_C_BIT 0x20000000
#define XREG_CPSR_V_BIT 0x10000000
/* CP15 defines */
#if defined (__GNUC__) || defined (__ICCARM__)
/* C0 Register defines */
#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
/* C1 Register Defines */
#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
#else /* RVCT */
/* C0 Register defines */
#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
/* C1 Register Defines */
#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
#endif
/* XREG_CP15_CONTROL bit defines */
#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
#define XREG_CP15_CONTROL_V_BIT 0x00002000U
#define XREG_CP15_CONTROL_I_BIT 0x00001000U
#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
#define XREG_CP15_CONTROL_B_BIT 0x00000080U
#define XREG_CP15_CONTROL_C_BIT 0x00000004U
#define XREG_CP15_CONTROL_A_BIT 0x00000002U
#define XREG_CP15_CONTROL_M_BIT 0x00000001U
#if defined (__GNUC__) || defined (__ICCARM__)
/* C2 Register Defines */
#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
/* C3 Register Defines */
#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
/* C4 Register Defines */
/* Not Used */
/* C5 Register Defines */
#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
/* C6 Register Defines */
#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
/* C7 Register Defines */
#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
/* The CP15 register access below has been deprecated in favor of the new
* isb instruction in Cortex A9.
*/
#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
/* The next two CP15 register accesses below have been deprecated in favor
* of the new dsb and dmb instructions in Cortex A9.
*/
#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
/* C8 Register Defines */
#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
/* C9 Register Defines */
#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
/* C10 Register Defines */
#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
/* C11 Register Defines */
/* Not used */
/* C12 Register Defines */
#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
/* C13 Register Defines */
#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
/* C14 Register Defines */
/* not used */
/* C15 Register Defines */
#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
#else
/* C2 Register Defines */
#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
/* C3 Register Defines */
#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
/* C4 Register Defines */
/* Not Used */
/* C5 Register Defines */
#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
/* C6 Register Defines */
#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
/* C7 Register Defines */
#define XREG_CP15_NOP "cp15:0:c7:c0:4"
#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
/* The CP15 register access below has been deprecated in favor of the new
* isb instruction in Cortex A9.
*/
#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
/* The next two CP15 register accesses below have been deprecated in favor
* of the new dsb and dmb instructions in Cortex A9.
*/
#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
/* C8 Register Defines */
#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
/* C9 Register Defines */
#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
/* C10 Register Defines */
#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
/* C11 Register Defines */
/* Not used */
/* C12 Register Defines */
#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
/* C13 Register Defines */
#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
/* C14 Register Defines */
/* not used */
/* C15 Register Defines */
#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
#endif
/* MPE register definitions */
#define XREG_FPSID c0
#define XREG_FPSCR c1
#define XREG_MVFR1 c6
#define XREG_MVFR0 c7
#define XREG_FPEXC c8
#define XREG_FPINST c9
#define XREG_FPINST2 c10
/* FPSID bits */
#define XREG_FPSID_IMPLEMENTER_BIT (24)
#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
#define XREG_FPSID_SOFTWARE (1<<23)
#define XREG_FPSID_ARCH_BIT (16)
#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
#define XREG_FPSID_PART_BIT (8)
#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
#define XREG_FPSID_VARIANT_BIT (4)
#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
#define XREG_FPSID_REV_BIT (0)
#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
/* FPSCR bits */
#define XREG_FPSCR_N_BIT (1 << 31)
#define XREG_FPSCR_Z_BIT (1 << 30)
#define XREG_FPSCR_C_BIT (1 << 29)
#define XREG_FPSCR_V_BIT (1 << 28)
#define XREG_FPSCR_QC (1 << 27)
#define XREG_FPSCR_AHP (1 << 26)
#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
#define XREG_FPSCR_RMODE_BIT (22)
#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
#define XREG_FPSCR_STRIDE_BIT (20)
#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
#define XREG_FPSCR_LENGTH_BIT (16)
#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
#define XREG_FPSCR_IDC (1 << 7)
#define XREG_FPSCR_IXC (1 << 4)
#define XREG_FPSCR_UFC (1 << 3)
#define XREG_FPSCR_OFC (1 << 2)
#define XREG_FPSCR_DZC (1 << 1)
#define XREG_FPSCR_IOC (1 << 0)
/* MVFR0 bits */
#define XREG_MVFR0_RMODE_BIT (28)
#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
#define XREG_MVFR0_SHORT_VEC_BIT (24)
#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
#define XREG_MVFR0_SQRT_BIT (20)
#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
#define XREG_MVFR0_DIVIDE_BIT (16)
#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
#define XREG_MVFR0_EXEC_TRAP_BIT (12)
#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
#define XREG_MVFR0_DP_BIT (8)
#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
#define XREG_MVFR0_SP_BIT (4)
#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
#define XREG_MVFR0_A_SIMD_BIT (0)
#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
/* FPEXC bits */
#define XREG_FPEXC_EX (1 << 31)
#define XREG_FPEXC_EN (1 << 30)
#define XREG_FPEXC_DEX (1 << 29)
/**
*@endcond
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XREG_CORTEXA9_H */

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;******************************************************************************
; Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
; SPDX-License-Identifier: MIT
;*****************************************************************************
;****************************************************************************
;**
; @file asm_vectors.s
;
; This file contains the initial vector table for the Cortex A9 processor
;
; <pre>
; MODIFICATION HISTORY:
;
; Ver Who Date Changes
; ----- ------- -------- ---------------------------------------------------
; 1.00a ecm/sdm 10/20/09 Initial version
; 3.11a asa 9/17/13 Added support for neon.
; 4.00 pkp 01/22/14 Modified return addresses for interrupt
; handlers
; 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
; abort and prefetch abort into DataAbortAddr and
; PrefetchAbortAddr for further use to fix CR#854523
; 5.4 pkp 12/03/15 Added handler for undefined exception
;</pre>
;
; @note
;
; None.
;
;****************************************************************************
EXPORT _vector_table
EXPORT IRQHandler
IMPORT _boot
IMPORT _prestart
IMPORT IRQInterrupt
IMPORT FIQInterrupt
IMPORT SWInterrupt
IMPORT DataAbortInterrupt
IMPORT PrefetchAbortInterrupt
IMPORT UndefinedException
IMPORT DataAbortAddr
IMPORT PrefetchAbortAddr
IMPORT UndefinedExceptionAddr
AREA |.vectors|, CODE
REQUIRE8 {TRUE}
PRESERVE8 {TRUE}
ENTRY ; define this as an entry point
_vector_table
B _boot
B Undefined
B SVCHandler
B PrefetchAbortHandler
B DataAbortHandler
NOP ; Placeholder for address exception vector
B IRQHandler
B FIQHandler
IRQHandler ; IRQ vector handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
bl IRQInterrupt ; IRQ vector
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
subs pc, lr, #4 ; adjust return
FIQHandler ; FIQ vector handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
vpush {d0-d7}
vpush {d16-d31}
vmrs r1, FPSCR
push {r1}
vmrs r1, FPEXC
push {r1}
FIQLoop
bl FIQInterrupt ; FIQ vector
pop {r1}
vmsr FPEXC, r1
pop {r1}
vmsr FPSCR, r1
vpop {d16-d31}
vpop {d0-d7}
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
subs pc, lr, #4 ; adjust return
Undefined ; Undefined handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
ldr r0, =UndefinedExceptionAddr
sub r1, lr,#4
str r1, [r0] ; Address of instruction causing undefined exception
bl UndefinedException ; UndefinedException: call C function here
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
movs pc, lr
SVCHandler ; SWI handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
tst r0, #0x20 ; check the T bit
ldrneh r0, [lr,#-2] ; Thumb mode
bicne r0, r0, #0xff00 ; Thumb mode
ldreq r0, [lr,#-4] ; ARM mode
biceq r0, r0, #0xff000000 ; ARM mode
bl SWInterrupt ; SWInterrupt: call C function here
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
movs pc, lr ; adjust return
DataAbortHandler ; Data Abort handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
ldr r0, =DataAbortAddr
sub r1, lr,#8
str r1, [r0] ;Address of instruction causing data abort
bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
subs pc, lr, #8 ; adjust return
PrefetchAbortHandler ; Prefetch Abort handler
stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
ldr r0, =PrefetchAbortAddr
sub r1, lr,#4
str r1, [r0] ;Address of instruction causing prefetch abort
bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here
ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
subs pc, lr, #4 ; adjust return
END

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/******************************************************************************
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpseudo_asm.h
*
* @addtogroup a53_32_specific Cortex A53 32bit Processor Specific Include Files
*
* The xpseudo_asm.h includes xreg_cortexa53.h and xpseudo_asm_gcc.h.
* The xreg_cortexa53.h file contains definitions for inline assembler code.
* It provides inline definitions for Cortex A53 GPRs, SPRs, co-processor
* registers and floating point registers.
*
* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
* assembler instructions, available as macros. These can be very useful for
* tasks such as setting or getting special purpose registers, synchronization,
* or cache manipulation etc. These inline assembler instructions can be used
* from drivers and user applications written in C.
*
* @{
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 5.2 pkp 28/05/15 First release
* </pre>
*
******************************************************************************/
#ifndef XPSEUDO_ASM_H
#define XPSEUDO_ASM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "xreg_cortexa53.h"
#include "xpseudo_asm_gcc.h"
#ifdef __cplusplus
}
#endif
#endif /* XPSEUDO_ASM_H */
/**
* @} End of "addtogroup a53_32_specific".
*/

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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_exception.h
*
* @addtogroup microblaze_exception_apis Microblaze Exception APIs
* @{
*
* The xil_exception.h file, available in the <install-directory>/src/microblaze folder,
* contains Microblaze specific exception related APIs and macros. Application programs
* can use these APIs for various exception related operations. For example, enable exception,
* disable exception, register exception hander.
*
* @note To use exception related functions, xil_exception.h must be added in source code
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 hbm 07/28/09 Initial release
*
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
#define XIL_EXCEPTION_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/*
* These constants are specific to Microblaze processor.
*/
#define XIL_EXCEPTION_ID_FIRST 0U
#define XIL_EXCEPTION_ID_FSL 0U
#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1U
#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2U
#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3U
#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3U
#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4U
#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4U
#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5U
#define XIL_EXCEPTION_ID_FPU 6U
#define XIL_EXCEPTION_ID_STACK_VIOLATION 7U
#define XIL_EXCEPTION_ID_MMU 7U
#define XIL_EXCEPTION_ID_LAST XIL_EXCEPTION_ID_MMU
/*
* XIL_EXCEPTION_ID_INT is defined for all processors, but with different value.
*/
#define XIL_EXCEPTION_ID_INT 16U /**
* exception ID for interrupt
*/
/**************************** Type Definitions *******************************/
/**
* This typedef is the exception handler function.
*/
typedef void (*Xil_ExceptionHandler)(void *Data);
/**
* This data type defines an interrupt handler for a device.
* The argument points to the instance of the component
*/
typedef void (*XInterruptHandler) (void *InstancePtr);
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern void Xil_ExceptionRegisterHandler(u32 Id,
Xil_ExceptionHandler Handler,
void *Data);
extern void Xil_ExceptionRemoveHandler(u32 Id);
extern void Xil_ExceptionInit(void);
extern void Xil_ExceptionEnable(void);
extern void Xil_ExceptionDisable(void);
#ifdef __cplusplus
}
#endif
#endif
/**
*@endcond
*/
/**
* @} End of "addtogroup microblaze_exception_apis".
*/

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/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdevcfg_sinit.c
* @addtogroup devcfg_v3_7
* @{
*
* This file contains method for static initialization (compile-time) of the
* driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a hvm 02/07/11 First release
* 3.5 ms 08/07/17 Fixed compilation warnings.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xdevcfg.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* Lookup the device configuration based on the unique device ID. The table
* contains the configuration info for each device in the system.
*
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
*
* @note None.
*
******************************************************************************/
XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
{
extern XDcfg_Config XDcfg_ConfigTable[];
XDcfg_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XDcfg_ConfigTable[Index];
break;
}
}
return (CfgPtr);
}
/** @} */

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>phased_array_system</name>
<comment></comment>
<projects>
<project>phased_array</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdx.system.core.embedded</nature>
<nature>com.xilinx.sdx.system.systemprojectnature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

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collect (PROJECT_LIB_HEADERS xparameters_ps.h)

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/******************************************************************************
* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/******************************************************************************
* File : microblaze_disable_dcache.s
* Date : 2002, March 20.
* Company: Xilinx
* Group : Emerging Software Technologies
*
* Summary:
* Disable the L1 dcache on the microblaze.
*
*******************************************************************************/
#include "xparameters.h"
#include "microblaze_instructions.h"
.text
.globl microblaze_disable_dcache
.ent microblaze_disable_dcache
.align 2
microblaze_disable_dcache:
#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
ADDIK r1, r1, -8
SI r15, r1, 0
BRLID r15, microblaze_flush_dcache /* microblaze_flush_dcache does not use r1*/
nop
LI r15, r1, 0
ADDIK r1, r1, 8
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
rtsd r15, 8
msrclr r0, 0x80
#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 1 */
ADDIK r1, r1, -8
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
SI r15, r1, 0
BRLID r15, microblaze_flush_dcache
nop
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
mfs r11, rmsr
andi r11, r11, ~(0x80)
mts rmsr, r11
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
LI r15, r1, 0
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
ADDIK r1, r1, 8
rtsd r15, 8
nop
#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
.end microblaze_disable_dcache

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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xscuwdt_selftest.c
* @addtogroup scuwdt_v2_4
* @{
*
* Contains diagnostic self-test functions for the XScuWdt driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a sdm 01/15/10 First release
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xscuwdt.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
*
* Run a self-test on the WDT. This test stops the watchdog, writes a value to
* the watchdog load register, starts the watchdog and verifies that the value
* read from the counter register is less that the value written to the load
* register. It then restores the control register and the watchdog load
* register.
*
* @param InstancePtr is a pointer to the XScuWdt instance.
*
* @return
* - XST_SUCCESS if self-test was successful.
* - XST_FAILURE if the WDT is not decrementing.
*
* @note None.
*
******************************************************************************/
s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
{
s32 SelfTestStatus;
u32 Register;
u32 CtrlOrig;
u32 LoadOrig;
/*
* Assert to ensure the inputs are valid and the instance has been
* initialized.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Stop the watchdog timer.
*/
CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
XScuWdt_SetControlReg(InstancePtr,
CtrlOrig & (~(u32)XSCUWDT_CONTROL_WD_ENABLE_MASK));
LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
XSCUWDT_LOAD_OFFSET);
XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFFU);
/*
* Start the watchdog timer and check if the watchdog counter is
* decrementing.
*/
XScuWdt_SetControlReg(InstancePtr,
CtrlOrig | (u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
XSCUWDT_COUNTER_OFFSET);
XScuWdt_LoadWdt(InstancePtr, LoadOrig);
XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
if (Register == 0xFFFFFFFFU) {
SelfTestStatus = (s32)XST_FAILURE;
}
else {
SelfTestStatus = (s32)XST_SUCCESS;
}
return SelfTestStatus;
}
/** @} */

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/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xil-crt0.S
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a ecm 10/20/09 Initial version
* 3.05a sdm 02/02/12 Added code for profiling
* 3.06a sgd 05/16/12 Added global constructors and cleanup code
* Uart initialization based on compiler flag
* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
* initialization of uart smc nor and sram
* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
* timer when USE_AMP flag is defined
* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
* Now the TTC instance as specified by the user will be
* started.
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#include "bspconfig.h"
.file "xil-crt0.S"
.section ".got2","aw"
.align 2
.text
.Lsbss_start:
.long __sbss_start
.Lsbss_end:
.long __sbss_end
.Lbss_start:
.long __bss_start
.Lbss_end:
.long __bss_end
.Lstack:
.long __stack
.globl _start
_start:
bl __cpu_init /* Initialize the CPU first (BSP provides this) */
mov r0, #0
/* clear sbss */
ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
ldr r2,.Lsbss_end /* calculate end of the SBSS */
.Lloop_sbss:
cmp r1,r2
bge .Lenclsbss /* If no SBSS, no clearing required */
str r0, [r1], #4
b .Lloop_sbss
.Lenclsbss:
/* clear bss */
ldr r1,.Lbss_start /* calculate beginning of the BSS */
ldr r2,.Lbss_end /* calculate end of the BSS */
.Lloop_bss:
cmp r1,r2
bge .Lenclbss /* If no BSS, no clearing required */
str r0, [r1], #4
b .Lloop_bss
.Lenclbss:
/* set stack pointer */
ldr r13,.Lstack /* stack address */
/* Reset and start Global Timer */
mov r0, #0x0
mov r1, #0x0
/* Reset and start Triple Timer Counter */
#if defined SLEEP_TIMER_BASEADDR
bl XTime_StartTTCTimer
#endif
#if USE_AMP != 1
bl XTime_SetTime
#endif
#ifdef PROFILING /* defined in Makefile */
/* Setup profiling stuff */
bl _profile_init
#endif /* PROFILING */
/* run global constructors */
bl __libc_init_array
/* make sure argc and argv are valid */
mov r0, #0
mov r1, #0
/* Let her rip */
bl main
/* Cleanup global constructors */
bl __libc_fini_array
#ifdef PROFILING
/* Cleanup profiling stuff */
bl _profile_clean
#endif /* PROFILING */
/* All done */
bl exit
.Lexit: /* should never get here */
b .Lexit
.Lstart:
.size _start,.Lstart-_start

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/******************************************************************************
* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_errata.h
*
* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
* @{
* Various ARM errata are handled in the standalone BSP. The implementation for
* errata handling follows ARM guidelines and is based on the open source Linux
* support for these errata.
*
* @note The errata handling is enabled by default. To disable handling of all the
* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
* disable errata on a per-erratum basis, un-define relevant macros in
* xil_errata.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a srt 04/18/13 First release
* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
* </pre>
*
******************************************************************************/
#ifndef XIL_ERRATA_H
#define XIL_ERRATA_H
#ifdef __cplusplus
extern "C" {
#endif
/**
*@cond nocomments
*/
/**
* @name errata_definitions
*
* The errata conditions handled in the standalone BSP are listed below
* @{
*/
#define ENABLE_ARM_ERRATA 1
/**
*@endcond
*/
#ifdef ENABLE_ARM_ERRATA
/**
* Errata No: 742230
* Description: DMB operation may be faulty
*/
#define CONFIG_ARM_ERRATA_742230 1
/**
* Errata No: 743622
* Description: Faulty hazard checking in the Store Buffer may lead
* to data corruption.
*/
#define CONFIG_ARM_ERRATA_743622 1
/**
* Errata No: 775420
* Description: A data cache maintenance operation which aborts,
* might lead to deadlock
*/
#define CONFIG_ARM_ERRATA_775420 1
/**
* Errata No: 794073
* Description: Speculative instruction fetches with MMU disabled
* might not comply with architectural requirements
*/
#define CONFIG_ARM_ERRATA_794073 1
/** PL310 L2 Cache Errata */
/**
* Errata No: 588369
* Description: Clean & Invalidate maintenance operations do not
* invalidate clean lines
*/
#define CONFIG_PL310_ERRATA_588369 1
/**
* Errata No: 727915
* Description: Background Clean and Invalidate by Way operation
* can cause data corruption
*/
#define CONFIG_PL310_ERRATA_727915 1
/*@}*/
#endif /* ENABLE_ARM_ERRATA */
#ifdef __cplusplus
}
#endif
#endif /* XIL_ERRATA_H */
/**
* @} End of "addtogroup a9_errata".
*/

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/******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xil-crt0.S
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.00 pkp 02/10/14 First release
* 5.04 pkp 12/18/15 Initialized global constructor for C++ applications
* 5.04 pkp 02/19/16 Added timer configuration using XTime_StartTimer API when
* TTC3 is present
* 6.4 asa 08/16/17 Added call to Xil_InitializeExistingMPURegConfig to
* initialize the MPU configuration table with the MPU
* configurations already set in Init_Mpu function.
* 6.6 srm 10/18/17 Updated the timer configuration with XTime_StartTTCTimer.
* Now the timer instance as specified by the user will be
* started.
* 7.2 mus 10/22/19 Defined RPU_TZ_MASK as #define instead of variable.
* 7.2 sd 03/20/20 Add clocking support.
* </pre>
*
******************************************************************************/
#include "xparameters.h"
#include "bspconfig.h"
.file "xil-crt0.S"
.section ".got2","aw"
.align 2
/*
* 0th bit of PROCESSOR_ACCESS_VALUE macro signifies trustzone
* setting for RPU address space
*/
#define RPU_TZ_MASK 0x1
.text
.Lsbss_start:
.long __sbss_start
.Lsbss_end:
.long __sbss_end
.Lbss_start:
.long __bss_start__
.Lbss_end:
.long __bss_end__
.Lstack:
.long __stack
.set RPU_0_PWRCTL, 0xFF9A0108
.set RPU_1_PWRCTL, 0xFF9A0208
.set MPIDR_AFF0, 0xFF
.set PWRCTL_MASK, 0x1
.globl _startup
_startup:
bl __cpu_init /* Initialize the CPU first (BSP provides this) */
#if (PROCESSOR_ACCESS_VALUE & RPU_TZ_MASK)
mrc p15, 0, r0, c0, c0, 5 /* Read MPIDR register */
ands r0, r0, #MPIDR_AFF0 /* Get affinity level 0 */
bne core1
ldr r10, =RPU_0_PWRCTL /* Load PWRCTRL address for core 0 */
b test_boot_status
core1:
ldr r10, =RPU_1_PWRCTL /* Load PWRCTRL address for core 1 */
test_boot_status:
ldr r11, [r10] /* Read PWRCTRL register */
ands r11, r11, #PWRCTL_MASK /* Extract and test core's PWRCTRL */
/* if warm reset, skip the clearing of BSS and SBSS */
bne .Lenclbss
#endif
mov r0, #0
/* clear sbss */
ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
ldr r2,.Lsbss_end /* calculate end of the SBSS */
.Lloop_sbss:
cmp r1,r2
bge .Lenclsbss /* If no SBSS, no clearing required */
str r0, [r1], #4
b .Lloop_sbss
.Lenclsbss:
/* clear bss */
ldr r1,.Lbss_start /* calculate beginning of the BSS */
ldr r2,.Lbss_end /* calculate end of the BSS */
.Lloop_bss:
cmp r1,r2
bge .Lenclbss /* If no BSS, no clearing required */
str r0, [r1], #4
b .Lloop_bss
.Lenclbss:
/* set stack pointer */
ldr r13,.Lstack /* stack address */
/* configure the timer if TTC is present */
#ifdef SLEEP_TIMER_BASEADDR
bl XTime_StartTTCTimer
#endif
bl Xil_InitializeExistingMPURegConfig /* Initialize MPU config */
/* run global constructors */
bl __libc_init_array
/* make sure argc and argv are valid */
mov r0, #0
mov r1, #0
#ifdef XCLOCKING
bl Xil_ClockInit
#endif
bl main /* Jump to main C code */
/* Cleanup global constructors */
bl __libc_fini_array
bl exit
.Lexit: /* should never get here */
b .Lexit
.Lstart:
.size _startup,.Lstart-_startup

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/******************************************************************************
* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include "xil_types.h"
/* Stuv for close() sys-call */
__weak s32 _sys_close(s32 fh)
{
return -1;
}

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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops.c
* @addtogroup gpiops_v3_9
* @{
*
* The XGpioPs driver. Functions in this file are the minimum required functions
* for this driver. See xgpiops.h for a detailed description of the driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
* relevant to Zynq device. The interrupts are disabled
* for output pins on all banks during initialization.
* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* 3.1 aru 07/13/18 Resolved doxygen reported warnings. CR# 1006331.
* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
* in safety mode and modified the code such as
* Use of mixed mode arithmetic,Declared the pointer param
* as Pointer to const,Casting operation to a pointer,
* Literal value requires a U suffix.
* 3.5 sne 03/13/19 Added Versal support.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xgpiops.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
void StubHandler(void *CallBackRef, u32 Bank, u32 Status); /**< Stub handler */
/*****************************************************************************/
/**
*
* This function initializes a XGpioPs instance/driver.
* All members of the XGpioPs instance structure are initialized and
* StubHandlers are assigned to the Bank Status Handlers.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param ConfigPtr points to the XGpioPs device configuration structure.
* @param EffectiveAddr is the device base address in the virtual memory
* address space. If the address translation is not used then the
* physical address should be passed.
* Unexpected errors may occur if the address mapping is changed
* after this function is invoked.
*
* @return XST_SUCCESS always.
*
* @note None.
*
******************************************************************************/
s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
u32 EffectiveAddr)
{
s32 Status = (s32)0;
u8 i;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
Xil_AssertNonvoid(EffectiveAddr != (u32)0);
/*
* Set some default values for instance data, don't indicate the device
* is ready to use until everything has been initialized successfully.
*/
InstancePtr->IsReady = 0U;
InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
InstancePtr->Handler = (XGpioPs_Handler)StubHandler;
InstancePtr->Platform = XGetPlatform_Info();
/* Initialize the Bank data based on platform */
if (InstancePtr->Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
/*
* Max pins in the ZynqMP GPIO device
* 0 - 25, Bank 0
* 26 - 51, Bank 1
* 52 - 77, Bank 2
* 78 - 109, Bank 3
* 110 - 141, Bank 4
* 142 - 173, Bank 5
*/
InstancePtr->MaxPinNum = (u32)174;
InstancePtr->MaxBanks = (u8)6;
}
else if (InstancePtr->Platform == (u32)XPLAT_VERSAL)
{
if(InstancePtr->PmcGpio == (u32)FALSE)
{
/* Max pins in the PS_GPIO devices
* 0 -25, Bank 0
* 26-57, Bank 3
*/
InstancePtr->MaxPinNum = (u32)58;
InstancePtr->MaxBanks = (u8)4;
}
else
{
/* Max pins in the PMC_GPIO devices
* 0 - 25,Bank 0
* 26 - 51,Bank 1
* 52 - 83,Bank 3
* 84 - 115, Bank 4
*/
InstancePtr->MaxPinNum = (u32)116;
InstancePtr->MaxBanks = (u8)5;
}
}
else {
/*
* Max pins in the GPIO device
* 0 - 31, Bank 0
* 32 - 53, Bank 1
* 54 - 85, Bank 2
* 86 - 117, Bank 3
*/
InstancePtr->MaxPinNum = (u32)118;
InstancePtr->MaxBanks = (u8)4;
}
/*
* By default, interrupts are not masked in GPIO. Disable
* interrupts for all pins in all the 4 banks.
*/
for (i=(u8)0U;i<InstancePtr->MaxBanks;i++) {
if (InstancePtr->Platform == XPLAT_VERSAL){
if(InstancePtr->PmcGpio == (u32)FALSE)
{
if((i== (u8)XGPIOPS_ONE)||(i== (u8)XGPIOPS_TWO))
{
continue;
}
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
}
else
{
if(i==(u32)XGPIOPS_TWO)
{
continue;
}
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
}
}
else
{
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
}
}
/* Indicate the component is now ready to use. */
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return Status;
}
/****************************************************************************/
/**
*
* Read the Data register of the specified GPIO bank.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
*
* @return Current value of the Data register.
*
* @note This function is used for reading the state of all the GPIO pins
* of specified bank.
*
*****************************************************************************/
u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
XGPIOPS_DATA_RO_OFFSET);
}
/****************************************************************************/
/**
*
* Read Data from the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number for which the data has to be read.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
* See xgpiops.h for the mapping of the pin numbers in the banks.
*
* @return Current value of the Pin (0 or 1).
*
* @note This function is used for reading the state of the specified
* GPIO pin.
*
*****************************************************************************/
u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
}
/****************************************************************************/
/**
*
* Write to the Data register of the specified GPIO bank.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
* @param Data is the value to be written to the Data register.
*
* @return None.
*
* @note This function is used for writing to all the GPIO pins of
* the bank. The previous state of the pins is not maintained.
*
*****************************************************************************/
void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertVoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
XGPIOPS_DATA_OFFSET, Data);
}
/****************************************************************************/
/**
*
* Write data to the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number to which the Data is to be written.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
* @param Data is the data to be written to the specified pin (0 or 1).
*
* @return None.
*
* @note This function does a masked write to the specified pin of
* the specified GPIO bank. The previous state of other pins
* is maintained.
*
*****************************************************************************/
void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data)
{
u32 RegOffset;
u32 Value;
u8 Bank;
u8 PinNumber;
u32 DataVar = Data;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
if (PinNumber > 15U) {
/* There are only 16 data bits in bit maskable register. */
PinNumber -= (u8)16;
RegOffset = XGPIOPS_DATA_MSW_OFFSET;
} else {
RegOffset = XGPIOPS_DATA_LSW_OFFSET;
}
/*
* Get the 32 bit value to be written to the Mask/Data register where
* the upper 16 bits is the mask and lower 16 bits is the data.
*/
DataVar &= (u32)0x01;
Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
RegOffset, Value);
}
/****************************************************************************/
/**
*
* Set the Direction of the pins of the specified GPIO Bank.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
* @param Direction is the 32 bit mask of the Pin direction to be set for
* all the pins in the Bank. Bits with 0 are set to Input mode,
* bits with 1 are set to Output Mode.
*
* @return None.
*
* @note This function is used for setting the direction of all the pins
* in the specified bank. The previous state of the pins is
* not maintained.
*
*****************************************************************************/
void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertVoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET, Direction);
}
/****************************************************************************/
/**
*
* Set the Direction of the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number to which the Data is to be written.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
* @param Direction is the direction to be set for the specified pin.
* Valid values are 0 for Input Direction, 1 for Output Direction.
*
* @return None.
*
*****************************************************************************/
void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction)
{
u8 Bank;
u8 PinNumber;
u32 DirModeReg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
Xil_AssertVoid(Direction <= (u32)1);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET);
if (Direction!=(u32)0) { /* Output Direction */
DirModeReg |= ((u32)1 << (u32)PinNumber);
} else { /* Input Direction */
DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
}
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET, DirModeReg);
}
/****************************************************************************/
/**
*
* Get the Direction of the pins of the specified GPIO Bank.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
*
* @return Returns a 32 bit mask of the Direction register. Bits with 0 are
* in Input mode, bits with 1 are in Output Mode.
*
* @note None.
*
*****************************************************************************/
u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET);
}
/****************************************************************************/
/**
*
* Get the Direction of the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number for which the Direction is to be
* retrieved.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
*
* @return Direction of the specified pin.
* - 0 for Input Direction
* - 1 for Output Direction
*
* @note None.
*
*****************************************************************************/
u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
}
/****************************************************************************/
/**
*
* Set the Output Enable of the pins of the specified GPIO Bank.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
* @param OpEnable is the 32 bit mask of the Output Enables to be set for
* all the pins in the Bank. The Output Enable of bits with 0 are
* disabled, the Output Enable of bits with 1 are enabled.
*
* @return None.
*
* @note This function is used for setting the Output Enables of all the
* pins in the specified bank. The previous state of the Output
* Enables is not maintained.
*
*****************************************************************************/
void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertVoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET, OpEnable);
}
/****************************************************************************/
/**
*
* Set the Output Enable of the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number to which the Data is to be written.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
* @param OpEnable specifies whether the Output Enable for the specified
* pin should be enabled.
* Valid values are 0 for Disabling Output Enable,
* 1 for Enabling Output Enable.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
{
u8 Bank;
u8 PinNumber;
u32 OpEnableReg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
Xil_AssertVoid(OpEnable <= (u32)1);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET);
if (OpEnable != (u32)0) { /* Enable Output Enable */
OpEnableReg |= ((u32)1 << (u32)PinNumber);
} else { /* Disable Output Enable */
OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
}
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET, OpEnableReg);
}
/****************************************************************************/
/**
*
* Get the Output Enable status of the pins of the specified GPIO Bank.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
*
* @return Returns a a 32 bit mask of the Output Enable register.
* Bits with 0 are in Disabled state, bits with 1 are in
* Enabled State.
*
* @note None.
*
*****************************************************************************/
u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
#ifdef versal
if(InstancePtr->PmcGpio == (u32)TRUE) {
Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
} else {
Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
}
#endif
return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET);
}
/****************************************************************************/
/**
*
* Get the Output Enable status of the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number for which the Output Enable status is to
* be retrieved.
* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
*
* @return Output Enable of the specified pin.
* - 0 if Output Enable is disabled for this pin
* - 1 if Output Enable is enabled for this pin
*
* @note None.
*
*****************************************************************************/
u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
/* Get the Bank number and Pin number within the bank. */
#ifdef versal
XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
#else
XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
#endif
return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
}
/****************************************************************************/
/**
*
* Get the Bank number and the Pin number in the Bank, for the given PinNumber
* in the GPIO device.
*
* @param PinNumber is the Pin number in the GPIO device.
* @param BankNumber returns the Bank in which this GPIO pin is present.
* Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
* @param PinNumberInBank returns the Pin Number within the Bank.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#ifdef versal
void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
#else
void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
#endif
{
u32 XGpioPsPinTable[6] = {0};
#ifdef versal
u8 i=(u8)0;
#endif
u32 Platform = XGetPlatform_Info();
if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
/*
* This structure defines the mapping of the pin numbers to the banks when
* the driver APIs are used for working on the individual pins.
*/
XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
*BankNumber = 0U;
while (*BankNumber < XGPIOPS_SIX) {
if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
break;
}
(*BankNumber)++;
}
}
#ifdef versal
else if(Platform == XPLAT_VERSAL)
{
if(InstancePtr->PmcGpio == (u32)(FALSE))
{
XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
XGpioPsPinTable[1] = (u32)57; /* 26 - 57, Bank 3 */
*BankNumber =0U;
if(PinNumber <= XGpioPsPinTable[*BankNumber])
{
*BankNumber = (u8)XGPIOPS_ZERO;
}
else
{
*BankNumber = (u8)XGPIOPS_THREE;
}
}
else
{
XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
XGpioPsPinTable[2] = (u32)83; /* 52 - 83, Bank 3 */
XGpioPsPinTable[3] = (u32)115; /*84 - 115, Bank 4 */
*BankNumber =0U;
while(i < XGPIOPS_FOUR)
{
if(i <= (u8)XGPIOPS_ONE)
{
if (PinNumber <= XGpioPsPinTable[i])
{
*BankNumber = (u8)i;
break;
}
i++;
}
else
{
if (PinNumber <= XGpioPsPinTable[i])
{
*BankNumber = (u8)i+1U;
break;
}
i++;
}
}
}
}
#endif
else {
XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
*BankNumber = 0U;
while (*BankNumber < XGPIOPS_FOUR) {
if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
break;
}
(*BankNumber)++;
}
}
if (*BankNumber == (u8)0) {
*PinNumberInBank = PinNumber;
}
#ifdef versal
else if(Platform == XPLAT_VERSAL)
{
if(InstancePtr->PmcGpio == (u32)(FALSE))
{
*PinNumberInBank = (u8)((u32)PinNumber - (XGpioPsPinTable[0] + (u32)1));
}
else {
if((*BankNumber ==(u8)XGPIOPS_THREE) || (*BankNumber ==(u8)XGPIOPS_FOUR))
{
*PinNumberInBank = (u8)((u32)PinNumber %
(XGpioPsPinTable[*BankNumber - (u8)XGPIOPS_TWO] + (u32)1));
}
else
{
*PinNumberInBank = (u8)((u32)PinNumber %
(XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
}
}
}
#endif
else {
*PinNumberInBank = (u8)((u32)PinNumber %
(XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
}
}
/*****************************************************************************/
/**
*
* This is a stub for the status callback. The stub is here in case the upper
* layers do not set the handler.
*
* @param CallBackRef is a pointer to the upper layer callback reference
* @param Bank is the GPIO Bank in which an interrupt occurred.
* @param Status is the Interrupt status of the GPIO bank.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
{
(void) CallBackRef;
(void) Bank;
(void) Status;
Xil_AssertVoidAlways();
}
/** @} */

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/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#include <stdio.h>
#include "xil_types.h"
/*
* fcntl -- Manipulate a file descriptor.
* We don't have a filesystem, so we do nothing.
*/
__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
{
(void)fd;
(void)cmd;
(void)arg;
return 0;
}

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<?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="phased_array" location="/home/dylan/workspace/phased_array" platform="/home/dylan/workspace/phased_array_platform/export/phased_array_platform/phased_array_platform.xpfm" platformUID="xilinx:zybo-z7-20::0.0(custom)" systemProject="phased_array_system" sysConfig="phased_array_platform" runtime="C/C++" cpu="standalone_domain" cpuInstance="ps7_cortexa9_0" os="standalone" dimmRepoPath="" mssSignature="dd66451c26ba4b25b4502d5912a040ac">
<configuration name="Debug" id="xilinx.gnu.armv7.exe.debug.1531516350">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
</configuration>
<configuration name="Release" id="xilinx.gnu.armv7.exe.release.32331858" dirty="true">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
</configuration>
<template appTemplateName="hello_world"/>
</sdkproject:SdkProject>

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/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xscutimer.c
* @addtogroup scutimer_v2_3
* @{
*
* Contains the implementation of interface functions of the SCU Timer driver.
* See xscutimer.h for a description of the driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a nm 03/10/10 First release
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xscutimer.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/****************************************************************************/
/**
*
* Initialize a specific timer instance/driver. This function must be called
* before other functions of the driver are called.
*
* @param InstancePtr is a pointer to the XScuTimer instance.
* @param ConfigPtr points to the XScuTimer configuration structure.
* @param EffectiveAddress is the base address for the device. It could be
* a virtual address if address translation is supported in the
* system, otherwise it is the physical address.
*
* @return
* - XST_SUCCESS if initialization was successful.
* - XST_DEVICE_IS_STARTED if the device has already been started.
*
* @note None.
*
******************************************************************************/
s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
{
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
/*
* If the device is started, disallow the initialize and return a
* status indicating it is started. This allows the user to stop the
* device and reinitialize, but prevents a user from inadvertently
* initializing.
*/
if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
/*
* Copy configuration into the instance structure.
*/
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
/*
* Save the base address pointer such that the registers of the block
* can be accessed and indicate it has not been started yet.
*/
InstancePtr->Config.BaseAddr = EffectiveAddress;
InstancePtr->IsStarted = (u32)0;
/*
* Indicate the instance is ready to use, successfully initialized.
*/
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
Status =(s32)XST_SUCCESS;
}
else {
Status = (s32)XST_DEVICE_IS_STARTED;
}
return Status;
}
/****************************************************************************/
/**
*
* Start the timer.
*
* @param InstancePtr is a pointer to the XScuTimer instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XScuTimer_Start(XScuTimer *InstancePtr)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Read the contents of the Control register.
*/
Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET);
/*
* Set the 'timer enable' bit in the register.
*/
Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
/*
* Update the Control register with the new value.
*/
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET, Register);
/*
* Indicate that the device is started.
*/
InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
}
/****************************************************************************/
/**
*
* Stop the timer.
*
* @param InstancePtr is a pointer to the XScuTimer instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XScuTimer_Stop(XScuTimer *InstancePtr)
{
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Read the contents of the Control register.
*/
Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET);
/*
* Clear the 'timer enable' bit in the register.
*/
Register &= (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
/*
* Update the Control register with the new value.
*/
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET, Register);
/*
* Indicate that the device is stopped.
*/
InstancePtr->IsStarted = (u32)0;
}
/*****************************************************************************/
/**
*
* This function sets the prescaler bits in the timer control register.
*
* @param InstancePtr is a pointer to the XScuTimer instance.
* @param PrescalerValue is a 8 bit value that sets the prescaler to use.
*
* @return None
*
* @note None
*
****************************************************************************/
void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
{
u32 ControlReg;
/*
* Assert to validate input arguments.
*/
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Read the Timer control register.
*/
ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET);
/*
* Clear all of the prescaler control bits in the register.
*/
ControlReg &= (u32)(~XSCUTIMER_CONTROL_PRESCALER_MASK);
/*
* Set the prescaler value.
*/
ControlReg |= (((u32)PrescalerValue) << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
/*
* Write the register with the new values.
*/
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET, ControlReg);
}
/*****************************************************************************/
/**
*
* This function returns the current prescaler value.
*
* @param InstancePtr is a pointer to the XScuTimer instance.
*
* @return The prescaler value.
*
* @note None.
*
****************************************************************************/
u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
{
u32 ControlReg;
/*
* Assert to validate input arguments.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Read the Timer control register.
*/
ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET);
ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
}
/** @} */

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/******************************************************************************
* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
#ifndef XIL_PRINTF_H
#define XIL_PRINTF_H
#ifdef __cplusplus
extern "C" {
#endif
#include <ctype.h>
#include <string.h>
#include <stdarg.h>
#include "xil_types.h"
#include "xparameters.h"
#include "bspconfig.h"
#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
#include "xen_console.h"
#endif
/*----------------------------------------------------*/
/* Use the following parameter passing structure to */
/* make xil_printf re-entrant. */
/*----------------------------------------------------*/
struct params_s;
/*---------------------------------------------------*/
/* The purpose of this routine is to output data the */
/* same as the standard printf function without the */
/* overhead most run-time libraries involve. Usually */
/* the printf brings in many kilobytes of code and */
/* that is unacceptable in most embedded systems. */
/*---------------------------------------------------*/
typedef char8* charptr;
typedef s32 (*func_ptr)(int c);
/* */
void xil_printf( const char8 *ctrl1, ...);
void xil_vprintf(const char8 *ctrl1, va_list argp);
void print( const char8 *ptr);
extern void outbyte (char8 c);
extern char8 inbyte(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */

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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_assert.c
* @addtogroup common_assert_apis Assert APIs and Macros
* @{
*
* This file contains basic assert related functions for Xilinx software IP.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 Initial release
* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/**
* @brief This variable allows testing to be done easier with asserts. An assert
* sets this variable such that a driver can evaluate this variable
* to determine if an assert occurred.
*/
u32 Xil_AssertStatus;
/**
* @brief This variable allows the assert functionality to be changed for testing
* such that it does not wait infinitely. Use the debugger to disable the
* waiting during testing of asserts.
*/
s32 Xil_AssertWait = 1;
/* The callback function to be invoked when an assert is taken */
static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* @brief Implement assert. Currently, it calls a user-defined callback
* function if one has been set. Then, it potentially enters an
* infinite loop depending on the value of the Xil_AssertWait
* variable.
*
* @param File: filename of the source
* @param Line: linenumber within File
*
* @return None.
*
* @note None.
*
******************************************************************************/
void Xil_Assert(const char8 *File, s32 Line)
{
/* if the callback has been set then invoke it */
if (Xil_AssertCallbackRoutine != 0) {
(*Xil_AssertCallbackRoutine)(File, Line);
}
/* if specified, wait indefinitely such that the assert will show up
* in testing
*/
while (Xil_AssertWait != 0) {
}
}
/*****************************************************************************/
/**
*
* @brief Set up a callback function to be invoked when an assert occurs.
* If a callback is already installed, then it will be replaced.
*
* @param Routine: callback to be invoked when an assert is taken
*
* @return None.
*
* @note This function has no effect if NDEBUG is set
*
******************************************************************************/
void Xil_AssertSetCallback(Xil_AssertCallback Routine)
{
Xil_AssertCallbackRoutine = Routine;
}
/*****************************************************************************/
/**
*
* @brief Null handler function. This follows the XInterruptHandler
* signature for interrupt handlers. It can be used to assign a null
* handler (a stub) to an interrupt controller vector table.
*
* @param NullParameter: arbitrary void pointer and not used.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XNullHandler(void *NullParameter)
{
(void) NullParameter;
}
/**
* @} End of "addtogroup common_assert_apis".
*/

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/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xscutimer_hw.h
* @addtogroup scutimer_v2_3
* @{
*
* This file contains the hardware interface to the Timer.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a nm 03/10/10 First release
* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
* and interrupt registers
* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
* when the xstatus.h in the common driver overwrites
* the xstatus.h of the standalone BSP during the
* libgen.
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
* </pre>
*
******************************************************************************/
#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
#define XSCUTIMER_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_io.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
* Offsets of registers from the start of the device
* @{
*/
#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
Status Register */
/* @} */
/** @name Timer Control register
* This register bits control the prescaler, Intr enable,
* auto-reload and timer enable.
* @{
*/
#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
/* @} */
/** @name Interrupt Status register
* This register indicates the Timer counter register has reached zero.
* @{
*/
#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
/*@}*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Write to the timer load register. This will also update the
* timer counter register with the new value. This macro can be used to
* change the time-out value.
*
* @param BaseAddr is the base address of the scu timer.
* @param Value is the count to be loaded in to the load register.
*
* @return None.
*
* @note C-style signature:
* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
*
******************************************************************************/
#define XScuTimer_SetLoadReg(BaseAddr, Value) \
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
/****************************************************************************/
/**
*
* Returns the current timer load register value.
*
* @param BaseAddr is the base address of the scu timer.
*
* @return Contents of the timer load register.
*
* @note C-style signature:
* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
*
******************************************************************************/
#define XScuTimer_GetLoadReg(BaseAddr) \
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
/****************************************************************************/
/**
*
* Write to the timer counter register.
*
* @param BaseAddr is the base address of the scu timer.
* @param Value is the count to be loaded in to the counter register.
*
* @return None.
*
* @note C-style signature:
* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
*
******************************************************************************/
#define XScuTimer_SetCounterReg(BaseAddr, Value) \
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
/****************************************************************************/
/**
*
* Returns the current timer counter register value.
*
* @param BaseAddr is the base address of the scu timer.
*
* @return Contents of the timer counter register.
*
* @note C-style signature:
u32 XScuTimer_GetCounterReg(u32 BaseAddr)
*
******************************************************************************/
#define XScuTimer_GetCounterReg(BaseAddr) \
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
/****************************************************************************/
/**
*
* Write to the timer load register. This will also update the
* timer counter register with the new value. This macro can be used to
* change the time-out value.
*
* @param BaseAddr is the base address of the scu timer.
* @param Value is the count to be loaded in to the load register.
*
* @return None.
*
* @note C-style signature:
* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
*
******************************************************************************/
#define XScuTimer_SetControlReg(BaseAddr, Value) \
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
/****************************************************************************/
/**
*
* Returns the current timer load register value.
*
* @param BaseAddr is the base address of the scu timer.
*
* @return Contents of the timer load register.
*
* @note C-style signature:
u32 XScuTimer_GetControlReg(u32 BaseAddr)
*
******************************************************************************/
#define XScuTimer_GetControlReg(BaseAddr) \
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
/****************************************************************************/
/**
*
* Write to the timer counter register.
*
* @param BaseAddr is the base address of the scu timer.
* @param Value is the count to be loaded in to the counter register.
*
* @return None.
*
* @note C-style signature:
* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
*
******************************************************************************/
#define XScuTimer_SetIntrReg(BaseAddr, Value) \
XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
/****************************************************************************/
/**
*
* Returns the current timer counter register value.
*
* @param BaseAddr is the base address of the scu timer.
*
* @return Contents of the timer counter register.
*
* @note C-style signature:
u32 XScuTimer_GetIntrReg(u32 BaseAddr)
*
******************************************************************************/
#define XScuTimer_GetIntrReg(BaseAddr) \
XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
/****************************************************************************/
/**
*
* Read from the given Timer register.
*
* @param BaseAddr is the base address of the device
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note C-style signature:
* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
*
*****************************************************************************/
#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (RegOffset))
/****************************************************************************/
/**
*
* Write to the given Timer register.
*
* @param BaseAddr is the base address of the device
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note C-style signature:
* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (RegOffset), (Data))
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */

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/******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xtime_l.c
*
* This file contains low level functions to get/set time from the Global Timer
* register in the ARM Cortex A53 MP core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ---------------------------------------------------
* 5.00 pkp 05/29/14 First release
* 5.05 pkp 04/13/16 Added XTime_StartTimer API to start the global timer
* counter if it is disabled. Also XTime_GetTime calls
* this API to ensure the global timer counter is enabled
* 6.02 pkp 01/22/17 Added support for EL1 non-secure
* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
* displaying same warnings multiple times. It fixes CR#1090562.
* </pre>
*
* @note None.
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xtime_l.h"
#include "xpseudo_asm.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "bspconfig.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
#pragma message ("For the sleep routines, Global timer is being used")
#endif
/****************************************************************************/
/**
* @brief Start the 64-bit physical timer counter.
*
* @return None.
*
* @note The timer is initialized only if it is disabled. If the timer is
* already running this function does not perform any operation. This
* API is effective only if BSP is built for EL3. For EL1 Non-secure,
* it simply exits.
*
****************************************************************************/
void XTime_StartTimer(void)
{
if (EL3 == 1){
/* Enable the global timer counter only if it is disabled */
if(((Xil_In32(XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET))
& XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK) !=
XIOU_SCNTRS_CNT_CNTRL_REG_EN){
/*write frequency to System Time Stamp Generator Register*/
Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),
XIOU_SCNTRS_FREQ);
/*Enable the timer/counter*/
Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET)
,XIOU_SCNTRS_CNT_CNTRL_REG_EN);
}
}
}
/****************************************************************************/
/**
* @brief Timer of A53 runs continuously and the time can not be set as
* desired. This API doesn't contain anything. It is defined to have
* uniformity across platforms.
*
* @param Xtime_Global: 64bit value to be written to the physical timer
* counter register. Since API does not do anything, the value is
* not utilized.
*
* @return None.
*
****************************************************************************/
void XTime_SetTime(XTime Xtime_Global)
{
(void) Xtime_Global;
/*As the generic timer of A53 runs constantly time can not be set as desired
so the API is left unimplemented*/
}
/****************************************************************************/
/**
* @brief Get the time from the physical timer counter register.
*
* @param Xtime_Global: Pointer to the 64-bit location to be updated with the
* current value of physical timer counter register.
*
* @return None.
*
****************************************************************************/
void XTime_GetTime(XTime *Xtime_Global)
{
if (EL3 == 1)
/* Start global timer counter, it will only be enabled if it is disabled */
XTime_StartTimer();
*Xtime_Global = mfcp(CNTPCT_EL0);
}

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/******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xreg_cortexr5.h
*
* This header file contains definitions for using inline assembler code. It is
* written specifically for the GNU, IAR, ARMCC compiler.
*
* All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along
* with the positions of the bits within the registers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 02/10/14 Initial version
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */
#define XREG_CORTEXR5_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* GPRs */
#define XREG_GPR0 r0
#define XREG_GPR1 r1
#define XREG_GPR2 r2
#define XREG_GPR3 r3
#define XREG_GPR4 r4
#define XREG_GPR5 r5
#define XREG_GPR6 r6
#define XREG_GPR7 r7
#define XREG_GPR8 r8
#define XREG_GPR9 r9
#define XREG_GPR10 r10
#define XREG_GPR11 r11
#define XREG_GPR12 r12
#define XREG_GPR13 r13
#define XREG_GPR14 r14
#define XREG_GPR15 r15
#define XREG_CPSR cpsr
/* Coprocessor number defines */
#define XREG_CP0 0
#define XREG_CP1 1
#define XREG_CP2 2
#define XREG_CP3 3
#define XREG_CP4 4
#define XREG_CP5 5
#define XREG_CP6 6
#define XREG_CP7 7
#define XREG_CP8 8
#define XREG_CP9 9
#define XREG_CP10 10
#define XREG_CP11 11
#define XREG_CP12 12
#define XREG_CP13 13
#define XREG_CP14 14
#define XREG_CP15 15
/* Coprocessor control register defines */
#define XREG_CR0 cr0
#define XREG_CR1 cr1
#define XREG_CR2 cr2
#define XREG_CR3 cr3
#define XREG_CR4 cr4
#define XREG_CR5 cr5
#define XREG_CR6 cr6
#define XREG_CR7 cr7
#define XREG_CR8 cr8
#define XREG_CR9 cr9
#define XREG_CR10 cr10
#define XREG_CR11 cr11
#define XREG_CR12 cr12
#define XREG_CR13 cr13
#define XREG_CR14 cr14
#define XREG_CR15 cr15
/* Current Processor Status Register (CPSR) Bits */
#define XREG_CPSR_THUMB_MODE 0x20U
#define XREG_CPSR_MODE_BITS 0x1FU
#define XREG_CPSR_SYSTEM_MODE 0x1FU
#define XREG_CPSR_UNDEFINED_MODE 0x1BU
#define XREG_CPSR_DATA_ABORT_MODE 0x17U
#define XREG_CPSR_SVC_MODE 0x13U
#define XREG_CPSR_IRQ_MODE 0x12U
#define XREG_CPSR_FIQ_MODE 0x11U
#define XREG_CPSR_USER_MODE 0x10U
#define XREG_CPSR_IRQ_ENABLE 0x80U
#define XREG_CPSR_FIQ_ENABLE 0x40U
#define XREG_CPSR_N_BIT 0x80000000U
#define XREG_CPSR_Z_BIT 0x40000000U
#define XREG_CPSR_C_BIT 0x20000000U
#define XREG_CPSR_V_BIT 0x10000000U
/*MPU region definitions*/
#define REGION_32B 0x00000004U
#define REGION_64B 0x00000005U
#define REGION_128B 0x00000006U
#define REGION_256B 0x00000007U
#define REGION_512B 0x00000008U
#define REGION_1K 0x00000009U
#define REGION_2K 0x0000000AU
#define REGION_4K 0x0000000BU
#define REGION_8K 0x0000000CU
#define REGION_16K 0x0000000DU
#define REGION_32K 0x0000000EU
#define REGION_64K 0x0000000FU
#define REGION_128K 0x00000010U
#define REGION_256K 0x00000011U
#define REGION_512K 0x00000012U
#define REGION_1M 0x00000013U
#define REGION_2M 0x00000014U
#define REGION_4M 0x00000015U
#define REGION_8M 0x00000016U
#define REGION_16M 0x00000017U
#define REGION_32M 0x00000018U
#define REGION_64M 0x00000019U
#define REGION_128M 0x0000001AU
#define REGION_256M 0x0000001BU
#define REGION_512M 0x0000001CU
#define REGION_1G 0x0000001DU
#define REGION_2G 0x0000001EU
#define REGION_4G 0x0000001FU
#define REGION_EN 0x00000001U
#define SHAREABLE 0x00000004U /*shareable */
#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/
#define DEVICE_SHARED 0x00000001U /*device, shareable*/
#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/
#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/
#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/
#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/
#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/
#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/
#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/
#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/
#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/
/* inner and outer cache policies can be combined for different combinations */
#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/
#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/
#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/
#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/
#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/
#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/
#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/
#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/
#define NO_ACCESS (0x00000000U<<8U) /*No access*/
#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/
#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/
#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/
#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/
#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/
#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/
/* CP15 defines */
/* C0 Register defines */
#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4"
#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5"
#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
/* C1 Register Defines */
#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
/* XREG_CP15_CONTROL bit defines */
#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
#define XREG_CP15_CONTROL_V_BIT 0x00002000U
#define XREG_CP15_CONTROL_I_BIT 0x00001000U
#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
#define XREG_CP15_CONTROL_B_BIT 0x00000080U
#define XREG_CP15_CONTROL_C_BIT 0x00000004U
#define XREG_CP15_CONTROL_A_BIT 0x00000002U
#define XREG_CP15_CONTROL_M_BIT 0x00000001U
/* C2 Register Defines */
/* Not Used */
/* C3 Register Defines */
/* Not Used */
/* C4 Register Defines */
/* Not Used */
/* C5 Register Defines */
#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
/* C6 Register Defines */
#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0"
#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2"
#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4"
#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0"
/* C7 Register Defines */
#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
/* The CP15 register access below has been deprecated in favor of the new
* isb instruction in Cortex R5.
*/
#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7"
#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0"
/* The next two CP15 register accesses below have been deprecated in favor
* of the new dsb and dmb instructions in Cortex R5.
*/
#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
/* C8 Register Defines */
/* Not Used */
/* C9 Register Defines */
#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1"
#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0"
#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0"
#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
/* C10 Register Defines */
/* Not used */
/* C11 Register Defines */
/* Not used */
/* C12 Register Defines */
/* Not used */
/* C13 Register Defines */
#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
/* C14 Register Defines */
/* not used */
/* C15 Register Defines */
#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0"
/* MPE register definitions */
#define XREG_FPSID c0
#define XREG_FPSCR c1
#define XREG_MVFR1 c6
#define XREG_MVFR0 c7
#define XREG_FPEXC c8
#define XREG_FPINST c9
#define XREG_FPINST2 c10
/* FPSID bits */
#define XREG_FPSID_IMPLEMENTER_BIT (24U)
#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT)
#define XREG_FPSID_SOFTWARE (0X00000001U << 23U)
#define XREG_FPSID_ARCH_BIT (16U)
#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT)
#define XREG_FPSID_PART_BIT (8U)
#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT)
#define XREG_FPSID_VARIANT_BIT (4U)
#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT)
#define XREG_FPSID_REV_BIT (0U)
#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT)
/* FPSCR bits */
#define XREG_FPSCR_N_BIT (0X00000001U << 31U)
#define XREG_FPSCR_Z_BIT (0X00000001U << 30U)
#define XREG_FPSCR_C_BIT (0X00000001U << 29U)
#define XREG_FPSCR_V_BIT (0X00000001U << 28U)
#define XREG_FPSCR_QC (0X00000001U << 27U)
#define XREG_FPSCR_AHP (0X00000001U << 26U)
#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U)
#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U)
#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U)
#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U)
#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U)
#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U)
#define XREG_FPSCR_RMODE_BIT (22U)
#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT)
#define XREG_FPSCR_STRIDE_BIT (20U)
#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT)
#define XREG_FPSCR_LENGTH_BIT (16U)
#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT)
#define XREG_FPSCR_IDC (0X00000001U << 7U)
#define XREG_FPSCR_IXC (0X00000001U << 4U)
#define XREG_FPSCR_UFC (0X00000001U << 3U)
#define XREG_FPSCR_OFC (0X00000001U << 2U)
#define XREG_FPSCR_DZC (0X00000001U << 1U)
#define XREG_FPSCR_IOC (0X00000001U << 0U)
/* MVFR0 bits */
#define XREG_MVFR0_RMODE_BIT (28U)
#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT)
#define XREG_MVFR0_SHORT_VEC_BIT (24U)
#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
#define XREG_MVFR0_SQRT_BIT (20U)
#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT)
#define XREG_MVFR0_DIVIDE_BIT (16U)
#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
#define XREG_MVFR0_EXEC_TRAP_BIT (12U)
#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
#define XREG_MVFR0_DP_BIT (8U)
#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT)
#define XREG_MVFR0_SP_BIT (4U)
#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT)
#define XREG_MVFR0_A_SIMD_BIT (0U)
#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT)
/* FPEXC bits */
#define XREG_FPEXC_EX (0X00000001U << 31U)
#define XREG_FPEXC_EN (0X00000001U << 30U)
#define XREG_FPEXC_DEX (0X00000001U << 29U)
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XREG_CORTEXR5_H */
/**
*@endcond
*/

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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/******************************************************************************/
/**
* @file xusbps_intr.c
* @addtogroup usbps_v2_7
* @{
*
* This file contains the functions that are related to interrupt processing
* for the EPB USB driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ----------------------------------------------------------
* 1.00a jz 10/10/10 First release
* 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
* handling.
* 2.3 bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
* (moving of dTD Head/Tail Pointers properly).
* 2.5 pm 02/20/20 Added ISO endpoint support.
* </pre>
******************************************************************************/
/***************************** Include Files **********************************/
#include "xusbps.h"
#include "xusbps_endpoint.h"
/************************** Constant Definitions ******************************/
/**************************** Type Definitions ********************************/
/***************** Macros (Inline Functions) Definitions **********************/
/************************** Variable Definitions ******************************/
/************************** Function Prototypes *******************************/
static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl);
static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl);
static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts);
static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr);
/*****************************************************************************/
/**
* This function is the first-level interrupt handler for the USB core. All USB
* interrupts will be handled here. Depending on the type of the interrupt,
* second level interrupt handler may be called. Second level interrupt
* handlers will be registered by the user using the:
* XUsbPs_IntrSetHandler()
* and/or
* XUsbPs_EpSetHandler()
* functions.
*
*
* @param HandlerRef is a Reference passed to the interrupt register
* function. In our case this will be a pointer to the XUsbPs
* instance.
*
* @return None
*
* @note None
*
******************************************************************************/
void XUsbPs_IntrHandler(void *HandlerRef)
{
XUsbPs *InstancePtr;
u32 IrqSts;
Xil_AssertVoid(HandlerRef != NULL);
InstancePtr = (XUsbPs *) HandlerRef;
/* Handle controller (non-endpoint) related interrupts. */
IrqSts = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_ISR_OFFSET);
/* Clear the interrupt status register. */
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
XUSBPS_ISR_OFFSET, IrqSts);
/* Nak interrupt, used to respond to host's IN request */
if(IrqSts & XUSBPS_IXR_NAK_MASK) {
/* Ack the hardware */
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPNAKISR_OFFSET,
XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPNAKISR_OFFSET));
}
/***************************************************************
*
* Handle general interrupts. Endpoint interrupts will be handler
* later.
*
*/
/* RESET interrupt.*/
if (IrqSts & XUSBPS_IXR_UR_MASK) {
XUsbPs_IntrHandleReset(InstancePtr, IrqSts);
return;
}
/* Check if we have a user handler that needs to be called. Note that
* this is the handler for general interrupts. Endpoint interrupts will
* be handled below.
*/
if ((IrqSts & InstancePtr->HandlerMask) && InstancePtr->HandlerFunc) {
(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
}
/***************************************************************
*
* Handle Endpoint interrupts.
*
*/
if (IrqSts & XUSBPS_IXR_UI_MASK) {
u32 EpStat;
u32 EpCompl;
/* ENDPOINT 0 SETUP PACKET HANDLING
*
* Check if we got a setup packet on endpoint 0. Currently we
* only check for setup packets on endpoint 0 as we would not
* expect setup packets on any other endpoint (even though it
* is possible to send setup packets on other endpoints).
*/
EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPSTAT_OFFSET);
if (EpStat & 0x0001) {
/* Handle the setup packet */
XUsbPs_IntrHandleEp0Setup(InstancePtr);
/* Re-Prime the endpoint.
* Endpoint is de-primed if a setup packet comes in.
*/
XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT);
}
/* Check for RX and TX complete interrupts. */
EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPCOMPL_OFFSET);
/* ACK the complete interrupts. */
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPCOMPL_OFFSET, EpCompl);
/* Check OUT (RX) endpoints. */
if (EpCompl & XUSBPS_EP_OUT_MASK) {
XUsbPs_IntrHandleRX(InstancePtr, EpCompl);
}
/* Check IN (TX) endpoints. */
if (EpCompl & XUSBPS_EP_IN_MASK) {
XUsbPs_IntrHandleTX(InstancePtr, EpCompl);
}
}
}
/*****************************************************************************/
/**
* This function registers the user callback handler for controller
* (non-endpoint) interrupts.
*
* @param InstancePtr is a pointer to the XUsbPs instance of the
* controller.
* @param CallBackFunc is the Callback function to register.
* CallBackFunc may be NULL to clear the entry.
* @param CallBackRef is the user data reference passed to the
* callback function. CallBackRef may be NULL.
* @param Mask is the User interrupt mask. Defines which interrupts
* will cause the callback to be called.
*
* @return
* - XST_SUCCESS: Callback registered successfully.
* - XST_FAILURE: Callback could not be registered.
*
* @note None.
*
******************************************************************************/
int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
XUsbPs_IntrHandlerFunc CallBackFunc,
void *CallBackRef, u32 Mask)
{
Xil_AssertNonvoid(InstancePtr != NULL);
InstancePtr->HandlerFunc = CallBackFunc;
InstancePtr->HandlerRef = CallBackRef;
InstancePtr->HandlerMask = Mask;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function handles TX buffer interrupts. It is called by the interrupt
* when a transmit complete interrupt occurs. It returns buffers of completed
* descriptors to the caller.
*
* @param InstancePtr is a pointer to the XUsbPs instance of the
* controller.
* @param EpCompl is the Bit mask of endpoints that caused a transmit
* complete interrupt.
*
* @return None
*
* @note None.
*
******************************************************************************/
static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl)
{
int Index;
u32 Mask;
int NumEp;
/* Check all endpoints for TX complete bits.
*/
Mask = 0x00010000;
NumEp = InstancePtr->DeviceConfig.NumEndpoints;
/* Check for every endpoint if its TX complete bit is
* set.
*/
for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
XUsbPs_EpIn *Ep;
if (!(EpCompl & Mask)) {
continue;
}
/* The TX complete bit for this endpoint is
* set. Walk the list of descriptors to see
* which ones are completed.
*/
Ep = &InstancePtr->DeviceConfig.Ep[Index].In;
do {
XUsbPs_dTDInvalidateCache(Ep->dTDTail);
/* If the descriptor is not active then the buffer has
* not been sent yet.
*/
if (XUsbPs_dTDIsActive(Ep->dTDTail)) {
break;
}
if (InstancePtr->DeviceConfig.EpCfg[Index].In.Type ==
XUSBPS_EP_TYPE_ISOCHRONOUS) {
if (Ep->HandlerIsoFunc) {
Ep->HandlerIsoFunc(Ep->HandlerRef,
Ep->RequestedBytes,
Ep->BytesTxed);
}
} else {
if (Ep->HandlerFunc) {
void *BufPtr;
BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail,
XUSBPS_dTDUSERDATA);
Ep->HandlerFunc(Ep->HandlerRef, Index,
XUSBPS_EP_EVENT_DATA_TX,
BufPtr);
}
}
Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail);
} while(Ep->dTDTail != Ep->dTDHead);
}
}
/*****************************************************************************/
/**
* This function handles RX buffer interrupts. It is called by the interrupt
* when a receive complete interrupt occurs. It notifies the callback functions
* that have been registered with the individual endpoints that data has been
* received.
*
* @param InstancePtr
* Pointer to the XUsbPs instance of the controller.
*
* @param EpCompl
* Bit mask of endpoints that caused a receive complete interrupt.
* @return
* none
*
******************************************************************************/
static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl)
{
XUsbPs_EpOut *Ep;
int Index;
u32 Mask;
int NumEp;
/* Check all endpoints for RX complete bits. */
Mask = 0x00000001;
NumEp = InstancePtr->DeviceConfig.NumEndpoints;
/* Check for every endpoint if its RX complete bit is set.*/
for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
int numP = 0;
if (!(EpCompl & Mask)) {
continue;
}
Ep = &InstancePtr->DeviceConfig.Ep[Index].Out;
XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
/* Handle all finished dTDs */
while (!XUsbPs_dTDIsActive(Ep->dTDCurr)) {
numP += 1;
/* We get data RX events for 0 length packets on
* endpoint 0. We receive and immediately release
* them again here, but there's no action to be
* taken.
*/
if (InstancePtr->DeviceConfig.EpCfg[Index].Out.Type ==
XUSBPS_EP_TYPE_ISOCHRONOUS){
if (Index == 0) {
u8 BufferPtr[64] = {0};
/* Get the data buffer. */
XUsbPs_EpDataBufferReceive(InstancePtr,
0, &BufferPtr[0], 64);
Ep->MemAlloted = 0;
}
if (Ep->MemAlloted == 1) {
XUsbPs_EpGetData(InstancePtr, Index,
Ep->RequestedBytes);
} else
break;
} else {
if (Ep->HandlerFunc) {
Ep->HandlerFunc(Ep->HandlerRef, Index,
XUSBPS_EP_EVENT_DATA_RX, NULL);
}
Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr);
XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
}
}
/* Re-Prime the endpoint.*/
XUsbPs_EpPrime(InstancePtr, Index, XUSBPS_EP_DIRECTION_OUT);
}
}
/*****************************************************************************/
/**
* This function handles a RESET interrupt. It will notify the interrupt
* handler callback of the RESET condition.
*
* @param InstancePtr is pointer to the XUsbPs instance of the controller
* @param IrqSts is the Interrupt status register content.
* To be passed on to the user.
*
* @return None
*
* @Note None.
*
******************************************************************************/
static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts)
{
u32 Timeout;
u8 Index;
if (InstancePtr->AppData != NULL)
InstancePtr->AppData->State = XUSBPS_STATE_DEFAULT;
for (Index = 0; Index < InstancePtr->DeviceConfig.NumEndpoints;
Index++) {
InstancePtr->DeviceConfig.Ep[Index].Out.MemAlloted = 0;
InstancePtr->DeviceConfig.Ep[Index].Out.BufferPtr = NULL;
InstancePtr->DeviceConfig.Ep[Index].Out.BytesTxed = 0;
InstancePtr->DeviceConfig.Ep[Index].Out.RequestedBytes = 0;
InstancePtr->DeviceConfig.Ep[Index].In.BufferPtr = NULL;
InstancePtr->DeviceConfig.Ep[Index].In.BytesTxed = 0;
InstancePtr->DeviceConfig.Ep[Index].In.RequestedBytes = 0;
}
/* Clear all setup token semaphores by reading the
* XUSBPS_EPSTAT_OFFSET register and writing its value back to
* itself.
*/
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPSTAT_OFFSET));
/* Clear all the endpoint complete status bits by reading the
* XUSBPS_EPCOMPL_OFFSET register and writings its value back
* to itself.
*/
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPCOMPL_OFFSET,
XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPCOMPL_OFFSET));
/* Cancel all endpoint prime status by waiting until all bits
* in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
* to XUSBPS_EPFLUSH_OFFSET.
*
* Avoid hanging here by using a Timeout counter...
*/
Timeout = XUSBPS_TIMEOUT_COUNTER;
while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPPRIME_OFFSET) &
XUSBPS_EP_ALL_MASK) && --Timeout) {
/* NOP */
}
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
/* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is
* still set at this point. If the code gets to this point and
* the reset bit has already been cleared we are in trouble and
* hardware reset is necessary.
*/
if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_PORTSCR1_OFFSET) &
XUSBPS_PORTSCR_PR_MASK)) {
/* Send a notification to the user that a hardware
* RESET is required. At this point we can only hope
* that the user registered an interrupt handler and
* will issue a hardware RESET.
*/
if (InstancePtr->HandlerFunc) {
(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef,
IrqSts);
}
else {
for (;;);
}
/* If we get here there is nothing more to do. The user
* should have reset the core.
*/
return;
}
/* Check if we have a user handler that needs to be called.
*/
if (InstancePtr->HandlerFunc) {
(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
}
/* We are done. After RESET we don't proceed in the interrupt
* handler.
*/
}
/*****************************************************************************/
/**
* This function handles a Setup Packet interrupt. It will notify the interrupt
* handler callback of the RESET condition.
*
* @param InstancePtr is a pointer to the XUsbPs instance of the
* controller.
*
* @return None
*
* @Note None
*
******************************************************************************/
static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr)
{
XUsbPs_EpOut *Ep;
/* Notify the user. */
Ep = &InstancePtr->DeviceConfig.Ep[0].Out;
if (Ep->HandlerFunc) {
Ep->HandlerFunc(Ep->HandlerRef, 0,
XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED, NULL);
}
}
/** @} */

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/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/* read.c -- read bytes from a input device.
*/
#ifndef UNDEFINE_FILE_OPS
#include "xil_printf.h"
#include "xparameters.h"
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
}
#endif
/*
* read -- read bytes from the serial port. Ignore fd, since
* we only have stdin.
*/
__attribute__((weak)) s32
read (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDIN_BASEADDRESS
s32 i;
s32 numbytes = 0;
char8* LocalBuf = buf;
(void)fd;
if(LocalBuf != NULL) {
for (i = 0; i < nbytes; i++) {
numbytes++;
*(LocalBuf + i) = inbyte();
if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
break;
}
}
}
return numbytes;
#else
(void)fd;
(void)buf;
(void)nbytes;
return 0;
#endif
}
__attribute__((weak)) s32
_read (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDIN_BASEADDRESS
s32 i;
s32 numbytes = 0;
char8* LocalBuf = buf;
(void)fd;
if(LocalBuf != NULL) {
for (i = 0; i < nbytes; i++) {
numbytes++;
*(LocalBuf + i) = inbyte();
if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
break;
}
}
}
return numbytes;
#else
(void)fd;
(void)buf;
(void)nbytes;
return 0;
#endif
}
#endif

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/******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file boot.S
*
* @addtogroup a53_64_boot_code Cortex A53 64bit Processor Boot Code
* @{
* <h2> boot.S </h2>
*
* The boot code performs minimum configuration which is required for an
* application. Cortex-A53 starts by checking current exception level. If the
* current exception level is EL3 and BSP is built for EL3, it will do
* initialization required for application execution at EL3. Below is a
* sequence illustrating what all configuration is performed before control
* reaches to main function for EL3 execution.
*
* 1. Program vector table base for exception handling
* 2. Set reset vector table base address
* 3. Program stack pointer for EL3
* 4. Routing of interrupts to EL3
* 5. Enable ECC protection
* 6. Program generic counter frequency
* 7. Invalidate instruction cache, data cache and TLBs
* 8. Configure MMU registers and program base address of translation table
* 9. Transfer control to _start which clears BSS sections and runs global
* constructor before jumping to main application
*
* If the current exception level is EL1 and BSP is also built for EL1_NONSECURE
* it will perform initialization required for application execution at EL1
* non-secure. For all other combination, the execution will go into infinite
* loop. Below is a sequence illustrating what all configuration is performed
* before control reaches to main function for EL1 execution.
*
* 1. Program vector table base for exception handling
* 2. Program stack pointer for EL1
* 3. Invalidate instruction cache, data cache and TLBs
* 4. Configure MMU registers and program base address of translation table
* 5. Transfer control to _start which clears BSS sections and runs global
* constructor before jumping to main application
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 5.00 pkp 05/21/14 Initial version
* 6.00 pkp 07/25/16 Program the counter frequency
* 6.02 pkp 01/22/17 Added support for EL1 non-secure
* 6.02 pkp 01/24/17 Clearing status of FPUStatus variable to ensure it
* holds correct value.
* 6.3 mus 04/20/17 CPU Cache protection bit in the L2CTLR_EL1 will be in
* set state on reset. So, setting that bit through boot
* code is redundant, hence removed the code which sets
* CPU cache protection bit.
* 6.4 mus 08/11/17 Implemented ARM erratum 855873.It fixes
* CR#982209.
* 6.6 mus 01/19/18 Added isb after writing to the cpacr_el1/cptr_el3,
* to ensure floating-point unit is disabled, before
* any subsequent instruction.
* 7.0 mus 03/26/18 Updated TCR_EL3/TCR_EL1 as per versal address map
* 7.3 mus 04/24/20 Corrected CPACR_EL1 handling at EL1 NS
*
* </pre>
*
******************************************************************************/
#include "xparameters.h"
#include "bspconfig.h"
#include "xil_errata.h"
.globl MMUTableL0
.globl MMUTableL1
.globl MMUTableL2
.global _prestart
.global _boot
.global __el3_stack
.global __el2_stack
.global __el1_stack
.global __el0_stack
.global _vector_table
.set EL3_stack, __el3_stack
.set EL2_stack, __el2_stack
.set EL1_stack, __el1_stack
.set EL0_stack, __el0_stack
.set TT_S1_FAULT, 0x0
.set TT_S1_TABLE, 0x3
.set L0Table, MMUTableL0
.set L1Table, MMUTableL1
.set L2Table, MMUTableL2
.set vector_base, _vector_table
.set rvbar_base, 0xFD5C0040
#if defined (versal)
.set counterfreq, XPAR_CPU_CORTEXA72_0_TIMESTAMP_CLK_FREQ
#else
.set counterfreq, XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
#endif
.set MODE_EL1, 0x5
.set DAIF_BIT, 0x1C0
.section .boot,"ax"
/* this initializes the various processor modes */
_prestart:
_boot:
mov x0, #0
mov x1, #0
mov x2, #0
mov x3, #0
mov x4, #0
mov x5, #0
mov x6, #0
mov x7, #0
mov x8, #0
mov x9, #0
mov x10, #0
mov x11, #0
mov x12, #0
mov x13, #0
mov x14, #0
mov x15, #0
mov x16, #0
mov x17, #0
mov x18, #0
mov x19, #0
mov x20, #0
mov x21, #0
mov x22, #0
mov x23, #0
mov x24, #0
mov x25, #0
mov x26, #0
mov x27, #0
mov x28, #0
mov x29, #0
mov x30, #0
#if 0 //don't put other a53 cpus in wfi
//Which core am I
// ----------------
mrs x0, MPIDR_EL1
and x0, x0, #0xFF //Mask off to leave Aff0
cbz x0, OKToRun //If core 0, run the primary init code
EndlessLoop0:
wfi
b EndlessLoop0
#endif
OKToRun:
mrs x0, currentEL
cmp x0, #0xC
beq InitEL3
cmp x0, #0x4
beq InitEL1
b error // go to error if current exception level is neither EL3 nor EL1
InitEL3:
.if (EL3 == 1)
/*Set vector table base address*/
ldr x1, =vector_base
msr VBAR_EL3,x1
/* Set reset vector address */
/* Get the cpu ID */
mrs x0, MPIDR_EL1
and x0, x0, #0xFF
mov w0, w0
ldr w2, =rvbar_base
/* calculate the rvbar base address for particular CPU core */
mov w3, #0x8
mul w0, w0, w3
add w2, w2, w0
/* store vector base address to RVBAR */
str x1, [x2]
/*Define stack pointer for current exception level*/
ldr x2,=EL3_stack
mov sp,x2
/* Enable Trapping of SIMD/FPU register for standalone BSP */
mov x0, #0
#ifndef FREERTOS_BSP
orr x0, x0, #(0x1 << 10)
#endif
msr CPTR_EL3, x0
isb
/*
* Clear FPUStatus variable to make sure that it contains current
* status of FPU i.e. disabled. In case of a warm restart execution
* when bss sections are not cleared, it may contain previously updated
* value which does not hold true now.
*/
#ifndef FREERTOS_BSP
ldr x0,=FPUStatus
str xzr, [x0]
#endif
/* Configure SCR_EL3 */
mov w1, #0 //; Initial value of register is unknown
orr w1, w1, #(1 << 11) //; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
orr w1, w1, #(1 << 10) //; Set RW bit (EL1 is AArch64, as this is the Secure world)
orr w1, w1, #(1 << 3) //; Set EA bit (SError routed to EL3)
orr w1, w1, #(1 << 2) //; Set FIQ bit (FIQs routed to EL3)
orr w1, w1, #(1 << 1) //; Set IRQ bit (IRQs routed to EL3)
msr SCR_EL3, x1
/*configure cpu auxiliary control register EL1 */
ldr x0,=0x80CA000 // L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
#if CONFIG_ARM_ERRATA_855873
/*
* Set ENDCCASCI bit in CPUACTLR_EL1 register, to execute data
* cache clean operations as data cache clean and invalidate
*
*/
orr x0, x0, #(1 << 44) //; Set ENDCCASCI bit
#endif
msr S3_1_C15_C2_0, x0 //CPUACTLR_EL1
/* program the counter frequency */
ldr x0,=counterfreq
msr CNTFRQ_EL0, x0
/*Enable hardware coherency between cores*/
mrs x0, S3_1_c15_c2_1 //Read EL1 CPU Extended Control Register
orr x0, x0, #(1 << 6) //Set the SMPEN bit
msr S3_1_c15_c2_1, x0 //Write EL1 CPU Extended Control Register
isb
tlbi ALLE3
ic IALLU //; Invalidate I cache to PoU
bl invalidate_dcaches
dsb sy
isb
ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL3
msr TTBR0_EL3, x1 //; Set TTBR0_EL3
/**********************************************
* Set up memory attributes
* This equates to:
* 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
* 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
* 2 = b00000000 = Device-nGnRnE
* 3 = b00000100 = Device-nGnRE
* 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
**********************************************/
ldr x1, =0x000000BB0400FF44
msr MAIR_EL3, x1
#if defined (versal)
/**********************************************
* Set up TCR_EL3
* Physical Address Size PS = 100 -> 44bits 16 TB
* Granual Size TG0 = 00 -> 4KB
* size offset of the memory region T0SZ = 20 -> (region size 2^(64-20) = 2^44)
***************************************************/
ldr x1,=0x80843514
#else
/**********************************************
* Set up TCR_EL3
* Physical Address Size PS = 010 -> 40bits 1TB
* Granual Size TG0 = 00 -> 4KB
* size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
***************************************************/
ldr x1,=0x80823518
#endif
msr TCR_EL3, x1
isb
/* Enable SError Exception for asynchronous abort */
mrs x1,DAIF
bic x1,x1,#(0x1<<8)
msr DAIF,x1
/* Configure SCTLR_EL3 */
mov x1, #0 //Most of the SCTLR_EL3 bits are unknown at reset
orr x1, x1, #(1 << 12) //Enable I cache
orr x1, x1, #(1 << 3) //Enable SP alignment check
orr x1, x1, #(1 << 2) //Enable caches
orr x1, x1, #(1 << 0) //Enable MMU
msr SCTLR_EL3, x1
dsb sy
isb
b _startup //jump to start
.else
b error // present exception level and selected exception level mismatch
.endif
InitEL1:
.if (EL1_NONSECURE == 1)
/*Set vector table base address*/
ldr x1, =vector_base
msr VBAR_EL1,x1
/* Trap floating point access only in case of standalone BSP */
#ifdef FREERTOS_BSP
mrs x0, CPACR_EL1
orr x0, x0, #(0x3 << 20)
msr CPACR_EL1, x0
#else
mrs x0, CPACR_EL1
bic x0, x0, #(0x3 << 20)
msr CPACR_EL1, x0
#endif
isb
/*
* Clear FPUStatus variable to make sure that it contains current
* status of FPU i.e. disabled. In case of a warm restart execution
* when bss sections are not cleared, it may contain previously updated
* value which does not hold true now.
*/
#ifndef FREERTOS_BSP
ldr x0,=FPUStatus
str xzr, [x0]
#endif
/*Define stack pointer for current exception level*/
ldr x2,=EL1_stack
mov sp,x2
/* Disable MMU first */
mov x1,#0x0
msr SCTLR_EL1, x1
isb
TLBI VMALLE1
ic IALLU //; Invalidate I cache to PoU
bl invalidate_dcaches
dsb sy
isb
ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL1
msr TTBR0_EL1, x1 //; Set TTBR0_EL1
/**********************************************
* Set up memory attributes
* This equates to:
* 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
* 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
* 2 = b00000000 = Device-nGnRnE
* 3 = b00000100 = Device-nGnRE
* 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
**********************************************/
ldr x1, =0x000000BB0400FF44
msr MAIR_EL1, x1
#if defined (versal)
/**********************************************
* Set up TCR_EL1
* Physical Address Size PS = 100 -> 44bits 16TB
* Granual Size TG0 = 00 -> 4KB
* size offset of the memory region T0SZ = 20 -> (region size 2^(64-20) = 2^44)
***************************************************/
ldr x1,=0x485800514
#else
/**********************************************
* Set up TCR_EL1
* Physical Address Size PS = 010 -> 44bits 16TB
* Granual Size TG0 = 00 -> 4KB
* size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
***************************************************/
ldr x1,=0x285800518
#endif
msr TCR_EL1, x1
isb
/* Enable SError Exception for asynchronous abort */
mrs x1,DAIF
bic x1,x1,#(0x1<<8)
msr DAIF,x1
//; Enable MMU
mov x1,#0x0
orr x1, x1, #(1 << 18) // ; Set WFE non trapping
orr x1, x1, #(1 << 17) // ; Set WFI non trapping
orr x1, x1, #(1 << 5) // ; Set CP15 barrier enabled
orr x1, x1, #(1 << 12) // ; Set I bit
orr x1, x1, #(1 << 2) // ; Set C bit
orr x1, x1, #(1 << 0) // ; Set M bit
msr SCTLR_EL1, x1
isb
bl _startup //jump to start
.else
b error // present exception level and selected exception level mismatch
.endif
error: b error
invalidate_dcaches:
dmb ISH
mrs x0, CLIDR_EL1 //; x0 = CLIDR
ubfx w2, w0, #24, #3 //; w2 = CLIDR.LoC
cmp w2, #0 //; LoC is 0?
b.eq invalidateCaches_end //; No cleaning required and enable MMU
mov w1, #0 //; w1 = level iterator
invalidateCaches_flush_level:
add w3, w1, w1, lsl #1 //; w3 = w1 * 3 (right-shift for cache type)
lsr w3, w0, w3 //; w3 = w0 >> w3
ubfx w3, w3, #0, #3 //; w3 = cache type of this level
cmp w3, #2 //; No cache at this level?
b.lt invalidateCaches_next_level
lsl w4, w1, #1
msr CSSELR_EL1, x4 //; Select current cache level in CSSELR
isb //; ISB required to reflect new CSIDR
mrs x4, CCSIDR_EL1 //; w4 = CSIDR
ubfx w3, w4, #0, #3
add w3, w3, #2 //; w3 = log2(line size)
ubfx w5, w4, #13, #15
ubfx w4, w4, #3, #10 //; w4 = Way number
clz w6, w4 //; w6 = 32 - log2(number of ways)
invalidateCaches_flush_set:
mov w8, w4 //; w8 = Way number
invalidateCaches_flush_way:
lsl w7, w1, #1 //; Fill level field
lsl w9, w5, w3
orr w7, w7, w9 //; Fill index field
lsl w9, w8, w6
orr w7, w7, w9 //; Fill way field
dc CISW, x7 //; Invalidate by set/way to point of coherency
subs w8, w8, #1 //; Decrement way
b.ge invalidateCaches_flush_way
subs w5, w5, #1 //; Descrement set
b.ge invalidateCaches_flush_set
invalidateCaches_next_level:
add w1, w1, #1 //; Next level
cmp w2, w1
b.gt invalidateCaches_flush_level
invalidateCaches_end:
ret
.end
/**
* @} End of "addtogroup a53_64_boot_code".
*/

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/******************************************************************************
* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_spinlock.h
*
* This header file contains function prototypes to be used while using Xilinx
* spinlocking mechanism.
* Please refer to file header contents of xil_spinlock.c to understand in
* detail the spinlocking mechanism.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 7.5 asa 02/16/21 First release
* 7.6 sk 08/05/21 Add Boolean check and braces for Xil_IsSpinLockEnabled
* if condition to fix misrac violations.
* </pre>
*
******************************************************************************/
#ifndef XIL_SPINLOCK_H /* prevent circular inclusions */
#define XIL_SPINLOCK_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xstatus.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
/************************** Function Prototypes *****************************/
u32 Xil_SpinLock(void);
u32 Xil_SpinUnlock(void);
u32 Xil_InitializeSpinLock(UINTPTR lockaddr, UINTPTR lockflagaddr,
u32 lockflag);
void Xil_ReleaseSpinLock(void);
u32 Xil_IsSpinLockEnabled(void);
/************************** MACRO Definitions ****************************/
#define XIL_SPINLOCK_LOCKVAL 0x10203040
#define XIL_SPINLOCK_RESETVAL 0x40302010
#define XIL_SPINLOCK_ENABLE 0x17273747
#define XIL_SPINLOCK_ENABLED 0x17273747
/***************** Macros (Inline Functions) Definitions ********************/
#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
/***************************************************************************/
#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
#define XIL_SPINLOCK() \
if(Xil_IsSpinLockEnabled()!=(u32)0) { \
Xil_SpinLock(); }
#else
#define XIL_SPINLOCK()
#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
#define XIL_SPINUNLOCK() \
if(Xil_IsSpinLockEnabled()!=(u32)0) { \
Xil_SpinUnlock(); }
#else
#define XIL_SPINUNLOCK()
#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_SPINLOCK_H */

765
Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/e04d6a565243001d18b399c1eb9b3628
View File

@ -1,765 +0,0 @@
/******************************************************************************/
/**
* Copyright (c) 2019 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
* @file xil_util.c
*
* This file contains xil utility functions
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.4 mmd 04/21/19 First release.
* 7.2 nava 08/01/20 Updated Xil_WaitForEvent() and Xil_WaitForEvents(()
* API to use microsecond timeout instead of a free
* counter.
* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API.
* rpo 08/19/20 Added function for read,modify,write
* kal 09/22/20 Changed the param type from const char to const char*
* to avoid copying key onto stack
* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
* Xil_MemCmp functions
* 7.4 am 11/26/20 Added Xil_StrCpyRange function
* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
*
* </pre>
*
*****************************************************************************/
/****************************** Include Files *********************************/
#include "xil_util.h"
#include "sleep.h"
/************************** Constant Definitions ****************************/
#define MAX_NIBBLES 8U
/************************** Function Prototypes *****************************/
/******************************************************************************/
/**
* This API ceils the provided float value.
*
* @param Value is a float variable which has to ceiled to nearest
* integer.
*
* @return Returns ceiled value.
*
*******************************************************************************/
int Xil_Ceil(float Value)
{
int Result = Value;
if (Value > Result) {
Result = Result + 1;
}
return Result;
}
/****************************************************************************/
/**
* Converts the char into the equivalent nibble.
* Ex: 'a' -> 0xa, 'A' -> 0xa, '9'->0x9
*
* @param InChar - Input character to be converted to nibble.
* Valid characters are between 0-9, a-f, A-F
* @param Num - Memory location where nibble is to be stored
*
* @return
* XST_SUCCESS - Character converted to nibble
* XST_FAILURE - Invalid input character
*
* @note None.
*
*****************************************************************************/
u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num)
{
u32 Status;
/* Convert the char to nibble */
if ((InChar >= (u8)'0') && (InChar <= (u8)'9')) {
*Num = InChar - (u8)'0';
Status = XST_SUCCESS;
}
else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) {
*Num = InChar - (u8)'a' + 10U;
Status = XST_SUCCESS;
}
else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) {
*Num = InChar - (u8)'A' + 10U;
Status = XST_SUCCESS;
}
else {
Status = XST_FAILURE;
}
return Status;
}
/****************************************************************************/
/*
* Converts the string into the equivalent Hex buffer.
* Ex: "abc123" -> {0xab, 0xc1, 0x23}
*
* @param Str - Pointer to string to be converted to Hex.
* Accepted characters in string are between 0-9, a-f and A-F
* @param Buf - Pointer to memory location where converted hex values are to
* be stored.
* @param Len - Length of input string
*
* @return
* XST_SUCCESS - Input string is converted to hex
* XST_FAILURE - Invalid character in inpit string
*
* @note None.
*
*****************************************************************************/
u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len)
{
u32 Status = XST_FAILURE;
u8 ConvertedLen = 0U, index = 0U;
u8 Nibble[MAX_NIBBLES] = {0U};
u8 i;
while (ConvertedLen < Len) {
for (i = 0U; i < MAX_NIBBLES; i++) {
Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
&Nibble[i]);
ConvertedLen = ConvertedLen +1U;
if (Status != XST_SUCCESS) {
/* Error converting char to nibble */
goto END;
}
}
buf[index] = ((Nibble[0] << (u8)28U) | (Nibble[1] << (u8)24U) |
(Nibble[2] << (u8)20U) | (Nibble[3] << (u8)16U) |
(Nibble[4] << (u8)12U) | (Nibble[5] << (u8)8U) |
(Nibble[6] << (u8)4U) | (u32)Nibble[7]);
index++;
}
END:
return Status;
}
/****************************************************************************/
/*
* Waits for the event
*
* @param RegAddr - Address of register to be checked for event(s) occurrence
* @param EventMask - Mask indicating event(s) to be checked
* @param Event - Specific event(s) value to be checked
* @param Timeout - Max number of microseconds to wait for an event(s).
*
* @return
* XST_SUCCESS - On occurrence of the event(s).
* XST_FAILURE - Event did not occur before counter reaches 0
*
* @note None.
*
*****************************************************************************/
u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout)
{
u32 EventStatus;
u32 PollCount = Timeout;
u32 Status = XST_FAILURE;
while(PollCount > 0) {
EventStatus = Xil_In32(RegAddr) & EventMask;
if (EventStatus == Event) {
Status = XST_SUCCESS;
break;
}
PollCount--;
usleep(1U);
}
return Status;
}
/******************************************************************************/
/**
* Waits for the events. Returns on occurrence of first event / timeout.
*
* @param EventsRegAddr - Address of register to be checked for event(s)
* occurrence
* @param EventsMask - Mask indicating event(s) to be checked
* @param WaitEvents - Specific event(s) to be checked
* @param Timeout - Max number of microseconds to wait for an event(s).
* @param Events - Mask of Events occurred returned in memory pointed by
* this variable
*
* @return
* XST_SUCCESS - On occurrence of the event(s).
* XST_FAILURE - Event did not occur before counter reaches 0
*
******************************************************************************/
u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
u32 Timeout, u32* Events)
{
u32 EventStatus;
u32 PollCount = Timeout;
u32 Status = XST_TIMEOUT;
*Events = 0x00;
do {
EventStatus = Xil_In32(EventsRegAddr);
EventStatus &= EventsMask;
if(EventStatus & WaitEvents) {
Status = XST_SUCCESS;
*Events = EventStatus;
break;
}
PollCount--;
usleep(1U);
}
while(PollCount > 0);
return Status;
}
/******************************************************************************/
/**
* Checks whether the passed character is a valid hex digit
*
* @param Ch - Pointer to the input character
*
* @return
* XST_SUCCESS - on valid hex digit
* XST_FAILURE - on invalid hex digit
*
* @note None.
*
******************************************************************************/
u32 Xil_IsValidHexChar(const char *Ch)
{
u32 Status = XST_FAILURE;
if(NULL == Ch) {
goto END;
}
if ((*Ch >= '0' && *Ch <='9')||
(*Ch >= 'a' && *Ch <='f')||
(*Ch >= 'A' && *Ch <='F')) {
Status = XST_SUCCESS;
}
END:
return Status;
}
/******************************************************************************/
/**
* Validate the input string contains only hexadecimal characters
*
* @param HexStr - Pointer to string to be validated
*
* @return
* XST_SUCCESS - On valid input hex string
* XST_INVALID_PARAM - On invalid length of the input string
* XST_FAILURE - On non hexadecimal character in string
*
* @note None
*
******************************************************************************/
u32 Xil_ValidateHexStr(const char *HexStr)
{
u32 Idx;
u32 Len;
u32 Status = XST_INVALID_PARAM;
if(NULL == HexStr) {
goto END;
}
Len = Xil_Strnlen(HexStr, XIL_MAX_HEX_STR_LEN + 1U);
if (Len > XIL_MAX_HEX_STR_LEN) {
goto END;
}
for (Idx = 0U; Idx < Len; Idx++) {
Status = Xil_IsValidHexChar(&HexStr[Idx]);
if (Status != XST_SUCCESS) {
break;
}
}
END:
return Status;
}
/****************************************************************************/
/**
* Converts the string into the equivalent Hex buffer.
* Ex: "abc123" -> {0xab, 0xc1, 0x23}
*
* @param Str is a Input String. Will support the lower and upper case values.
* Value should be between 0-9, a-f and A-F
* @param Buf is Output buffer.
* @param Len of the input string. Should have even values
*
* @return
* - XST_SUCCESS no errors occurred.
* - XST_FAILURE an error when input parameters are not valid
* - an error when input buffer has invalid values
*
* TDD Test Cases:
* ---Initialization---
* Len is odd
* Len is zero
* Str is NULL
* Buf is NULL
* ---Functionality---
* Str input with only numbers
* Str input with All values in A-F
* Str input with All values in a-f
* Str input with values in a-f, 0-9, A-F
* Str input with values in a-z, 0-9, A-Z
* Boundary Cases
* Memory Bounds of buffer checking
* ****************************************************************************/
u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len)
{
u32 ConvertedLen;
u8 LowerNibble = 0U;
u8 UpperNibble = 0U;
u32 Status = (u32)XST_FAILURE;
if ((Str == NULL) || (Buf == NULL)) {
Status = (u32)XST_INVALID_PARAM;
goto END;
}
if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) {
Status = (u32)XST_INVALID_PARAM;
goto END;
}
if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
Status = (u32)XST_INVALID_PARAM;
goto END;
}
ConvertedLen = 0U;
while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
if (Xil_ConvertCharToNibble(Str[ConvertedLen],&UpperNibble)
== (u32)XST_SUCCESS) {
if (Xil_ConvertCharToNibble(Str[ConvertedLen+1],
&LowerNibble) == (u32)XST_SUCCESS) {
Buf[ConvertedLen/2] =
(UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
LowerNibble;
}
else {
Status = (u32)XST_INVALID_PARAM;
goto END;
}
}
else {
Status = (u32)XST_INVALID_PARAM;
goto END;
}
ConvertedLen += 2U;
}
Status = (u32)XST_SUCCESS;
END:
return Status;
}
/******************************************************************************/
/**
* Converts the string into the equivalent Hex buffer.
* Ex: "abc123" -> {0x23, 0xc1, 0xab}
*
* @param Str - Input String to be converted to hex number in little
* endian format. Valid characters of input strin are between
* 0-9, a-f and A-F
* @param Buf - Pointer to memory location where converted hex numbers are to
* be stored.
* @param Len - Expected number of output bits
*
* @return
* XST_SUCCESS - Input string is converted to hex number(s)
* XST_FAILURE - Invalid input character detected in input string
*
* @note
*
******************************************************************************/
u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len)
{
u32 ConvertedLen;
u8 LowerNibble = 0U;
u8 UpperNibble = 0U;
u32 StrIndex;
u32 Status = XST_FAILURE;
if ((NULL == Str) || (NULL == Buf)) {
Status = XST_INVALID_PARAM;
goto END;
}
if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) {
Status = XST_INVALID_PARAM;
goto END;
}
if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
Status = XST_INVALID_PARAM;
goto END;
}
StrIndex = (Len / XIL_SIZE_OF_BYTE_IN_BITS) - 1U;
ConvertedLen = 0U;
while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
&UpperNibble);
if (XST_SUCCESS == Status) {
Status = Xil_ConvertCharToNibble(Str[ConvertedLen + 1],
&LowerNibble);
if (XST_SUCCESS == Status) {
Buf[StrIndex] =
(UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
LowerNibble;
StrIndex = StrIndex - 1U;
}
else {
Status = XST_INVALID_PARAM;
goto END;
}
}
else {
Status = XST_INVALID_PARAM;
goto END;
}
ConvertedLen += 2U;
}
Status = XST_SUCCESS;
END:
return Status;
}
/******************************************************************************/
/**
* Returns the length of input string.
*
* @param Str - Input string
* @param MaxLen - Maximum expected length of the input string
*
* @return
* Returns length of the input string if length is less than MaxLen.
* Returns MaxLen if the length of the input string is >= MaxLen.
*
* @note
*
******************************************************************************/
u32 Xil_Strnlen(const char *Str, u32 MaxLen)
{
const char *InStr = Str;
u32 StrLen = 0U;
if (NULL == Str) {
goto END;
}
while(StrLen < MaxLen) {
if ('\0' == *InStr) {
break;
}
StrLen++;
InStr++;
}
END:
return StrLen;
}
/*****************************************************************************/
/**
* @brief This function will Read, Modify and Write to an address.
*
* @param Addr denotes Address
* @param Mask denotes the bits to be modified
* @param Value is the value to be written to the address
*
* @return None
*
*****************************************************************************/
void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value)
{
u32 Val;
Val = Xil_In32(Addr);
Val = (Val & (~Mask)) | (Mask & Value);
Xil_Out32(Addr, Val);
}
/*****************************************************************************/
/**
* @brief This functions copies source string to destination string. This
* function is a safe version of strcpy
*
* @param DestPtr is pointer to destination string
* @param SrcPtr is pointer to source string
* @param Size is the maximum number of bytes of the source string
* to be copied
*
* @return XST_SUCCESS on success and error code on failure
*
******************************************************************************/
int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size)
{
int Status = XST_FAILURE;
u32 Count;
if ((SrcPtr == NULL) || (DestPtr == NULL) || (Size == 0U)) {
goto END;
}
for (Count = 0U; (SrcPtr[Count] != '\0') && (Count < Size); ++Count) {
DestPtr[Count] = SrcPtr[Count];
}
if (Count == Size) {
DestPtr[0U] = '\0';
goto END;
}
DestPtr[Count] = '\0';
Status = XST_SUCCESS;
END:
return Status;
}
/****************************************************************************/
/**
* @brief Copies specified range from source string to destination string
*
* @param Src is a pointer to source string
* @param Dst is a pointer to destination string
* @param From is 0 based index from where string copy starts
* @param To is 0 based index till which string is copied
* @param MaxSrcLen is the maximum length of source string
* @param MaxDstLen is the maximum length of destination string
*
* @return XST_SUCCESS on success
* XST_FAILURE on failure
*
* @note None
*
****************************************************************************/
int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
u32 MaxDstLen)
{
int Status = XST_FAILURE;
u32 SrcLength;
u32 Index;
if ((Src == NULL) || (Dst == NULL)) {
Status = XST_INVALID_PARAM;
goto END;
}
if ((To >= MaxSrcLen) || (To < From)) {
Status = XST_INVALID_PARAM;
goto END;
}
if ((To - From + 1U) >= MaxDstLen) {
Status = XST_INVALID_PARAM;
goto END;
}
SrcLength = Xil_Strnlen((const char *)Src, MaxSrcLen);
if (To >= SrcLength) {
Status = XST_INVALID_PARAM;
goto END;
}
for (Index = From; Index <= To && Src[Index]!= '\0'; Index++) {
Dst[Index - From] = Src[Index];
}
Dst[Index - From] = '\0';
Status = XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/**
* @brief This function appends string2 to string1. This function is a safe
* version of strcat
*
* @param Str1Ptr is pointer to string1
* @param Str2Ptr is pointer to string2
* @param Size is the maximum number of bytes Str1 can hold
*
* @return XST_SUCCESS on success and error code on failure
*
******************************************************************************/
int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size)
{
int Status = XST_FAILURE;
u32 Count = 0U;
u32 CountTmp = 0U;
if ((Str1Ptr == NULL) || (Str2Ptr == NULL) || (Size == 0U)) {
goto END;
}
while ((Count < Size) && (Str1Ptr[Count] != '\0')) {
Count++;
}
while ((Str2Ptr[CountTmp] != '\0') && (Count < Size)) {
Str1Ptr[Count++] = Str2Ptr[CountTmp++];
}
if (Count == Size) {
Str1Ptr[0U] = '\0';
goto END;
}
Str1Ptr[Count] = '\0';
Status = XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/**
* @brief This function copies Len bytes from source memory to destination
* memory. If Len is greater than DestPtrLen, then DestPtr is also
* filled with 0s till DestPtrLen bytes and is considered as a failure.
* This function is a secure implementation of memcpy
*
* @param DestPtr is pointer to destination address
* @param DestPtrLen is the memory alloted to the destination buffer
* @param SrcPtr is pointer to source address
* @param Len is number of bytes to be copied
*
* @return XST_SUCCESS on success and error code on failure
*
******************************************************************************/
int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len)
{
int Status = XST_FAILURE;
u8 *Dest = (u8 *)DestPtr;
const u8 *Src = (const u8 *)SrcPtr;
if ((DestPtr == NULL) || (SrcPtr == NULL)) {
goto END;
}
if (Len > DestPtrLen) {
while (DestPtrLen != 0U) {
*Dest = 0U;
Dest++;
DestPtrLen--;
}
goto END;
}
/* Loop and copy. */
while (Len != 0U) {
*Dest = *Src;
Dest++;
Src++;
Len--;
}
Status = XST_SUCCESS;
END:
return Status;
}
/*****************************************************************************/
/**
* @brief This function compares Len bytes from memory1 and memory2. This
* function is a secure implementation of memcmp
*
* @param Buf1Ptr is pointer to memory1
* @param Buf2Ptr is pointer to memory2
* @param Len is number of byets to be compared
*
* @return 0 if contents of both the memory regions are same,
* -1 if first non-matching character has lower value in Buf1Ptr
* 1 if first non-matching character is greater value in Buf1Ptr
*
******************************************************************************/
int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len)
{
volatile int RetVal = 1;
const u8 *Buf1 = Buf1Ptr;
const u8 *Buf2 = Buf2Ptr;
u32 Size = Len;
/* Assert validates the input arguments */
if ((Buf1 == NULL) || (Buf2 == NULL) || (Len == 0x0U)) {
goto END;
}
/* Loop and compare */
while (Size != 0U) {
if (*Buf1 > *Buf2) {
RetVal = 1;
goto END;
} else if (*Buf1 < *Buf2) {
RetVal = -1;
goto END;
} else {
Buf1++;
Buf2++;
Size--;
}
}
/* Make sure size is zero to know the whole of data is compared */
if (Size == 0U) {
RetVal = 0;
}
END:
return RetVal;
}
/*****************************************************************************/
/**
* @brief This function is used to zeroize the memory
*
* @param DataPtr Pointer to the memory which need to be zeroized.
* @param Length Length of the data in bytes.
*
* @return
* - XST_SUCCESS: If Zeroization is successful.
* - XST_FAILURE: If Zeroization is not successful.
********************************************************************************/
int Xil_SecureZeroize(u8 *DataPtr, const u32 Length)
{
u32 Index;
int Status = XST_FAILURE;
/* Clear the data */
(void)memset(DataPtr, 0, Length);
/* Read it back to verify */
for (Index = 0U; Index < Length; Index++) {
if (DataPtr[Index] != 0x00U) {
goto END;
}
}
if (Index == Length) {
Status = XST_SUCCESS;
}
END:
return Status;
}

39
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@ -1,39 +0,0 @@
DRIVER_LIB_VERSION = 1.0
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib/
INCLUDEDIR=../../../include/
INCLUDES=-I./. -I$(INCLUDEDIR)
SRCFILES:=$(wildcard *.c)
OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
libs: $(OBJECTS)
DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
include $(wildcard $(DEPFILES))
include $(wildcard ../../../../dep.mk)
$(RELEASEDIR)%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
.PHONY: include
include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
$(INCLUDEDIR)%.h: %.h
$(CP) $< $@
clean:
rm -rf ${OBJECTS}
rm -rf ${DEPFILES}

42
Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1c/e0868d595243001d18b399c1eb9b3628
View File

@ -1,42 +0,0 @@
/******************************************************************************
* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
.globl _mcount
.text
.align 2
.ent _mcount
#ifndef PROFILE_NO_GRAPH
_mcount:
addi r1, r1, -48
swi r11, r1, 44
swi r12, r1, 40
swi r5, r1, 36
swi r6, r1, 32
swi r7, r1, 28
swi r8, r1, 24
swi r9, r1, 20
swi r10, r1, 16
swi r15, r1, 12
add r5, r0, r15
brlid r15, mcount
add r6, r0, r16
lwi r11, r1, 44
lwi r12, r1, 40
lwi r5, r1, 36
lwi r6, r1, 32
lwi r7, r1, 28
lwi r8, r1, 24
lwi r9, r1, 20
lwi r10, r1, 16
lwi r15, r1, 12
rtsd r15, 4
addi r1, r1, 48
#endif /* PROFILE_NO_GRAPH */
.end _mcount

41
Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1c/f0f08b545243001d18b399c1eb9b3628
View File

@ -1,41 +0,0 @@
DRIVER_LIB_VERSION = 1.0
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
RELEASEDIR=../../../lib/
INCLUDEDIR=../../../include/
INCLUDES=-I./. -I$(INCLUDEDIR)
INCLUDEFILES:=*.h
SRCFILES:=$(wildcard *.c)
OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
libs: $(OBJECTS)
DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
include $(wildcard $(DEPFILES))
include $(wildcard ../../../../dep.mk)
$(RELEASEDIR)%.o: %.c
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
.PHONY: include
include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
$(INCLUDEDIR)%.h: %.h
$(CP) $< $@
clean:
rm -rf ${OBJECTS}
rm -rf $(DEPFILES)

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/******************************************************************************/
/**
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
* @file xil_mem.c
*
* This file contains xil mem copy function to use in case of word aligned
* data copies.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.1 nsk 11/07/16 First release.
*
* </pre>
*
*****************************************************************************/
/***************************** Include Files ********************************/
#include "xil_types.h"
/***************** Inline Functions Definitions ********************/
/*****************************************************************************/
/**
* @brief This function copies memory from once location to other.
*
* @param dst: pointer pointing to destination memory
*
* @param src: pointer pointing to source memory
*
* @param cnt: 32 bit length of bytes to be copied
*
*****************************************************************************/
void Xil_MemCpy(void* dst, const void* src, u32 cnt)
{
char *d = (char*)(void *)dst;
const char *s = src;
while (cnt >= sizeof (int)) {
*(int*)d = *(int*)s;
d += sizeof (int);
s += sizeof (int);
cnt -= sizeof (int);
}
while (cnt >= sizeof (u16)) {
*(u16*)d = *(u16*)s;
d += sizeof (u16);
s += sizeof (u16);
cnt -= sizeof (u16);
}
while ((cnt) > 0U){
*d = *s;
d += 1U;
s += 1U;
cnt -= 1U;
}
}

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/******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_io.h
*
* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
*
* The xil_io.h file contains the interface for the general I/O component, which
* encapsulates the Input/Output functions for the processors that do not
* require any special I/O handling.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
* ARM processors
* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
* CR-1049218
* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
* xil_io.h and made them as static inline
* am 10/13/20 Changed the return type of Xil_SecureOut32 function
* from u32 to int
* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
* when -Werror=conversion compiler flag is enabled
* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
*
* </pre>
******************************************************************************/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_printf.h"
#include "xstatus.h"
#if defined (__MICROBLAZE__)
#include "mb_interface.h"
#else
#include "xpseudo_asm.h"
#endif
/************************** Function Prototypes ******************************/
#ifdef ENABLE_SAFETY
extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
#endif
/***************** Macros (Inline Functions) Definitions *********************/
#if defined __GNUC__
#if defined (__MICROBLAZE__)
# define INST_SYNC mbar(0)
# define DATA_SYNC mbar(1)
# else
# define SYNCHRONIZE_IO dmb()
# define INST_SYNC isb()
# define DATA_SYNC dsb()
# endif
#else
# define SYNCHRONIZE_IO
# define INST_SYNC
# define DATA_SYNC
# define INST_SYNC
# define DATA_SYNC
#endif
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
#define INLINE inline
#else
#define INLINE __inline
#endif
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading
* from the specified address and returning the 8 bit Value read from
* that address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 8 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u8 Xil_In8(UINTPTR Addr)
{
return *(volatile u8 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading from
* the specified address and returning the 16 bit Value read from that
* address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 16 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u16 Xil_In16(UINTPTR Addr)
{
return *(volatile u16 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by
* reading from the specified address and returning the 32 bit Value
* read from that address.
*
* @param Addr: contains the address to perform the input operation
*
* @return The 32 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u32 Xil_In32(UINTPTR Addr)
{
return *(volatile u32 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading the
* 64 bit Value read from that address.
*
*
* @param Addr: contains the address to perform the input operation
*
* @return The 64 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u64 Xil_In64(UINTPTR Addr)
{
return *(volatile u64 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for an memory location by
* writing the 8 bit Value to the the specified address.
*
* @param Addr: contains the address to perform the output operation
* @param Value: contains the 8 bit Value to be written at the specified
* address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
{
/* write 8 bit value to specified address */
volatile u8 *LocalAddr = (volatile u8 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 16 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains the Value to be written at the specified address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
{
/* write 16 bit value to specified address */
volatile u16 *LocalAddr = (volatile u16 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 32 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains the 32 bit Value to be written at the specified
* address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
{
/* write 32 bit value to specified address */
#ifndef ENABLE_SAFETY
volatile u32 *LocalAddr = (volatile u32 *)Addr;
*LocalAddr = Value;
#else
XStl_RegUpdate(Addr, Value);
#endif
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 64 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains 64 bit Value to be written at the specified address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
{
/* write 64 bit value to specified address */
volatile u64 *LocalAddr = (volatile u64 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 32 bit Value to the the specified address and then reading it
* back to verify the value written in the register.
*
* @param Addr contains the address to perform the output operation
* @param Value contains 32 bit Value to be written at the specified address
*
* @return Returns Status
* - XST_SUCCESS on success
* - XST_FAILURE on failure
*
*****************************************************************************/
static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
{
int Status = XST_FAILURE;
u32 ReadReg;
u32 ReadRegTemp;
/* writing 32 bit value to specified address */
Xil_Out32(Addr, Value);
/* verify value written to specified address with multiple reads */
ReadReg = Xil_In32(Addr);
ReadRegTemp = Xil_In32(Addr);
if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
Status = XST_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/**
*
* @brief Perform a 16-bit endian conversion.
*
* @param Data: 16 bit value to be converted
*
* @return 16 bit Data with converted endianness
*
******************************************************************************/
static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
{
return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
}
/*****************************************************************************/
/**
*
* @brief Perform a 32-bit endian conversion.
*
* @param Data: 32 bit value to be converted
*
* @return 32 bit data with converted endianness
*
******************************************************************************/
static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
{
u16 LoWord;
u16 HiWord;
/* get each of the half words from the 32 bit word */
LoWord = (u16) (Data & 0x0000FFFFU);
HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
/* byte swap each of the 16 bit half words */
LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
/* swap the half words before returning the value */
return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
# else
# define Xil_In16BE Xil_In16
# define Xil_In32BE Xil_In32
# define Xil_Out16BE Xil_Out16
# define Xil_Out32BE Xil_Out32
# define Xil_Htons(Data) (Data)
# define Xil_Htonl(Data) (Data)
# define Xil_Ntohs(Data) (Data)
# define Xil_Ntohl(Data) (Data)
#endif
#else
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
#endif
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u16 Xil_In16BE(UINTPTR Addr)
#else
static INLINE u16 Xil_In16LE(UINTPTR Addr)
#endif
#else
static INLINE u16 Xil_In16BE(UINTPTR Addr)
#endif
{
u16 value = Xil_In16(Addr);
return Xil_EndianSwap16(value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#else
static INLINE u32 Xil_In32LE(UINTPTR Addr)
#endif
#else
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#endif
{
u32 value = Xil_In32(Addr);
return Xil_EndianSwap32(value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#else
static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
#endif
#else
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#endif
{
Value = Xil_EndianSwap16(Value);
Xil_Out16(Addr, Value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#else
static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
#endif
#else
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#endif
{
Value = Xil_EndianSwap32(Value);
Xil_Out32(Addr, Value);
}
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_io_interfacing_apis".
*/

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/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*
*
* This is a template implementation of the "__lseek" function used by
* the standard library. Replace it with a system-specific
* implementation.
*
* The "__lseek" function makes the next file operation (__read or
* __write) act on a new location. The parameter "whence" specifies
* how the "offset" parameter should be interpreted according to the
* following table:
*
* 0 (=SEEK_SET) - Goto location "offset".
* 1 (=SEEK_CUR) - Go "offset" bytes from the current location.
* 2 (=SEEK_END) - Go to "offset" bytes from the end.
*
* This function should return the current file position, or -1 on
* failure.
*/
#include <stdio.h>
#include <yfuns.h>
#include "xil_types.h"
LONG __lseek(sint32 handle, LONG offset, sint32 whence);
LONG __lseek(sint32 handle, LONG offset, sint32 whence)
{
return (-1);
}

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/******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xplatform_info.c
* @addtogroup common_platform_info Hardware Platform Information
* @{
* This file contains information about hardware for which the code is built
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 5.00 pkp 12/15/14 Initial release
* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
* mode
* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
* function for PMUFW.
* ms 06/13/17 Added PSU_PMU macro to provide support of
* XGetPlatform_Info function for PMUFW.
* mus 08/17/17 Add EL1 NS mode support for
* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
* APIs.
* 7.0 aru 03/15/19 Check for versal before aarch64 and armr5
* in XGetPlatform_Info()
* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
* arguments with void keyword. This has been done to fix
* compilation warnings with "-Wstrict-prototypes" flag.
* It fixes CR#1108601.
* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
* reported with "-Wundef" flag. It fixes CR#1108601.
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_io.h"
#include "xplatform_info.h"
#if defined (__aarch64__)
#include "bspconfig.h"
#include "xil_smc.h"
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* @brief This API is used to provide information about platform
*
* @return The information about platform defined in xplatform_info.h
*
******************************************************************************/
u32 XGetPlatform_Info(void)
{
#if defined (versal)
return XPLAT_VERSAL;
#elif defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU)
return XPLAT_ZYNQ_ULTRA_MP;
#elif defined (__microblaze__)
return XPLAT_MICROBLAZE;
#else
return XPLAT_ZYNQ;
#endif
}
/*****************************************************************************/
/**
*
* @brief This API is used to provide information about zynq ultrascale MP platform
*
* @return The information about zynq ultrascale MP platform defined in
* xplatform_info.h
*
******************************************************************************/
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
u32 XGet_Zynq_UltraMp_Platform_info(void)
{
#if EL1_NONSECURE
XSmc_OutVar reg;
/*
* This SMC call will return,
* idcode - upper 32 bits of reg.Arg0
* version - lower 32 bits of reg.Arg1
*/
reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
#else
u32 reg;
reg = ((Xil_In32(XPLAT_PS_VERSION_ADDRESS) >> XPLAT_INFO_SHIFT )
& XPLAT_INFO_MASK);
return reg;
#endif
}
#endif
/*****************************************************************************/
/**
*
* @brief This API is used to provide information about PS Silicon version
*
* @return The information about PS Silicon version.
*
******************************************************************************/
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal)
u32 XGetPSVersion_Info(void)
{
#if EL1_NONSECURE
/*
* This SMC call will return,
* idcode - upper 32 bits of reg.Arg0
* version - lower 32 bits of reg.Arg1
*/
XSmc_OutVar reg;
reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >>
XPS_VERSION_INFO_SHIFT);
#else
u32 reg;
reg = (Xil_In32(XPLAT_PS_VERSION_ADDRESS)
& XPS_VERSION_INFO_MASK);
return (reg >> XPS_VERSION_INFO_SHIFT);
#endif
}
#endif
/** @} */

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/******************************************************************************
* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv.h
*
* Defines common services that are typically found in a host operating.
* environment. This include file simply includes an OS specific file based
* on the compile-time constant BUILD_ENV_*, where * is the name of the target
* environment.
*
* All services are defined as macros.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b ch 10/24/02 Added XENV_LINUX
* 1.00a rmm 04/17/02 First release
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XENV_H /* prevent circular inclusions */
#define XENV_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/*
* Select which target environment we are operating under
*/
/* VxWorks target environment */
#if defined XENV_VXWORKS
#include "xenv_vxworks.h"
/* Linux target environment */
#elif defined XENV_LINUX
#include "xenv_linux.h"
/* Unit test environment */
#elif defined XENV_UNITTEST
#include "ut_xenv.h"
/* Integration test environment */
#elif defined XENV_INTTEST
#include "int_xenv.h"
/* Standalone environment selected */
#else
#include "xenv_standalone.h"
#endif
/*
* The following comments specify the types and macro wrappers that are
* expected to be defined by the target specific header files
*/
/**************************** Type Definitions *******************************/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP
*
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
* Samples the processor's or external timer's time base counter.
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of microseconds.
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of milliseconds.
*/
/*****************************************************************************//**
*
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None
*/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
*@endcond
*/

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/******************************************************************************
* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef UNDEFINE_FILE_OPS
#include <errno.h>
#include "xil_types.h"
#include <time.h>
struct tms* tms;
#ifdef __cplusplus
extern "C" {
__attribute__((weak)) clock_t _times(struct tms* tms);
}
#endif
__attribute__((weak)) clock_t _times(struct tms* tms)
{
(void)tms;
errno = EIO;
return (-1);
}
#endif

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/******************************************************************************
* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file translation_table.s
*
* @addtogroup a53_32_boot_code
* @{
* <h2> translation_table.S </h2>
* The translation_table.S contains a static page table required by MMU for
* cortex-A53. This translation table is flat mapped (input address = output
* address) with default memory attributes defined for zynq ultrascale+
* architecture. It utilizes short descriptor translation table format with each
* section defining 1MB of memory.
*
* For DDR in region 0x00000000 - 0x7FFFFFFF, a system where DDR is less than
* 2GB, region after DDR and before PL is marked as undefined/reserved in
* translation table. In region 0xFFC00000 - 0xFFDFFFFF, it contains CSU
* and PMU memory which are marked as Device since it is less than 1MB and
* falls in a region with device memory.
*
* The overview of translation table memory attributes is described below.
*
*| | Memory Range | Definition in Translation Table |
*|-----------------|-------------------------|---------------------------------|
*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable |
*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered |
*| QSPI, lower PCIe| 0xC0000000 - 0xEFFFFFFF | Device Memory |
*| Reserved | 0xF0000000 - 0xF7FFFFFF | Unassigned |
*| STM Coresight | 0xF8000000 - 0xF8FFFFFF | Device Memory |
*| GIC | 0xF9000000 - 0xF90FFFFF | Device memory |
*| Reserved | 0xF9100000 - 0xFCFFFFFF | Unassigned |
*| FPS, LPS slaves | 0xFD000000 - 0xFFBFFFFF | Device memory |
*| CSU, PMU | 0xFFC00000 - 0xFFDFFFFF | Device Memory |
*| TCM, OCM | 0xFFE00000 - 0xFFFFFFFF | Normal write-back cacheable |
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 5.2 pkp 28/05/15 First release
* 5.4 pkp 18/12/15 Updated the address map according to proper address map
* 6.0 mus 20/07/16 Added warning for ddrless HW design CR-954977
* </pre>
*
*
******************************************************************************/
#include "xparameters.h"
.globl MMUTable
.section .mmu_tbl,"a"
MMUTable:
/* Each table entry occupies one 32-bit word and there are
* 4096 entries, so the entire table takes up 16KB.
* Each entry covers a 1MB section.
*/
.set SECT, 0
#ifdef XPAR_PSU_DDR_0_S_AXI_BASEADDR
.set DDR_START, XPAR_PSU_DDR_0_S_AXI_BASEADDR
.set DDR_END, XPAR_PSU_DDR_0_S_AXI_HIGHADDR
.set DDR_SIZE, (DDR_END - DDR_START)+1
.if DDR_SIZE > 0x80000000
/* If DDR size is larger than 2GB, truncate to 2GB */
.set DDR_REG, 0x800
.else
.set DDR_REG, DDR_SIZE/0x100000
.endif
#else
.set DDR_REG, 0
#warning "There's no DDR in the HW design. MMU translation table marks 2 GB DDR address space as undefined"
#endif
.set UNDEF_REG, 0x800 - DDR_REG
.rept DDR_REG /* DDR Cacheable */
.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept UNDEF_REG /* unassigned/reserved */
/* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x0200 /* 0x80000000 - 0x9fffffff (FPGA slave0) */
.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0200 /* 0xA0000000 - 0xbfffffff (FPGA slave1) */
.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0200 /* 0xc0000000 - 0xdfffffff (OSPI IOU)*/
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x0100 /* 0xe0000000 - 0xefffffff (Lower PCIe)*/
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x80 /* 0xf0000000 - 0xf7ffffff (unassigned/reserved).
* Generates a translation fault if accessed */
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x10 /* 0xf8000000 - 0xf8ffffff (STM Coresight) */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x1 /* 0xf9000000 - 0xf90fffff (RPU_A53_GIC) */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x3f /* 0xf9100000 - 0xfcffffff (reserved).*/
.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
.set SECT, SECT+0x100000
.endr
.rept 0x10 /* 0xfd000000 - 0xfdffffff (FPS Slaves) */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x1C /* 0xfe0000000 - 0xfeffffff (LPS Slaves) */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x2 /* 0xffc000000 - 0xffdfffff (CSU and PMU) */
.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.rept 0x02 /* 0xffe00000 - 0xffffffff (TCM and OCM Cacheable) */
.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
.set SECT, SECT+0x100000
.endr
.end
/**
* @} End of "addtogroup a53_32_boot_code".
*/

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# Usage with Vitis IDE:
# In Vitis IDE create a Single Application Debug launch configuration,
# change the debug type to 'Attach to running target' and provide this
# tcl script in 'Execute Script' option.
# Path of this script: /home/dylan/workspace/phased_array_system/_ide/scripts/systemdebugger_phased_array_system_standalone.tcl
#
#
# Usage with xsct:
# To debug using xsct, launch xsct and run below command
# source /home/dylan/workspace/phased_array_system/_ide/scripts/systemdebugger_phased_array_system_standalone.tcl
#
connect -url tcp:127.0.0.1:3121
targets -set -nocase -filter {name =~"APU*"}
rst -system
after 3000
targets -set -filter {jtag_cable_name =~ "Digilent Zybo Z7 210351B104CCA" && level==0 && jtag_device_ctx=="jsn-Zybo Z7-210351B104CCA-23727093-0"}
fpga -file /home/dylan/workspace/phased_array/_ide/bitstream/design_1_wrapper.bit
targets -set -nocase -filter {name =~"APU*"}
loadhw -hw /home/dylan/workspace/phased_array_platform/export/phased_array_platform/hw/design_1_wrapper.xsa -mem-ranges [list {0x40000000 0xbfffffff}] -regs
configparams force-mem-access 1
targets -set -nocase -filter {name =~"APU*"}
source /home/dylan/workspace/phased_array/_ide/psinit/ps7_init.tcl
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "*A9*#0"}
dow /home/dylan/workspace/phased_array/Debug/phased_array.elf
configparams force-mem-access 0
targets -set -nocase -filter {name =~ "*A9*#0"}
con

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/******************************************************************************
* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xparameters_ps.h
*
* This file contains the address definitions for the hard peripherals
* attached to the ARM Cortex A72 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 7.00 mus 01/11/18 First release
* mn 03/26/18 Change Interrupt IDs for versal
* mn 03/26/18 Update SLCR base address
* ap 02/14/19 Add Interrupt Id for usbpsu controller
* sne 03/26/20 Add Interrupt Id's for WWDT.
* 7.2 pm 03/24/20 Add wakeup Interrupt Id for usbpsu controller
*
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _XPARAMETERS_PS_H_
#define _XPARAMETERS_PS_H_
/**
*@cond nocomments
*/
#ifdef __cplusplus
extern "C" {
#endif
#include "bspconfig.h"
/************************** Constant Definitions *****************************/
/*
* This block contains constant declarations for the peripherals
* within the hardblock
*/
/* Canonical definitions for DDR MEMORY */
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
/* Canonical definitions for Interrupts */
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
#define XPAR_XGWDT_0_INTR XPS_LPD_GWDT_0_INT_ID
#define XPAR_XGWDT_0_RST_INTR XPS_LPD_GWDT_0_RST_INT_ID
#define XPAR_XWWDT_0_INTR XPS_LPD_WWDT_0_INT_ID
#define XPAR_XWWDT_0_RST_PEND_INTR XPS_LPD_WWDT_0_RST_PEND_INT_ID
#define XPAR_XGWDT_1_INTR XPS_FPD_GWDT_1_INT_ID
#define XPAR_XGWDT_1_RST_INTR XPS_FPD_GWDT_1_RST_INT_ID
#define XPAR_XWWDT_1_INTR XPS_FPD_WWDT_1_INT_ID
#define XPAR_XWWDT_1_RST_PEND_INTR XPS_FPD_WWDT_1_RST_PEND_INT_ID
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID
#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID
#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID
#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID
#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID
#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID
#define XPAR_PSV_ADMA_0_INTR XPS_ADMA_CH0_INT_ID
#define XPAR_PSV_ADMA_1_INTR XPS_ADMA_CH1_INT_ID
#define XPAR_PSV_ADMA_2_INTR XPS_ADMA_CH2_INT_ID
#define XPAR_PSV_ADMA_3_INTR XPS_ADMA_CH3_INT_ID
#define XPAR_PSV_ADMA_4_INTR XPS_ADMA_CH4_INT_ID
#define XPAR_PSV_ADMA_5_INTR XPS_ADMA_CH5_INT_ID
#define XPAR_PSV_ADMA_6_INTR XPS_ADMA_CH6_INT_ID
#define XPAR_PSV_ADMA_7_INTR XPS_ADMA_CH7_INT_ID
#define XPAR_PSV_PMC_GPIO_INTR XPMC_GPIO_INT_ID
#define XPAR_PSV_PMC_I2C_INTR XPMC_I2C_INT_ID
#define XPAR_PSV_PMC_DMA_0_INTR XPS_PMCDMA0_INT_ID
#define XPAR_PSV_PMC_DMA_1_INTR XPS_PMCDMA1_INT_ID
#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID
#define XPAR_PSV_GDMA_1_INTR XPS_ZDMA_CH1_INT_ID
#define XPAR_PSV_GDMA_2_INTR XPS_ZDMA_CH2_INT_ID
#define XPAR_PSV_GDMA_3_INTR XPS_ZDMA_CH3_INT_ID
#define XPAR_PSV_GDMA_4_INTR XPS_ZDMA_CH4_INT_ID
#define XPAR_PSV_GDMA_5_INTR XPS_ZDMA_CH5_INT_ID
#define XPAR_PSV_GDMA_6_INTR XPS_ZDMA_CH6_INT_ID
#define XPAR_PSV_GDMA_7_INTR XPS_ZDMA_CH7_INT_ID
#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID
#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID
#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID
#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID
#define XPAR_XUSBPS_0_WAKE_INTR XPS_USB3_0_WAKE_INT_ID
#define XPAR_XRTCPSU_ALARM_INTR XPS_RTC_ALARM_INT_ID
#define XPAR_XRTCPSU_SECONDS_INTR XPS_RTC_SEC_INT_ID
#define XPAR_XSYSMONPSU_INTR XPS_AMS_INT_ID
/* Canonical definitions for SCU GIC */
#define XPAR_SCUGIC_NUM_INSTANCES 1U
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
#define XPAR_CPU_CORTEXA72_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA72_0_CPU_CLK_FREQ_HZ
/*
* This block contains constant declarations for the peripherals
* within the hardblock. These have been put for backwards compatibility
*/
#define XPS_SYS_CTRL_BASEADDR 0xF1060000U
#define XPS_SCU_PERIPH_BASE 0xF9000000U
#define XPS_CRP_BASEADDRESS 0xF1260000U
#define XPS_PMC_GLOBAL_BASEADDRESS 0xF1110000U
/* Shared Peripheral Interrupts (SPI) */
#define XPS_FPGA0_INT_ID 121U
#define XPS_FPGA1_INT_ID 122U
#define XPS_FPGA2_INT_ID 123U
#define XPS_FPGA3_INT_ID 124U
#define XPS_FPGA4_INT_ID 125U
#define XPS_FPGA5_INT_ID 126U
#define XPS_FPGA6_INT_ID 127U
#define XPS_FPGA7_INT_ID 128U
#define XPS_FPGA8_INT_ID 136U
#define XPS_FPGA9_INT_ID 137U
#define XPS_FPGA10_INT_ID 138U
#define XPS_FPGA11_INT_ID 139U
#define XPS_FPGA12_INT_ID 140U
#define XPS_FPGA13_INT_ID 141U
#define XPS_FPGA14_INT_ID 142U
#define XPS_FPGA15_INT_ID 143U
/* Updated Interrupt-IDs */
#define XPS_OCMINTR_INT_ID (10U + 32U)
#define XPS_OSPI_INT_ID (124U + 32U)
#define XPS_QSPI_INT_ID (125U + 32U)
#define XPS_GPIO_INT_ID (13U + 32U)
#define XPS_I2C0_INT_ID (14U + 32U)
#define XPS_I2C1_INT_ID (15U + 32U)
#define XPS_SPI0_INT_ID (16U + 32U)
#define XPS_SPI1_INT_ID (17U + 32U)
#define XPS_UART0_INT_ID (18U + 32U)
#define XPS_UART1_INT_ID (19U + 32U)
#define XPS_CAN0_INT_ID (20U + 32U)
#define XPS_CAN1_INT_ID (21U + 32U)
#define XPS_USB3_0_ENDPT_INT_ID (22U + 32U)
#define XPS_LPD_GWDT_0_INT_ID (70U + 32U)
#define XPS_LPD_GWDT_0_RST_INT_ID (71U + 32U)
#define XPS_LPD_WWDT_0_INT_ID (49U + 32U)
#define XPS_LPD_WWDT_0_RST_PEND_INT_ID (69U + 32U)
#define XPS_FPD_GWDT_1_INT_ID (108U + 32U)
#define XPS_FPD_GWDT_1_RST_INT_ID (110U + 32U)
#define XPS_FPD_WWDT_1_INT_ID (100U + 32U)
#define XPS_FPD_WWDT_1_RST_PEND_INT_ID (109U + 32U)
#define XPS_RTC_ALARM_INT_ID (142U + 32U)
#define XPS_RTC_SEC_INT_ID (143U + 32U)
#define XPS_TTC0_0_INT_ID (37U + 32U)
#define XPS_TTC0_1_INT_ID (38U + 32U)
#define XPS_TTC0_2_INT_ID (39U + 32U)
#define XPS_TTC1_0_INT_ID (40U + 32U)
#define XPS_TTC1_1_INT_ID (41U + 32U)
#define XPS_TTC1_2_INT_ID (42U + 32U)
#define XPS_TTC2_0_INT_ID (43U + 32U)
#define XPS_TTC2_1_INT_ID (44U + 32U)
#define XPS_TTC2_2_INT_ID (45U + 32U)
#define XPS_TTC3_0_INT_ID (46U + 32U)
#define XPS_TTC3_1_INT_ID (47U + 32U)
#define XPS_TTC3_2_INT_ID (48U + 32U)
#define XPS_SDIO0_INT_ID (126U + 32U)
#define XPS_SDIO0_WAKE_INT_ID (127U + 32U)
#define XPS_SDIO1_INT_ID (128U + 32U)
#define XPS_SDIO1_WAKE_INT_ID (129U + 32U)
#define XPS_AMS_INT_ID (53U + 32U)
#define XPS_GEM0_INT_ID (56U + 32U)
#define XPS_GEM0_WAKE_INT_ID (57U + 32U)
#define XPS_GEM1_INT_ID (58U + 32U)
#define XPS_GEM1_WAKE_INT_ID (59U + 32U)
#define XPS_ADMA_CH0_INT_ID (60U + 32U)
#define XPS_ADMA_CH1_INT_ID (61U + 32U)
#define XPS_ADMA_CH2_INT_ID (62U + 32U)
#define XPS_ADMA_CH3_INT_ID (63U + 32U)
#define XPS_ADMA_CH4_INT_ID (64U + 32U)
#define XPS_ADMA_CH5_INT_ID (65U + 32U)
#define XPS_ADMA_CH6_INT_ID (66U + 32U)
#define XPS_ADMA_CH7_INT_ID (67U + 32U)
#define XPS_XMPU_LPD_INT_ID (68U + 32U)
#define XPS_USB3_0_WAKE_INT_ID (74U + 32U)
#define XPS_XMPU_FPD_INT_ID (102U + 32U)
#define XPS_FPD_CCI_INT_ID (106U + 32U)
#define XPS_FPD_SMMU_INT_ID (107U + 32U)
#define XPMC_GPIO_INT_ID (122U + 32U)
#define XPMC_I2C_INT_ID (123U + 32U)
#define XPS_PMCDMA0_INT_ID (131U + 32U)
#define XPS_PMCDMA1_INT_ID (132U + 32U)
/* REDEFINES for TEST APP */
#define XPAR_PSV_SBSAUART_0_INTR XPS_UART0_INT_ID
#define XPAR_PSV_SBSAUART_1_INTR XPS_UART1_INT_ID
#define XPAR_PSV_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PSV_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PSV_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PSV_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PSV_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PSV_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PSV_CANFD_0_INTR XPS_CAN0_INT_ID
#define XPAR_PSV_CANFD_1_INTR XPS_CAN1_INT_ID
#define XPAR_PSV_GWDT_0_INTR XPS_LPD_GWDT_0_INT_ID
#define XPAR_PSV_GWDT_0_RST_INTR XPS_LPD_GWDT_0_RST_INT_ID
#define XPAR_PSV_WWDT_0_INTR XPS_LPD_WWDT_0_INT_ID
#define XPAR_PSV_WWDT_0_RST_PEND_INTR XPS_LPD_WWDT_0_RST_PEND_INT_ID
#define XPAR_PSV_GWDT_1_INTR XPS_FPD_GWDT_1_INT_ID
#define XPAR_PSV_GWDT_1_RST_INTR XPS_FPD_GWDT_1_RST_INT_ID
#define XPAR_PSV_WWDT_1_INTR XPS_FPD_WWDT_1_INT_ID
#define XPAR_PSV_WWDT_1_RST_PEND_INTR XPS_FPD_WWDT_1_RST_PEND_INT_ID
#define XPAR_PSV_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PSV_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PSV_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PSV_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PSV_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PSV_ETHERNET_2_INTR XPS_GEM2_INT_ID
#define XPAR_PSV_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
#define XPAR_PSV_ETHERNET_3_INTR XPS_GEM3_INT_ID
#define XPAR_PSV_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
#define XPAR_PSV_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PSV_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PSV_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PSV_TTC_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_PSV_TTC_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_PSV_TTC_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_PSV_TTC_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_PSV_TTC_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_PSV_TTC_6_INTR XPS_TTC2_0_INT_ID
#define XPAR_PSV_TTC_7_INTR XPS_TTC2_1_INT_ID
#define XPAR_PSV_TTC_8_INTR XPS_TTC2_2_INT_ID
#define XPAR_PSV_TTC_9_INTR XPS_TTC3_0_INT_ID
#define XPAR_PSV_TTC_10_INTR XPS_TTC3_1_INT_ID
#define XPAR_PSV_TTC_11_INTR XPS_TTC3_2_INT_ID
#define XPAR_PSV_AMS_INTR XPS_AMS_INT_ID
#define XPAR_XADCPS_NUM_INSTANCES 1U
#define XPAR_XADCPS_0_DEVICE_ID 0U
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
/* For backwards compatibility */
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
#ifdef XPAR_CPU_CORTEXA72_0_CPU_CLK_FREQ_HZ
#define XPAR_CPU_CORTEXA72_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA72_0_CPU_CLK_FREQ_HZ
#endif
#ifdef XPAR_CPU_CORTEXA72_1_CPU_CLK_FREQ_HZ
#define XPAR_CPU_CORTEXA72_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA72_1_CPU_CLK_FREQ_HZ
#endif
#ifdef __cplusplus
}
#endif
/**
*@endcond
*/
#endif /* protection macro */

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/*
* xen_events.h
*
* Created on: Sep 14, 2016
* Author: jarvis
*/
/*
Copyright DornerWorks 2016
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
following disclaimer.
THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _XEN_EVENTS_H_
#define _XEN_EVENTS_H_
#include "xil_types.h"
#define PAGE_SHIFT 12 // not really a good place for this
#define PAGE_SIZE (1<<PAGE_SHIFT)
#define EVENT_IRQ 31
#define XENMAPSPACE_shared_info 0 /* shared info page */
/* ` enum event_channel_op { // EVTCHNOP_* => struct evtchn_* */
#define EVTCHNOP_bind_interdomain 0
#define EVTCHNOP_bind_virq 1
#define EVTCHNOP_bind_pirq 2
#define EVTCHNOP_close 3
#define EVTCHNOP_send 4
#define EVTCHNOP_status 5
#define EVTCHNOP_alloc_unbound 6
#define EVTCHNOP_bind_ipi 7
#define EVTCHNOP_bind_vcpu 8
#define EVTCHNOP_unmask 9
#define EVTCHNOP_reset 10
#define EVTCHNOP_init_control 11
#define EVTCHNOP_expand_array 12
#define EVTCHNOP_set_priority 13
void notify_evtch(u32 evtch_id);
void init_events(void);
int register_event_handler(u32 evtch_id, void (*fptr)(void));
void unmask_evtchn(u32 port);
void handle_event_irq(void* data);
#endif /* _XEN_EVENTS_H_ */

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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/******************************************************************************/
/**
* @file xusbps.c
* @addtogroup usbps_v2_7
* @{
*
* The XUsbPs driver. Functions in this file are the minimum required
* functions for this driver. See xusbps.h for a detailed description of the
* driver.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- --------------------------------------------------------
* 1.00a jz 10/10/10 First release
* 2.1 kpc 04/28/14 Removed unused functions
* 2.5 pm 02/20/20 Added usb state interface.
* </pre>
******************************************************************************/
/***************************** Include Files **********************************/
#include <stdio.h>
#include "xusbps.h"
/************************** Constant Definitions ******************************/
/**************************** Type Definitions ********************************/
/***************** Macros (Inline Functions) Definitions **********************/
/************************** Variable Definitions ******************************/
/************************** Function Prototypes *******************************/
/*****************************************************************************/
/**
*
* This function initializes a XUsbPs instance/driver.
*
* The initialization entails:
* - Initialize all members of the XUsbPs structure.
*
* @param InstancePtr is a pointer to XUsbPs instance of the controller.
* @param ConfigPtr is a pointer to a XUsbPs_Config configuration
* structure. This structure will contain the requested
* configuration for the device. Typically, this is a local
* structure and the content of which will be copied into the
* configuration structure within XUsbPs.
* @param VirtBaseAddress is the base address of the device. For systems
* with virtual memory, this address must be the virtual address
* of the device.
* For systems that do not support virtual memory this address
* should be the physical address of the device. For backwards
* compatibility NULL may be passed in systems that do not support
* virtual memory (deprecated).
*
* @return
* - XST_SUCCESS no errors occurred.
* - XST_FAILURE an error occurred during initialization.
*
* @note
* After calling XUsbPs_CfgInitialize() the controller
* IS NOT READY for use. Before the controller can be used its
* DEVICE parameters must be configured. See xusbps.h
* for details.
*
******************************************************************************/
int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
/* Copy the config structure. */
InstancePtr->Config = *ConfigPtr;
/* Check if the user provided a non-NULL base address. If so, we have
* to overwrite the base address in the configuration structure.
*/
if (0 != VirtBaseAddress) {
InstancePtr->Config.BaseAddress = VirtBaseAddress;
}
/* Initialize the XUsbPs structure to default values. */
InstancePtr->CurrentAltSetting = XUSBPS_DEFAULT_ALT_SETTING;
InstancePtr->HandlerFunc = NULL;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function performs device reset, device is stopped at the end.
*
* @param InstancePtr is a pointer to XUsbPs instance of the controller.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XUsbPs_DeviceReset(XUsbPs *InstancePtr)
{
int Timeout;
/* Clear all setup token semaphores by reading the
* XUSBPS_EPSTAT_OFFSET register and writing its value back to
* itself.
*/
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPSTAT_OFFSET));
/* Clear all the endpoint complete status bits by reading the
* XUSBPS_EPCOMPL_OFFSET register and writings its value back
* to itself.
*/
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET,
XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPCOMPL_OFFSET));
/* Cancel all endpoint prime status by waiting until all bits
* in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
* to XUSBPS_EPFLUSH_OFFSET.
*
* Avoid hanging here by using a Timeout counter...
*/
Timeout = XUSBPS_TIMEOUT_COUNTER;
while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPPRIME_OFFSET) &
XUSBPS_EP_ALL_MASK) && --Timeout) {
/* NOP */
}
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
XUsbPs_Stop(InstancePtr);
/* Write to CR register for controller reset */
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK);
/* Wait for reset to finish, hardware clears the reset bit once done */
Timeout = 1000000;
while((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_CMD_OFFSET) &
XUSBPS_CMD_RST_MASK) && --Timeout) {
/* NOP */
}
}
/*****************************************************************************/
/**
*
* This function resets the USB device. All the configuration registers are
* reset to their default values. The function waits until the reset operation
* is complete or for a certain duration within which the reset operation is
* expected to be completed.
*
* @param InstancePtr is a pointer to XUsbPs instance of the controller.
*
* @return
* - XST_SUCCESS Reset operation completed successfully.
* - XST_FAILURE Reset operation timed out.
*
* @note None.
*
******************************************************************************/
int XUsbPs_Reset(XUsbPs *InstancePtr)
{
int Timeout;
Xil_AssertNonvoid(InstancePtr != NULL);
/* Write a 1 to the RESET bit. The RESET bit is cleared by HW once the
* RESET is complete.
*
* We are going to wait for the RESET bit to clear before we return
* from this function. Unfortunately we do not have timers available at
* this point to determine when we should report a Timeout.
*
* However, by using a large number for the poll loop we can assume
* that the polling operation will take longer than the expected time
* the HW needs to RESET. If the poll loop expires we can assume a
* Timeout. The drawback is that on a slow system (and even on a fast
* system) this can lead to _very_ long Timeout periods.
*/
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK);
/* Wait for the RESET bit to be cleared by HW. */
Timeout = XUSBPS_TIMEOUT_COUNTER;
while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
XUSBPS_CMD_OFFSET) &
XUSBPS_CMD_RST_MASK) && --Timeout) {
/* NOP */
}
if (0 == Timeout) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* USB Suspend
*
* In order to conserve power, USB devices automatically enter the suspended
* state when the device has observed no bus traffic for a specified period.
* When suspended, the USB device maintains any internal status, including its
* address and configuration. Attached devices must be prepared to suspend at
* any time they are powered, regardless of if they have been assigned a
* non-default address, are configured, or neither. Bus activity may cease due
* to the host entering a suspend mode of its own. In addition, a USB device
* shall also enter the suspended state when the hub port it is attached to is
* disabled.
*
* A USB device exits suspend mode when there is bus activity. A USB device may
* also request the host to exit suspend mode or selective suspend by using
* electrical signaling to indicate remote wakeup. The ability of a device to
* signal remote wakeup is optional. If the USB device is capable of remote
* wakeup signaling, the device must support the ability of the host to enable
* and disable this capability. When the device is reset, remote wakeup
* signaling must be disabled.
*
* @param InstancePtr is a pointer to XUsbPs instance of the controller.
*
* @return
* - XST_SUCCESS if the USB device has entered Suspend mode
* successfully
* - XST_FAILURE on any error
*
* @note None.
*
******************************************************************************/
int XUsbPs_Suspend(const XUsbPs *InstancePtr)
{
(void) InstancePtr;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* USB Resume
*
If the USB controller is suspended, its operation is resumed when any
* non-idle signaling is received on its upstream facing port.
*
* @param InstancePtr is a pointer to XUsbPs instance of the controller.
*
* @return
* - XST_SUCCESS if the USB device has Resumed successfully
* - XST_FAILURE on any error
*
* @note None.
*
******************************************************************************/
int XUsbPs_Resume(const XUsbPs *InstancePtr)
{
(void) InstancePtr;
return XST_SUCCESS;
}
/*****************************************************************************/
/**
* USB Assert Resume
*
* @param InstancePtr is a pointer to XUsbPs instance of the controller.
*
* @return
* - XST_SUCCESS if the USB device has Resumed successfully
* - XST_FAILURE on any error
*
* @note None.
*
******************************************************************************/
int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr)
{
(void) InstancePtr;
return XST_SUCCESS;
}
/****************************************************************************/
/**
* This functions sets the controller's DEVICE address. It also sets the
* advance bit so the controller will wait for the next IN-ACK before the new
* address takes effect.
*
* @param InstancePtr is a pointer to XUsbPs instance of the controller.
* @param Address is the Address of the device.
*
* @return
* - XST_SUCCESS: Address set successfully.
* - XST_FAILURE: An error occurred.
* - XST_INVALID_PARAM: Invalid parameter passed, e.g. address
* value too big.
*
* @note None.
*
*****************************************************************************/
int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address)
{
Xil_AssertNonvoid(InstancePtr != NULL);
if ((InstancePtr->AppData != NULL) &&
(InstancePtr->AppData->State ==
XUSBPS_STATE_CONFIGURED)) {
return XST_FAILURE;
}
/* Check address range validity. */
if (Address > XUSBPS_DEVICEADDR_MAX) {
return XST_INVALID_PARAM;
}
/* Set the address register with the Address value provided. Also set
* the Address Advance Bit. This will cause the address to be set only
* after an IN occurred and has been ACKed on the endpoint.
*/
XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
XUSBPS_DEVICEADDR_OFFSET,
(Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) |
XUSBPS_DEVICEADDR_DEVICEAADV_MASK);
if (InstancePtr->AppData != NULL) {
if (Address)
InstancePtr->AppData->State = XUSBPS_STATE_ADDRESS;
else
InstancePtr->AppData->State = XUSBPS_STATE_DEFAULT;
}
return XST_SUCCESS;
}
/** @} */

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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops_hw.h
* @addtogroup gpiops_v3_9
* @{
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
* are defined in xgpiops.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.02a hk 08/22/13 Added low level reset API function prototype and
* related constant definitions
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/13/15 Corrected reset values of banks.
* 3.5 sne 03/14/19 Added versal support.
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
#define XGPIOPS_HW_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register offsets for the GPIO. Each register is 32 bits.
* @{
*/
#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /**< Mask and Data Register LSW, WO */
#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /**< Mask and Data Register MSW, WO */
#define XGPIOPS_DATA_OFFSET 0x00000040U /**< Data Register, RW */
#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /**< Data Register - Input, RO */
#define XGPIOPS_DIRM_OFFSET 0x00000204U /**< Direction Mode Register, RW */
#define XGPIOPS_OUTEN_OFFSET 0x00000208U /**< Output Enable Register, RW */
#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /**< Interrupt Mask Register, RO */
#define XGPIOPS_INTEN_OFFSET 0x00000210U /**< Interrupt Enable Register, WO */
#define XGPIOPS_INTDIS_OFFSET 0x00000214U /**< Interrupt Disable Register, WO*/
#define XGPIOPS_INTSTS_OFFSET 0x00000218U /**< Interrupt Status Register, RO */
#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /**< Interrupt Type Register, RW */
#define XGPIOPS_INTPOL_OFFSET 0x00000220U /**< Interrupt Polarity Register, RW */
#define XGPIOPS_INTANY_OFFSET 0x00000224U /**< Interrupt On Any Register, RW */
/** @} */
/** @name Register offsets for each Bank.
* @{
*/
#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /**< Data/Mask Registers offset */
#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /**< Data Registers offset */
#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /**< Registers offset */
/** @} */
/* For backwards compatibility */
#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 /**< Mask for backward support */
/** @name Interrupt type reset values for each bank
* @{
*/
#ifdef XPAR_PSU_GPIO_0_BASEADDR
#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#else
#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU /**< Resets specific to Zynq */
#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
#endif
#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /**< Reset common to both platforms */
#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
/** @} */
#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /**< Flag for Base Address for PS_GPIO in Versal */
#define XGPIOPS_ZERO 0U /**< Flag for 0 Value */
#define XGPIOPS_ONE 1U /**< Flag for 1 Value */
#define XGPIOPS_TWO 2U /**< Flag for 2 Value */
#define XGPIOPS_THREE 3U /**< Flag for 3 Value */
#define XGPIOPS_FOUR 4U /**< Flag for 4 Value */
#define XGPIOPS_SIX 6U /**< Flag for 6 Value */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the register offset to be read.
*
* @return The 32-bit value of the register
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* This macro writes to the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the offset of the register to be written.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes ******************************/
void XGpioPs_ResetHw(UINTPTR BaseAddress);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XGPIOPS_HW_H */
/** @} */

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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xreg_cortexa9.h
*
* This header file contains definitions for using inline assembler code. It is
* written specifically for the GNU, ARMCC compiler.
*
* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
* with the positions of the bits within the registers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 1.00a ecm/sdm 10/20/09 First release
* </pre>
*
******************************************************************************/
#ifndef XREG_CORTEXA9_H
#define XREG_CORTEXA9_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
*@cond nocomments
*/
/* GPRs */
#define XREG_GPR0 r0
#define XREG_GPR1 r1
#define XREG_GPR2 r2
#define XREG_GPR3 r3
#define XREG_GPR4 r4
#define XREG_GPR5 r5
#define XREG_GPR6 r6
#define XREG_GPR7 r7
#define XREG_GPR8 r8
#define XREG_GPR9 r9
#define XREG_GPR10 r10
#define XREG_GPR11 r11
#define XREG_GPR12 r12
#define XREG_GPR13 r13
#define XREG_GPR14 r14
#define XREG_GPR15 r15
#define XREG_CPSR cpsr
/* Coprocessor number defines */
#define XREG_CP0 0
#define XREG_CP1 1
#define XREG_CP2 2
#define XREG_CP3 3
#define XREG_CP4 4
#define XREG_CP5 5
#define XREG_CP6 6
#define XREG_CP7 7
#define XREG_CP8 8
#define XREG_CP9 9
#define XREG_CP10 10
#define XREG_CP11 11
#define XREG_CP12 12
#define XREG_CP13 13
#define XREG_CP14 14
#define XREG_CP15 15
/* Coprocessor control register defines */
#define XREG_CR0 cr0
#define XREG_CR1 cr1
#define XREG_CR2 cr2
#define XREG_CR3 cr3
#define XREG_CR4 cr4
#define XREG_CR5 cr5
#define XREG_CR6 cr6
#define XREG_CR7 cr7
#define XREG_CR8 cr8
#define XREG_CR9 cr9
#define XREG_CR10 cr10
#define XREG_CR11 cr11
#define XREG_CR12 cr12
#define XREG_CR13 cr13
#define XREG_CR14 cr14
#define XREG_CR15 cr15
/* Current Processor Status Register (CPSR) Bits */
#define XREG_CPSR_THUMB_MODE 0x20
#define XREG_CPSR_MODE_BITS 0x1F
#define XREG_CPSR_SYSTEM_MODE 0x1F
#define XREG_CPSR_UNDEFINED_MODE 0x1B
#define XREG_CPSR_DATA_ABORT_MODE 0x17
#define XREG_CPSR_SVC_MODE 0x13
#define XREG_CPSR_IRQ_MODE 0x12
#define XREG_CPSR_FIQ_MODE 0x11
#define XREG_CPSR_USER_MODE 0x10
#define XREG_CPSR_IRQ_ENABLE 0x80
#define XREG_CPSR_FIQ_ENABLE 0x40
#define XREG_CPSR_N_BIT 0x80000000
#define XREG_CPSR_Z_BIT 0x40000000
#define XREG_CPSR_C_BIT 0x20000000
#define XREG_CPSR_V_BIT 0x10000000
/* CP15 defines */
#if defined (__GNUC__) || defined (__ICCARM__)
/* C0 Register defines */
#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
/* C1 Register Defines */
#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
#else /* RVCT */
/* C0 Register defines */
#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
/* C1 Register Defines */
#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
#endif
/* XREG_CP15_CONTROL bit defines */
#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
#define XREG_CP15_CONTROL_V_BIT 0x00002000U
#define XREG_CP15_CONTROL_I_BIT 0x00001000U
#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
#define XREG_CP15_CONTROL_B_BIT 0x00000080U
#define XREG_CP15_CONTROL_C_BIT 0x00000004U
#define XREG_CP15_CONTROL_A_BIT 0x00000002U
#define XREG_CP15_CONTROL_M_BIT 0x00000001U
#if defined (__GNUC__) || defined (__ICCARM__)
/* C2 Register Defines */
#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
/* C3 Register Defines */
#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
/* C4 Register Defines */
/* Not Used */
/* C5 Register Defines */
#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
/* C6 Register Defines */
#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
/* C7 Register Defines */
#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
/* The CP15 register access below has been deprecated in favor of the new
* isb instruction in Cortex A9.
*/
#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
/* The next two CP15 register accesses below have been deprecated in favor
* of the new dsb and dmb instructions in Cortex A9.
*/
#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
/* C8 Register Defines */
#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
/* C9 Register Defines */
#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
/* C10 Register Defines */
#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
/* C11 Register Defines */
/* Not used */
/* C12 Register Defines */
#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
/* C13 Register Defines */
#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
/* C14 Register Defines */
/* not used */
/* C15 Register Defines */
#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
#else
/* C2 Register Defines */
#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
/* C3 Register Defines */
#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
/* C4 Register Defines */
/* Not Used */
/* C5 Register Defines */
#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
/* C6 Register Defines */
#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
/* C7 Register Defines */
#define XREG_CP15_NOP "cp15:0:c7:c0:4"
#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
/* The CP15 register access below has been deprecated in favor of the new
* isb instruction in Cortex A9.
*/
#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
/* The next two CP15 register accesses below have been deprecated in favor
* of the new dsb and dmb instructions in Cortex A9.
*/
#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
/* C8 Register Defines */
#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
/* C9 Register Defines */
#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
/* C10 Register Defines */
#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
/* C11 Register Defines */
/* Not used */
/* C12 Register Defines */
#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
/* C13 Register Defines */
#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
/* C14 Register Defines */
/* not used */
/* C15 Register Defines */
#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
#endif
/* MPE register definitions */
#define XREG_FPSID c0
#define XREG_FPSCR c1
#define XREG_MVFR1 c6
#define XREG_MVFR0 c7
#define XREG_FPEXC c8
#define XREG_FPINST c9
#define XREG_FPINST2 c10
/* FPSID bits */
#define XREG_FPSID_IMPLEMENTER_BIT (24)
#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
#define XREG_FPSID_SOFTWARE (1<<23)
#define XREG_FPSID_ARCH_BIT (16)
#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
#define XREG_FPSID_PART_BIT (8)
#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
#define XREG_FPSID_VARIANT_BIT (4)
#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
#define XREG_FPSID_REV_BIT (0)
#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
/* FPSCR bits */
#define XREG_FPSCR_N_BIT (1 << 31)
#define XREG_FPSCR_Z_BIT (1 << 30)
#define XREG_FPSCR_C_BIT (1 << 29)
#define XREG_FPSCR_V_BIT (1 << 28)
#define XREG_FPSCR_QC (1 << 27)
#define XREG_FPSCR_AHP (1 << 26)
#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
#define XREG_FPSCR_RMODE_BIT (22)
#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
#define XREG_FPSCR_STRIDE_BIT (20)
#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
#define XREG_FPSCR_LENGTH_BIT (16)
#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
#define XREG_FPSCR_IDC (1 << 7)
#define XREG_FPSCR_IXC (1 << 4)
#define XREG_FPSCR_UFC (1 << 3)
#define XREG_FPSCR_OFC (1 << 2)
#define XREG_FPSCR_DZC (1 << 1)
#define XREG_FPSCR_IOC (1 << 0)
/* MVFR0 bits */
#define XREG_MVFR0_RMODE_BIT (28)
#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
#define XREG_MVFR0_SHORT_VEC_BIT (24)
#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
#define XREG_MVFR0_SQRT_BIT (20)
#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
#define XREG_MVFR0_DIVIDE_BIT (16)
#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
#define XREG_MVFR0_EXEC_TRAP_BIT (12)
#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
#define XREG_MVFR0_DP_BIT (8)
#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
#define XREG_MVFR0_SP_BIT (4)
#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
#define XREG_MVFR0_A_SIMD_BIT (0)
#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
/* FPEXC bits */
#define XREG_FPEXC_EX (1 << 31)
#define XREG_FPEXC_EN (1 << 30)
#define XREG_FPEXC_DEX (1 << 29)
/**
*@endcond
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XREG_CORTEXA9_H */

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