From a2bee250026142ff0000f1cb7c89b397aa38f3db Mon Sep 17 00:00:00 2001 From: Dylan Missuwe Date: Sun, 6 Nov 2022 12:00:22 +0100 Subject: [PATCH] Update README.md --- README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.md b/README.md index 7d6f4ff..2620817 100644 --- a/README.md +++ b/README.md @@ -15,3 +15,7 @@ If we were to send a sinewave through the transducers with a delay determined by ## Setup There are two array's used in the levitation example. One is facing upwards and the other is facing downwards. They are facing eachother with a distance of 70mm. this distance is arbitrarily chosen based on the needed volume for levitation. + +## FPGA +The FPGA implementation receives 7 bit values from the PS for every transducer. This value sets the phase of the output signal. This is acheived by making a fifo of length = 2^7. The 40KHz signal is fed into the fifo at 40KHz * 2^7 = 5.12MHz. The reason for this is because we want a full period of the signal in the fifo. The 7 bit value determines where the output signal is tapped from. +Im currently cleaning up the FPGA implementation and turn it into an IP-block, i will include the files in this repository once i'm finished.