Update README.md
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@ -68,7 +68,7 @@ here is an overview of the in- and output signals:
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- **S00_AXI**: AXI slave port
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- **pmod_out**: this port goes directly to a Pmod port on the FPGA-board and drives the transducer board.
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The AXI peripheral IP_block generates the delayed signals and outputs them as a 25 bit vector. This vector is split into 5x 5 bit vectors that enter the seializer. The data is then clocked bit by bit to the output.
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The AXI peripheral IP_block generates the delayed signals and outputs them as a 25 bit vector. This vector is split into 5x 5 bit vectors by the xlslice blocks. The 5 bit vectors enter the seializer. The data is then clocked bit by bit to the output.
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### Implementation
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[<img src="Vivado\block_diagram\top_level_design.svg"/>]()
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@ -78,11 +78,6 @@ TODO
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### Processing System
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The Processing system sends data to the FPGA facric which adjusts the phase offsets of the physical transducers.
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To calculate the phases for a beam, the following formula is used:
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### Practical limitations
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In an ideal world the signal applied to the physical transducer should give the same signal in air pressure. That is however not the case. For every transducer there is a significant random phase shift present. This will completely negate our effort to acheive a phased array. So we have to measure the phase shift of every transducer and incorporate this into the phase calculations.
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