41 lines
1.4 KiB
Plaintext
41 lines
1.4 KiB
Plaintext
################################################################################
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# DONOT REMOVE THIS FILE
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# Unified simulation database file for selected simulation model for IP
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#
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# File: ssm.db (Sun Sep 15 03:14:15 2024)
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#
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# This file is generated by the unified simulation automation and contains the
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# selected simulation model information for the IP/BD instances.
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# DONOT REMOVE THIS FILE
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################################################################################
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axi_jtag_test_clk_wiz_0_0,rtl
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axi_jtag_test_delay_wrap_wrapper_0_1,rtl
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axi_jtag_test_divider_0_0,rtl
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axi_jtag_test_divider_1_0,rtl
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axi_jtag_test_divider_1_2,rtl
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axi_jtag_test_ila_0_0,rtl
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axi_jtag_test_jtag_axi_0_1,rtl
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axi_jtag_test_serial_to_parallel_0_0,rtl
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axi_jtag_test_xlconstant_0_0,rtl
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axi_jtag_test_xlslice_0_0,rtl
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axi_jtag_test_xlslice_1_0,rtl
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delay_wrap_Serializer_0_0,rtl
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delay_wrap_axi_delay_generator_0_0,rtl
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delay_wrap_xlconcat_0_0,rtl
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delay_wrap_xlconstant_0_0,rtl
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delay_wrap_xlslice_0_0,rtl
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delay_wrap_xlslice_1_0,rtl
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delay_wrap_xlslice_2_0,rtl
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delay_wrap_xlslice_3_0,rtl
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delay_wrap_xlslice_4_0,rtl
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design_1_auto_pc_0,rtl
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design_1_axi_delay_generator_0_0,rtl
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design_1_axi_gpio_0_0,rtl
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design_1_clk_wiz_0_0,rtl
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design_1_clk_wiz_0_1,rtl
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design_1_processing_system7_0_0,rtl
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design_1_ps7_0_axi_periph_0,rtl
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design_1_rst_ps7_0_50M_0,rtl
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design_1_xbar_0,rtl
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design_1_xlconstant_0_0,rtl
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