commit faf2b57c5907ad8c14e6d87f2ae74e2ea25371e5 Author: zcy <290198252@qq.com> Date: Sat Sep 14 13:31:12 2024 +0800 f diff --git a/api_lib/win32/xjtag.dll b/api_lib/win32/xjtag.dll new file mode 100644 index 0000000..fd8fba7 Binary files /dev/null and b/api_lib/win32/xjtag.dll differ diff --git a/api_lib/win32/xjtag.lib b/api_lib/win32/xjtag.lib new file mode 100644 index 0000000..7018152 Binary files /dev/null and b/api_lib/win32/xjtag.lib differ diff --git a/api_lib/x64/xjtag.dll b/api_lib/x64/xjtag.dll new file mode 100644 index 0000000..ac65ce4 Binary files /dev/null and b/api_lib/x64/xjtag.dll differ diff --git a/api_lib/x64/xjtag.lib b/api_lib/x64/xjtag.lib new file mode 100644 index 0000000..940666a Binary files /dev/null and b/api_lib/x64/xjtag.lib differ diff --git a/api_lib/xjtag.h b/api_lib/xjtag.h new file mode 100644 index 0000000..60186a4 --- /dev/null +++ b/api_lib/xjtag.h @@ -0,0 +1,24 @@ +// The following ifdef block is the standard way of creating macros which make exporting +// from a DLL simpler. All files within this DLL are compiled with the XJTAG_EXPORTS +// symbol defined on the command line. This symbol should not be defined on any project +// that uses this DLL. This way any other project whose source files include this file see +// XJTAG_API functions as being imported from a DLL, whereas this DLL sees symbols +// defined with this macro as being exported. +#ifdef XJTAG_EXPORTS +#define XJTAG_API __declspec(dllexport) +#else +#define XJTAG_API __declspec(dllimport) +#endif + + +XJTAG_API int xbus_axi_open(unsigned long *hif,char num,char *sel,int *err); +XJTAG_API int xbus_axi_close(unsigned long hif); +XJTAG_API int xbus_init(unsigned long hif,unsigned long frqReq,unsigned int mode, unsigned char device_id,int *er); +XJTAG_API int xbus_get_ver(unsigned long hif,unsigned int *sw_ver,unsigned int *ip_ver,unsigned int *hw_ver); +XJTAG_API int xbus_axi_write(unsigned long hif, unsigned int addr,unsigned int wdat,unsigned int mask); +XJTAG_API int xbus_axi_read(unsigned long hif, unsigned int addr,unsigned int *rdat); +XJTAG_API int xbus_local_write(unsigned long hif, unsigned int addr,unsigned int wdat,unsigned int mask); +XJTAG_API int xbus_local_read(unsigned long hif, unsigned int addr,unsigned int *rdat); + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa.logs/runme.log b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa.logs/runme.log new file mode 100644 index 0000000..4d89efa --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa.logs/runme.log @@ -0,0 +1,327 @@ + +*** Running vivado + with args -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source clk_wiz_0.tcl -notrace +Command: synth_design -top clk_wiz_0 -part xc7k160tffg676-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 8224 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 394.207 ; gain = 93.684 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] + Parameter CAPACITANCE bound to: DONT_CARE - type: string + Parameter DIFF_TERM bound to: FALSE - type: string + Parameter DQS_BIAS bound to: FALSE - type: string + Parameter IBUF_DELAY_VALUE bound to: 0 - type: string + Parameter IBUF_LOW_PWR bound to: TRUE - type: string + Parameter IFD_DELAY_VALUE bound to: AUTO - type: string + Parameter IOSTANDARD bound to: DEFAULT - type: string +INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (1#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: float + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float + Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float + Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string + Parameter COMPENSATION bound to: ZHOLD - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 + Parameter IS_PSEN_INVERTED bound to: 1'b0 + Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 + Parameter IS_PWRDWN_INVERTED bound to: 1'b0 + Parameter IS_RST_INVERTED bound to: 1'b0 + Parameter REF_JITTER1 bound to: 0.010000 - type: float + Parameter REF_JITTER2 bound to: 0.010000 - type: float + Parameter SS_EN bound to: FALSE - type: string + Parameter SS_MODE bound to: CENTER_HIGH - type: string + Parameter SS_MOD_PERIOD bound to: 10000 - type: integer + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (2#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (3#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (5#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.281 ; gain = 143.758 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.281 ; gain = 143.758 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.281 ; gain = 143.758 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 715.059 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 779.535 ; gain = 479.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 779.535 ; gain = 479.012 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 779.535 ; gain = 479.012 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |BUFG | 2| +|2 |MMCME2_ADV | 1| +|3 |IBUFDS | 1| ++------+-----------+------+ + +Report Instance Areas: ++------+---------+------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------+------+ +|1 |top | | 4| +|2 | inst |clk_wiz_0_clk_wiz | 4| ++------+---------+------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 781.172 ; gain = 209.871 +Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 781.180 ; gain = 480.648 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 802.621 ; gain = 513.566 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/53a5071bda7105fa.xci b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/53a5071bda7105fa.xci new file mode 100644 index 0000000..26f1fc3 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/53a5071bda7105fa.xci @@ -0,0 +1,294 @@ + + + xilinx.com + ipcache + 53a5071bda7105fa + 0 + + + clk_wiz_0 + + + 100000000 + 100000000 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 0.010 + 100.0 + 0.010 + BUFG + 112.316 + false + 89.971 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_0 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 5.000 + 0.000 + false + 5.000 + 10.0 + 10.000 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 1 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 200.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + false + false + false + false + kintex7 + + xc7k160t + ffg676 + VERILOG + + MIXED + -2 + + TRUE + TRUE + 2e0224e4 + 53a5071bda7105fa + fa99e727 + IP_Unknown + 1 + TRUE + . + + . + 2018.2 + GLOBAL + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0.dcp b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0.dcp new file mode 100644 index 0000000..d1dd403 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0.dcp differ diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_sim_netlist.v b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_sim_netlist.v new file mode 100644 index 0000000..8967037 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_sim_netlist.v @@ -0,0 +1,245 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 17:10:06 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v +// Design : clk_wiz_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (clk_out1, + locked, + clk_in1_p, + clk_in1_n); + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; + + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_n; + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_p; + wire clk_out1; + wire locked; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz inst + (.clk_in1_n(clk_in1_n), + .clk_in1_p(clk_in1_p), + .clk_out1(clk_out1), + .locked(locked)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz + (clk_out1, + locked, + clk_in1_p, + clk_in1_n); + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; + + wire clk_in1_clk_wiz_0; + wire clk_in1_n; + wire clk_in1_p; + wire clk_out1; + wire clk_out1_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfbout_clk_wiz_0; + wire locked; + wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; + wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; + wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; + wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_clk_wiz_0), + .O(clkfbout_buf_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUFDS #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufgds + (.I(clk_in1_p), + .IB(clk_in1_n), + .O(clk_in1_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(clk_out1_clk_wiz_0), + .O(clk_out1)); + (* BOX_TYPE = "PRIMITIVE" *) + MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(5.000000), + .CLKFBOUT_PHASE(0.000000), + .CLKFBOUT_USE_FINE_PS("FALSE"), + .CLKIN1_PERIOD(5.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE_F(10.000000), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT0_USE_FINE_PS("FALSE"), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT1_USE_FINE_PS("FALSE"), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT2_USE_FINE_PS("FALSE"), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT3_USE_FINE_PS("FALSE"), + .CLKOUT4_CASCADE("FALSE"), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT4_USE_FINE_PS("FALSE"), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .CLKOUT5_USE_FINE_PS("FALSE"), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.500000), + .CLKOUT6_PHASE(0.000000), + .CLKOUT6_USE_FINE_PS("FALSE"), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(1), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PSEN_INVERTED(1'b0), + .IS_PSINCDEC_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .SS_EN("FALSE"), + .SS_MODE("CENTER_HIGH"), + .SS_MOD_PERIOD(10000), + .STARTUP_WAIT("FALSE")) + mmcm_adv_inst + (.CLKFBIN(clkfbout_buf_clk_wiz_0), + .CLKFBOUT(clkfbout_clk_wiz_0), + .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), + .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), + .CLKIN1(clk_in1_clk_wiz_0), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), + .CLKOUT0(clk_out1_clk_wiz_0), + .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), + .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), + .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), + .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), + .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), + .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(locked), + .PSCLK(1'b0), + .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(1'b0), + .RST(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_sim_netlist.vhdl b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_sim_netlist.vhdl new file mode 100644 index 0000000..da3b292 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_sim_netlist.vhdl @@ -0,0 +1,189 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 17:10:06 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl +-- Design : clk_wiz_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is + port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is + signal clk_in1_clk_wiz_0 : STD_LOGIC; + signal clk_out1_clk_wiz_0 : STD_LOGIC; + signal clkfbout_buf_clk_wiz_0 : STD_LOGIC; + signal clkfbout_clk_wiz_0 : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkin1_ibufgds : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of clkin1_ibufgds : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of clkin1_ibufgds : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of clkin1_ibufgds : label is "AUTO"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_clk_wiz_0, + O => clkfbout_buf_clk_wiz_0 + ); +clkin1_ibufgds: unisim.vcomponents.IBUFDS + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => clk_in1_p, + IB => clk_in1_n, + O => clk_in1_clk_wiz_0 + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => clk_out1_clk_wiz_0, + O => clk_out1 + ); +mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 5.000000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 5.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 10.000000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_DIVIDE => 1, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => clkfbout_buf_clk_wiz_0, + CLKFBOUT => clkfbout_clk_wiz_0, + CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, + CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, + CLKIN1 => clk_in1_clk_wiz_0, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, + CLKOUT0 => clk_out1_clk_wiz_0, + CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, + CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, + CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, + CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, + CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, + CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, + CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => locked, + PSCLK => '0', + PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +begin +inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz + port map ( + clk_in1_n => clk_in1_n, + clk_in1_p => clk_in1_p, + clk_out1 => clk_out1, + locked => locked + ); +end STRUCTURE; diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_stub.v b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_stub.v new file mode 100644 index 0000000..4e42e43 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 17:10:06 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, locked, clk_in1_p, clk_in1_n) +/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1_p,clk_in1_n" */; + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_stub.vhdl b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..8fdbf23 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/clk_wiz_0_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 17:10:06 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1_p,clk_in1_n"; +begin +end; diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/stats.txt b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/stats.txt new file mode 100644 index 0000000..1aaa280 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/53a5071bda7105fa/stats.txt @@ -0,0 +1,4 @@ +NumberHits:0 +Timestamp: Sun Jun 28 09:10:06 UTC 2020 +VLNV: xilinx.com:ip:clk_wiz:6.0 +SynthRuntime: 31 diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e.logs/runme.log b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e.logs/runme.log new file mode 100644 index 0000000..ebea44f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e.logs/runme.log @@ -0,0 +1,975 @@ + +*** Running vivado + with args -log design_1_axi_gpio_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_axi_gpio_0_0.tcl + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source design_1_axi_gpio_0_0.tcl -notrace +Command: synth_design -top design_1_axi_gpio_0_0 -part xc7k160tffg676-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 1728 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 396.789 ; gain = 95.898 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'design_1_axi_gpio_0_0' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:86] + Parameter C_FAMILY bound to: kintex7 - type: string + Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer + Parameter C_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_GPIO2_WIDTH bound to: 32 - type: integer + Parameter C_ALL_INPUTS bound to: 0 - type: integer + Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer + Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000000000000000000000 + Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111 + Parameter C_IS_DUAL bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000 + Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111 +INFO: [Synth 8-3491] module 'axi_gpio' declared at 'd:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1265' bound to instance 'U0' of component 'axi_gpio' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:172] +INFO: [Synth 8-638] synthesizing module 'axi_gpio' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1358] + Parameter C_FAMILY bound to: kintex7 - type: string + Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer + Parameter C_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_GPIO2_WIDTH bound to: 32 - type: integer + Parameter C_ALL_INPUTS bound to: 0 - type: integer + Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer + Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT bound to: 0 - type: integer + Parameter C_TRI_DEFAULT bound to: -1 - type: integer + Parameter C_IS_DUAL bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer + Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer +INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1295] +INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1296] +INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] + Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer + Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111 + Parameter C_USE_WSTRB bound to: 0 - type: integer + Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer + Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 + Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 + Parameter C_FAMILY bound to: kintex7 - type: string +INFO: [Synth 8-638] synthesizing module 'slave_attachment' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] + Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 + Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 + Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer + Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer + Parameter C_USE_WSTRB bound to: 0 - type: integer + Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer + Parameter C_FAMILY bound to: kintex7 - type: string +INFO: [Synth 8-638] synthesizing module 'address_decoder' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] + Parameter C_BUS_AWIDTH bound to: 9 - type: integer + Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer + Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 + Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-638] synthesizing module 'pselect_f' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b00 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f' (1#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b01 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (1#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b10 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (1#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b11 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (1#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-256] done synthesizing module 'address_decoder' (2#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] +INFO: [Synth 8-226] default block is never used [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] +INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (3#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] +INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (4#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] +INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:178] + Parameter C_DW bound to: 32 - type: integer + Parameter C_AW bound to: 9 - type: integer + Parameter C_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_GPIO2_WIDTH bound to: 32 - type: integer + Parameter C_MAX_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT bound to: 0 - type: integer + Parameter C_TRI_DEFAULT bound to: -1 - type: integer + Parameter C_IS_DUAL bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer + Parameter C_ALL_INPUTS bound to: 0 - type: integer + Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer + Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer + Parameter C_FAMILY bound to: kintex7 - type: string +INFO: [Synth 8-226] default block is never used [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:443] +INFO: [Synth 8-638] synthesizing module 'cdc_sync' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] + Parameter C_CDC_TYPE bound to: 1 - type: integer + Parameter C_RESET_STATE bound to: 0 - type: integer + Parameter C_SINGLE_BIT bound to: 0 - type: integer + Parameter C_FLOP_INPUT bound to: 0 - type: integer + Parameter C_VECTOR_WIDTH bound to: 32 - type: integer + Parameter C_MTBF_STAGES bound to: 4 - type: integer + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] +INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (5#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (6#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:178] +INFO: [Synth 8-256] done synthesizing module 'axi_gpio' (7#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1358] +INFO: [Synth 8-256] done synthesizing module 'design_1_axi_gpio_0_0' (8#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:86] +WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_aclk +WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_resetn +WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_in +WARNING: [Synth 8-3331] design cdc_sync has unconnected port scndry_resetn +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[1] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[2] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[3] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[4] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[7] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[8] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[0] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[1] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[2] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[3] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[0] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[1] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[2] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[3] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[4] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[5] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[6] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[7] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[8] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[9] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[10] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[11] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[12] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[13] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[14] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[15] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[16] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[17] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[18] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[19] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[20] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[21] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[22] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[23] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[24] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[25] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[26] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[27] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[28] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[29] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[30] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[31] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[0] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[1] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[2] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[3] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[4] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[7] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[8] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Bus_RNW +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[3] +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[2] +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[1] +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[0] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 449.645 ; gain = 148.754 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 449.645 ; gain = 148.754 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 449.645 ; gain = 148.754 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 192 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_ooc.xdc] for cell 'U0' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'U0' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'U0' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'U0' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'U0' +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/design_1_axi_gpio_0_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/design_1_axi_gpio_0_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 192 instances were transformed. + FDR => FDRE: 192 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 810.129 ; gain = 1.438 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 810.129 ; gain = 509.238 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 810.129 ; gain = 509.238 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for U0. (constraint file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/design_1_axi_gpio_0_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 810.129 ; gain = 509.238 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment' +INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE2 | 0001 | 00 + iSTATE | 0010 | 01 + iSTATE0 | 0100 | 10 + iSTATE1 | 1000 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 810.129 ; gain = 509.238 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 5 + 9 Bit Registers := 1 + 4 Bit Registers := 1 + 2 Bit Registers := 3 + 1 Bit Registers := 82 ++---Muxes : + 2 Input 32 Bit Muxes := 2 + 5 Input 32 Bit Muxes := 1 + 2 Input 9 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 5 + 7 Input 2 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 43 + 4 Input 1 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module pselect_f +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module pselect_f__parameterized0 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module pselect_f__parameterized1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module pselect_f__parameterized2 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module address_decoder +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 6 +Module slave_attachment +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 9 Bit Registers := 1 + 4 Bit Registers := 1 + 2 Bit Registers := 3 + 1 Bit Registers := 7 ++---Muxes : + 2 Input 9 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 5 + 7 Input 2 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 4 + 4 Input 1 Bit Muxes := 3 +Module GPIO_Core +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 3 + 1 Bit Registers := 66 ++---Muxes : + 2 Input 32 Bit Muxes := 2 + 5 Input 32 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 35 +Module axi_gpio +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 1 + 1 Bit Registers := 3 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-4471] merging register 'bus2ip_reset_reg' into 'AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1684] +WARNING: [Synth 8-6014] Unused sequential element bus2ip_reset_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1684] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[3] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[2] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[1] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[0] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[31] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[30] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[29] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[28] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[27] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[26] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[25] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[24] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[23] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[22] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[21] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[20] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[19] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[18] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[17] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[16] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[15] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[14] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[13] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[12] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[11] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[10] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[9] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[8] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[7] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[6] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[5] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[4] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[3] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[2] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[1] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[0] +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[1] ) +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[1]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[1]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[7]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[6]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[5]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[4]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[1]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[0]) is unused and will be removed from module axi_gpio. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 810.129 ; gain = 509.238 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 812.570 ; gain = 511.680 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 823.102 ; gain = 522.211 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 834.758 ; gain = 533.867 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 834.758 ; gain = 533.867 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 834.758 ; gain = 533.867 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 834.758 ; gain = 533.867 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 834.758 ; gain = 533.867 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 834.758 ; gain = 533.867 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 834.758 ; gain = 533.867 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT1 | 2| +|2 |LUT2 | 9| +|3 |LUT3 | 7| +|4 |LUT4 | 6| +|5 |LUT5 | 108| +|6 |LUT6 | 8| +|7 |FDR | 128| +|8 |FDRE | 221| +|9 |FDSE | 33| ++------+-----+------+ + +Report Instance Areas: ++------+------------------------------------+-----------------+------+ +| |Instance |Module |Cells | ++------+------------------------------------+-----------------+------+ +|1 |top | | 522| +|2 | U0 |axi_gpio | 522| +|3 | AXI_LITE_IPIF_I |axi_lite_ipif | 131| +|4 | I_SLAVE_ATTACHMENT |slave_attachment | 131| +|5 | I_DECODER |address_decoder | 55| +|6 | gpio_core_1 |GPIO_Core | 357| +|7 | \Not_Dual.INPUT_DOUBLE_REGS3 |cdc_sync | 128| ++------+------------------------------------+-----------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 834.758 ; gain = 533.867 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 37 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 834.758 ; gain = 173.383 +Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 834.758 ; gain = 533.867 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 128 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 128 instances were transformed. + FDR => FDRE: 128 instances + +INFO: [Common 17-83] Releasing license: Synthesis +230 Infos, 127 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 838.504 ; gain = 546.496 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/design_1_axi_gpio_0_0_synth_1/design_1_axi_gpio_0_0.dcp' has been generated. diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0.dcp b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0.dcp new file mode 100644 index 0000000..33273db Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0.dcp differ diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_sim_netlist.v b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_sim_netlist.v new file mode 100644 index 0000000..d05da11 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_sim_netlist.v @@ -0,0 +1,6465 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 17:10:34 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_0_0_sim_netlist.v +// Design : design_1_axi_gpio_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core + (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg , + GPIO_xferAck_i, + gpio_xferAck_Reg, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg , + gpio_io_o, + gpio_io_t, + ip2bus_wrack_i, + ip2bus_rdack_i, + bus2ip_rnw_i_reg, + s_axi_aclk, + SR, + p_73_in, + p_75_in, + bus2ip_rnw, + bus2ip_cs, + gpio_io_i, + E, + s_axi_wdata, + bus2ip_rnw_i_reg_0); + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ; + output GPIO_xferAck_i; + output gpio_xferAck_Reg; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ; + output [31:0]gpio_io_o; + output [31:0]gpio_io_t; + output ip2bus_wrack_i; + output ip2bus_rdack_i; + input bus2ip_rnw_i_reg; + input s_axi_aclk; + input [0:0]SR; + input p_73_in; + input p_75_in; + input bus2ip_rnw; + input bus2ip_cs; + input [31:0]gpio_io_i; + input [0:0]E; + input [31:0]s_axi_wdata; + input [0:0]bus2ip_rnw_i_reg_0; + + wire [0:0]E; + wire GPIO_xferAck_i; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[0]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[0]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1[10]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2[10]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1[11]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2[11]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1[12]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2[12]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1[13]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2[13]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1[14]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2[14]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1[15]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2[15]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1[16]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2[16]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1[17]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2[17]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1[18]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2[18]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1[19]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2[19]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[1]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[1]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1[20]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2[20]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1[21]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2[21]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1[22]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2[22]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1[23]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2[23]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1[24]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2[24]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1[25]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2[25]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1[26]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2[26]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1[27]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2[27]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1[28]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2[28]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1[29]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2[29]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1[2]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2[2]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1[30]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2[30]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_2_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2[31]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1[3]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2[3]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1[4]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2[4]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1[5]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2[5]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1[6]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2[6]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1[7]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2[7]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1[8]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2[8]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1[9]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2[9]_i_1_n_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ; + wire [0:0]SR; + wire bus2ip_cs; + wire bus2ip_rnw; + wire bus2ip_rnw_i_reg; + wire [0:0]bus2ip_rnw_i_reg_0; + wire [0:31]gpio_Data_In; + wire [31:0]gpio_io_i; + wire [0:31]gpio_io_i_d2; + wire [31:0]gpio_io_o; + wire [31:0]gpio_io_t; + wire gpio_xferAck_Reg; + wire iGPIO_xferAck; + wire ip2bus_rdack_i; + wire ip2bus_wrack_i; + wire p_73_in; + wire p_75_in; + wire s_axi_aclk; + wire [31:0]s_axi_wdata; + + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[0]_i_1 + (.I0(gpio_io_o[31]), + .I1(gpio_io_t[31]), + .I2(p_73_in), + .I3(gpio_Data_In[0]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[0]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[0]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[0]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ), + .I1(gpio_io_t[31]), + .I2(p_73_in), + .I3(gpio_Data_In[0]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[0]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[0]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1[10]_i_1 + (.I0(gpio_io_o[21]), + .I1(gpio_io_t[21]), + .I2(p_73_in), + .I3(gpio_Data_In[10]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1[10]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg[10] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1[10]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2[10]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ), + .I1(gpio_io_t[21]), + .I2(p_73_in), + .I3(gpio_Data_In[10]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2[10]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg[10] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2[10]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1[11]_i_1 + (.I0(gpio_io_o[20]), + .I1(gpio_io_t[20]), + .I2(p_73_in), + .I3(gpio_Data_In[11]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1[11]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg[11] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1[11]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2[11]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ), + .I1(gpio_io_t[20]), + .I2(p_73_in), + .I3(gpio_Data_In[11]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2[11]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg[11] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2[11]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1[12]_i_1 + (.I0(gpio_io_o[19]), + .I1(gpio_io_t[19]), + .I2(p_73_in), + .I3(gpio_Data_In[12]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1[12]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg[12] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1[12]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2[12]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ), + .I1(gpio_io_t[19]), + .I2(p_73_in), + .I3(gpio_Data_In[12]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2[12]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg[12] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2[12]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1[13]_i_1 + (.I0(gpio_io_o[18]), + .I1(gpio_io_t[18]), + .I2(p_73_in), + .I3(gpio_Data_In[13]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1[13]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg[13] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1[13]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2[13]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ), + .I1(gpio_io_t[18]), + .I2(p_73_in), + .I3(gpio_Data_In[13]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2[13]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg[13] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2[13]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1[14]_i_1 + (.I0(gpio_io_o[17]), + .I1(gpio_io_t[17]), + .I2(p_73_in), + .I3(gpio_Data_In[14]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1[14]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg[14] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1[14]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2[14]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ), + .I1(gpio_io_t[17]), + .I2(p_73_in), + .I3(gpio_Data_In[14]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2[14]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg[14] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2[14]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1[15]_i_1 + (.I0(gpio_io_o[16]), + .I1(gpio_io_t[16]), + .I2(p_73_in), + .I3(gpio_Data_In[15]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1[15]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg[15] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1[15]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2[15]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ), + .I1(gpio_io_t[16]), + .I2(p_73_in), + .I3(gpio_Data_In[15]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2[15]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg[15] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2[15]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1[16]_i_1 + (.I0(gpio_io_o[15]), + .I1(gpio_io_t[15]), + .I2(p_73_in), + .I3(gpio_Data_In[16]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1[16]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg[16] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1[16]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2[16]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ), + .I1(gpio_io_t[15]), + .I2(p_73_in), + .I3(gpio_Data_In[16]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2[16]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg[16] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2[16]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1[17]_i_1 + (.I0(gpio_io_o[14]), + .I1(gpio_io_t[14]), + .I2(p_73_in), + .I3(gpio_Data_In[17]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1[17]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg[17] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1[17]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2[17]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ), + .I1(gpio_io_t[14]), + .I2(p_73_in), + .I3(gpio_Data_In[17]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2[17]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg[17] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2[17]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1[18]_i_1 + (.I0(gpio_io_o[13]), + .I1(gpio_io_t[13]), + .I2(p_73_in), + .I3(gpio_Data_In[18]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1[18]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg[18] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1[18]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2[18]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ), + .I1(gpio_io_t[13]), + .I2(p_73_in), + .I3(gpio_Data_In[18]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2[18]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg[18] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2[18]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1[19]_i_1 + (.I0(gpio_io_o[12]), + .I1(gpio_io_t[12]), + .I2(p_73_in), + .I3(gpio_Data_In[19]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1[19]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg[19] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1[19]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2[19]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ), + .I1(gpio_io_t[12]), + .I2(p_73_in), + .I3(gpio_Data_In[19]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2[19]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg[19] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2[19]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[1]_i_1 + (.I0(gpio_io_o[30]), + .I1(gpio_io_t[30]), + .I2(p_73_in), + .I3(gpio_Data_In[1]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[1]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[1]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[1]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ), + .I1(gpio_io_t[30]), + .I2(p_73_in), + .I3(gpio_Data_In[1]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[1]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[1]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1[20]_i_1 + (.I0(gpio_io_o[11]), + .I1(gpio_io_t[11]), + .I2(p_73_in), + .I3(gpio_Data_In[20]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1[20]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg[20] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1[20]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2[20]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ), + .I1(gpio_io_t[11]), + .I2(p_73_in), + .I3(gpio_Data_In[20]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2[20]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg[20] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2[20]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1[21]_i_1 + (.I0(gpio_io_o[10]), + .I1(gpio_io_t[10]), + .I2(p_73_in), + .I3(gpio_Data_In[21]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1[21]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg[21] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1[21]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2[21]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ), + .I1(gpio_io_t[10]), + .I2(p_73_in), + .I3(gpio_Data_In[21]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2[21]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg[21] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2[21]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1[22]_i_1 + (.I0(gpio_io_o[9]), + .I1(gpio_io_t[9]), + .I2(p_73_in), + .I3(gpio_Data_In[22]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1[22]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg[22] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1[22]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2[22]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ), + .I1(gpio_io_t[9]), + .I2(p_73_in), + .I3(gpio_Data_In[22]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2[22]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg[22] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2[22]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1[23]_i_1 + (.I0(gpio_io_o[8]), + .I1(gpio_io_t[8]), + .I2(p_73_in), + .I3(gpio_Data_In[23]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1[23]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg[23] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1[23]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2[23]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ), + .I1(gpio_io_t[8]), + .I2(p_73_in), + .I3(gpio_Data_In[23]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2[23]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg[23] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2[23]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1[24]_i_1 + (.I0(gpio_io_o[7]), + .I1(gpio_io_t[7]), + .I2(p_73_in), + .I3(gpio_Data_In[24]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1[24]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg[24] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1[24]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2[24]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ), + .I1(gpio_io_t[7]), + .I2(p_73_in), + .I3(gpio_Data_In[24]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2[24]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg[24] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2[24]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1[25]_i_1 + (.I0(gpio_io_o[6]), + .I1(gpio_io_t[6]), + .I2(p_73_in), + .I3(gpio_Data_In[25]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1[25]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg[25] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1[25]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2[25]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ), + .I1(gpio_io_t[6]), + .I2(p_73_in), + .I3(gpio_Data_In[25]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2[25]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg[25] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2[25]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1[26]_i_1 + (.I0(gpio_io_o[5]), + .I1(gpio_io_t[5]), + .I2(p_73_in), + .I3(gpio_Data_In[26]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1[26]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg[26] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1[26]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2[26]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ), + .I1(gpio_io_t[5]), + .I2(p_73_in), + .I3(gpio_Data_In[26]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2[26]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg[26] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2[26]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1[27]_i_1 + (.I0(gpio_io_o[4]), + .I1(gpio_io_t[4]), + .I2(p_73_in), + .I3(gpio_Data_In[27]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1[27]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg[27] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1[27]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2[27]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ), + .I1(gpio_io_t[4]), + .I2(p_73_in), + .I3(gpio_Data_In[27]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2[27]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg[27] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2[27]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1[28]_i_1 + (.I0(gpio_io_o[3]), + .I1(gpio_io_t[3]), + .I2(p_73_in), + .I3(gpio_Data_In[28]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1[28]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg[28] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1[28]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2[28]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ), + .I1(gpio_io_t[3]), + .I2(p_73_in), + .I3(gpio_Data_In[28]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2[28]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg[28] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2[28]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1[29]_i_1 + (.I0(gpio_io_o[2]), + .I1(gpio_io_t[2]), + .I2(p_73_in), + .I3(gpio_Data_In[29]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1[29]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg[29] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1[29]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2[29]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ), + .I1(gpio_io_t[2]), + .I2(p_73_in), + .I3(gpio_Data_In[29]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2[29]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg[29] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2[29]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1[2]_i_1 + (.I0(gpio_io_o[29]), + .I1(gpio_io_t[29]), + .I2(p_73_in), + .I3(gpio_Data_In[2]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1[2]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg[2] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1[2]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2[2]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ), + .I1(gpio_io_t[29]), + .I2(p_73_in), + .I3(gpio_Data_In[2]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2[2]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg[2] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2[2]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1[30]_i_1 + (.I0(gpio_io_o[1]), + .I1(gpio_io_t[1]), + .I2(p_73_in), + .I3(gpio_Data_In[30]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1[30]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg[30] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1[30]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2[30]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ), + .I1(gpio_io_t[1]), + .I2(p_73_in), + .I3(gpio_Data_In[30]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2[30]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg[30] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2[30]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_2 + (.I0(gpio_io_o[0]), + .I1(gpio_io_t[0]), + .I2(p_73_in), + .I3(gpio_Data_In[31]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_2_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg[31] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_2_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2[31]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ), + .I1(gpio_io_t[0]), + .I2(p_73_in), + .I3(gpio_Data_In[31]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2[31]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg[31] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2[31]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1[3]_i_1 + (.I0(gpio_io_o[28]), + .I1(gpio_io_t[28]), + .I2(p_73_in), + .I3(gpio_Data_In[3]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1[3]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg[3] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1[3]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2[3]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ), + .I1(gpio_io_t[28]), + .I2(p_73_in), + .I3(gpio_Data_In[3]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2[3]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg[3] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2[3]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1[4]_i_1 + (.I0(gpio_io_o[27]), + .I1(gpio_io_t[27]), + .I2(p_73_in), + .I3(gpio_Data_In[4]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1[4]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg[4] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1[4]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2[4]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ), + .I1(gpio_io_t[27]), + .I2(p_73_in), + .I3(gpio_Data_In[4]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2[4]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg[4] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2[4]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1[5]_i_1 + (.I0(gpio_io_o[26]), + .I1(gpio_io_t[26]), + .I2(p_73_in), + .I3(gpio_Data_In[5]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1[5]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg[5] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1[5]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2[5]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ), + .I1(gpio_io_t[26]), + .I2(p_73_in), + .I3(gpio_Data_In[5]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2[5]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg[5] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2[5]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1[6]_i_1 + (.I0(gpio_io_o[25]), + .I1(gpio_io_t[25]), + .I2(p_73_in), + .I3(gpio_Data_In[6]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1[6]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg[6] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1[6]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2[6]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ), + .I1(gpio_io_t[25]), + .I2(p_73_in), + .I3(gpio_Data_In[6]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2[6]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg[6] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2[6]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1[7]_i_1 + (.I0(gpio_io_o[24]), + .I1(gpio_io_t[24]), + .I2(p_73_in), + .I3(gpio_Data_In[7]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1[7]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg[7] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1[7]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2[7]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ), + .I1(gpio_io_t[24]), + .I2(p_73_in), + .I3(gpio_Data_In[7]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2[7]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg[7] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2[7]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1[8]_i_1 + (.I0(gpio_io_o[23]), + .I1(gpio_io_t[23]), + .I2(p_73_in), + .I3(gpio_Data_In[8]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1[8]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg[8] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1[8]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2[8]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ), + .I1(gpio_io_t[23]), + .I2(p_73_in), + .I3(gpio_Data_In[8]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2[8]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg[8] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2[8]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1[9]_i_1 + (.I0(gpio_io_o[22]), + .I1(gpio_io_t[22]), + .I2(p_73_in), + .I3(gpio_Data_In[9]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1[9]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg[9] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1[9]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ), + .R(bus2ip_rnw_i_reg)); + LUT5 #( + .INIT(32'hFE02C2C2)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2[9]_i_1 + (.I0(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ), + .I1(gpio_io_t[22]), + .I2(p_73_in), + .I3(gpio_Data_In[9]), + .I4(p_75_in), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2[9]_i_1_n_0 )); + FDRE \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg[9] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2[9]_i_1_n_0 ), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ), + .R(bus2ip_rnw_i_reg)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \Not_Dual.INPUT_DOUBLE_REGS3 + (.gpio_io_i(gpio_io_i), + .s_axi_aclk(s_axi_aclk), + .scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4],gpio_io_i_d2[5],gpio_io_i_d2[6],gpio_io_i_d2[7],gpio_io_i_d2[8],gpio_io_i_d2[9],gpio_io_i_d2[10],gpio_io_i_d2[11],gpio_io_i_d2[12],gpio_io_i_d2[13],gpio_io_i_d2[14],gpio_io_i_d2[15],gpio_io_i_d2[16],gpio_io_i_d2[17],gpio_io_i_d2[18],gpio_io_i_d2[19],gpio_io_i_d2[20],gpio_io_i_d2[21],gpio_io_i_d2[22],gpio_io_i_d2[23],gpio_io_i_d2[24],gpio_io_i_d2[25],gpio_io_i_d2[26],gpio_io_i_d2[27],gpio_io_i_d2[28],gpio_io_i_d2[29],gpio_io_i_d2[30],gpio_io_i_d2[31]})); + FDRE \Not_Dual.gpio_Data_In_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[0]), + .Q(gpio_Data_In[0]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[10] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[10]), + .Q(gpio_Data_In[10]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[11] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[11]), + .Q(gpio_Data_In[11]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[12] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[12]), + .Q(gpio_Data_In[12]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[13] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[13]), + .Q(gpio_Data_In[13]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[14] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[14]), + .Q(gpio_Data_In[14]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[15] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[15]), + .Q(gpio_Data_In[15]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[16] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[16]), + .Q(gpio_Data_In[16]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[17] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[17]), + .Q(gpio_Data_In[17]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[18] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[18]), + .Q(gpio_Data_In[18]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[19] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[19]), + .Q(gpio_Data_In[19]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[1]), + .Q(gpio_Data_In[1]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[20] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[20]), + .Q(gpio_Data_In[20]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[21] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[21]), + .Q(gpio_Data_In[21]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[22] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[22]), + .Q(gpio_Data_In[22]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[23] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[23]), + .Q(gpio_Data_In[23]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[24] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[24]), + .Q(gpio_Data_In[24]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[25] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[25]), + .Q(gpio_Data_In[25]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[26] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[26]), + .Q(gpio_Data_In[26]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[27] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[27]), + .Q(gpio_Data_In[27]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[28] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[28]), + .Q(gpio_Data_In[28]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[29] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[29]), + .Q(gpio_Data_In[29]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[2] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[2]), + .Q(gpio_Data_In[2]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[30] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[30]), + .Q(gpio_Data_In[30]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[31] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[31]), + .Q(gpio_Data_In[31]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[3] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[3]), + .Q(gpio_Data_In[3]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[4] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[4]), + .Q(gpio_Data_In[4]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[5] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[5]), + .Q(gpio_Data_In[5]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[6] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[6]), + .Q(gpio_Data_In[6]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[7] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[7]), + .Q(gpio_Data_In[7]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[8] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[8]), + .Q(gpio_Data_In[8]), + .R(1'b0)); + FDRE \Not_Dual.gpio_Data_In_reg[9] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2[9]), + .Q(gpio_Data_In[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[0] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[31]), + .Q(gpio_io_o[31]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[10] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[21]), + .Q(gpio_io_o[21]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[11] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[20]), + .Q(gpio_io_o[20]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[12] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[19]), + .Q(gpio_io_o[19]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[13] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[18]), + .Q(gpio_io_o[18]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[14] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[17]), + .Q(gpio_io_o[17]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[15] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[16]), + .Q(gpio_io_o[16]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[16] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[15]), + .Q(gpio_io_o[15]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[17] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[14]), + .Q(gpio_io_o[14]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[18] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[13]), + .Q(gpio_io_o[13]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[19] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[12]), + .Q(gpio_io_o[12]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[1] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[30]), + .Q(gpio_io_o[30]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[20] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[11]), + .Q(gpio_io_o[11]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[21] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[10]), + .Q(gpio_io_o[10]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[22] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[9]), + .Q(gpio_io_o[9]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[23] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[8]), + .Q(gpio_io_o[8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[24] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[7]), + .Q(gpio_io_o[7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[25] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[6]), + .Q(gpio_io_o[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[26] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[5]), + .Q(gpio_io_o[5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[27] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[4]), + .Q(gpio_io_o[4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[28] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[3]), + .Q(gpio_io_o[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[29] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[2]), + .Q(gpio_io_o[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[2] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[29]), + .Q(gpio_io_o[29]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[30] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[1]), + .Q(gpio_io_o[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[31] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[0]), + .Q(gpio_io_o[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[3] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[28]), + .Q(gpio_io_o[28]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[4] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[27]), + .Q(gpio_io_o[27]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[5] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[26]), + .Q(gpio_io_o[26]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[6] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[25]), + .Q(gpio_io_o[25]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[7] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[24]), + .Q(gpio_io_o[24]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[8] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[23]), + .Q(gpio_io_o[23]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \Not_Dual.gpio_Data_Out_reg[9] + (.C(s_axi_aclk), + .CE(bus2ip_rnw_i_reg_0), + .D(s_axi_wdata[22]), + .Q(gpio_io_o[22]), + .R(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[0] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[31]), + .Q(gpio_io_t[31]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[10] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[21]), + .Q(gpio_io_t[21]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[11] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[20]), + .Q(gpio_io_t[20]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[12] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[19]), + .Q(gpio_io_t[19]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[13] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[18]), + .Q(gpio_io_t[18]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[14] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[17]), + .Q(gpio_io_t[17]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[15] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[16]), + .Q(gpio_io_t[16]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[16] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[15]), + .Q(gpio_io_t[15]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[17] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[14]), + .Q(gpio_io_t[14]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[18] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[13]), + .Q(gpio_io_t[13]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[19] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[12]), + .Q(gpio_io_t[12]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[1] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[30]), + .Q(gpio_io_t[30]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[20] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[11]), + .Q(gpio_io_t[11]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[21] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[10]), + .Q(gpio_io_t[10]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[22] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[9]), + .Q(gpio_io_t[9]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[23] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[8]), + .Q(gpio_io_t[8]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[24] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[7]), + .Q(gpio_io_t[7]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[25] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[6]), + .Q(gpio_io_t[6]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[26] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[5]), + .Q(gpio_io_t[5]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[27] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[4]), + .Q(gpio_io_t[4]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[28] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[3]), + .Q(gpio_io_t[3]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[29] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[2]), + .Q(gpio_io_t[2]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[2] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[29]), + .Q(gpio_io_t[29]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[30] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[1]), + .Q(gpio_io_t[1]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[31] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[0]), + .Q(gpio_io_t[0]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[3] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[28]), + .Q(gpio_io_t[28]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[4] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[27]), + .Q(gpio_io_t[27]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[5] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[26]), + .Q(gpio_io_t[26]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[6] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[25]), + .Q(gpio_io_t[25]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[7] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[24]), + .Q(gpio_io_t[24]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[8] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[23]), + .Q(gpio_io_t[23]), + .S(SR)); + FDSE #( + .INIT(1'b1)) + \Not_Dual.gpio_OE_reg[9] + (.C(s_axi_aclk), + .CE(E), + .D(s_axi_wdata[22]), + .Q(gpio_io_t[22]), + .S(SR)); + FDRE gpio_xferAck_Reg_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(GPIO_xferAck_i), + .Q(gpio_xferAck_Reg), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h04)) + iGPIO_xferAck_i_1 + (.I0(gpio_xferAck_Reg), + .I1(bus2ip_cs), + .I2(GPIO_xferAck_i), + .O(iGPIO_xferAck)); + FDRE iGPIO_xferAck_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(iGPIO_xferAck), + .Q(GPIO_xferAck_i), + .R(SR)); + LUT2 #( + .INIT(4'h8)) + ip2bus_rdack_i_D1_i_1 + (.I0(GPIO_xferAck_i), + .I1(bus2ip_rnw), + .O(ip2bus_rdack_i)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h2)) + ip2bus_wrack_i_D1_i_1 + (.I0(GPIO_xferAck_i), + .I1(bus2ip_rnw), + .O(ip2bus_wrack_i)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder + (\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 , + p_75_in, + p_73_in, + E, + \Not_Dual.gpio_Data_Out_reg[0] , + s_axi_arready, + s_axi_wready, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] , + D, + Q, + s_axi_aclk, + \bus2ip_addr_i_reg[8] , + bus2ip_rnw_i_reg, + s_axi_aresetn, + GPIO_xferAck_i, + gpio_xferAck_Reg, + ip2bus_rdack_i_D1, + is_read_reg, + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] , + ip2bus_wrack_i_D1, + is_write_reg, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ); + output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ; + output p_75_in; + output p_73_in; + output [0:0]E; + output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; + output s_axi_arready; + output s_axi_wready; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] ; + output [31:0]D; + input Q; + input s_axi_aclk; + input [2:0]\bus2ip_addr_i_reg[8] ; + input bus2ip_rnw_i_reg; + input s_axi_aresetn; + input GPIO_xferAck_i; + input gpio_xferAck_Reg; + input ip2bus_rdack_i_D1; + input is_read_reg; + input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ; + input ip2bus_wrack_i_D1; + input is_write_reg; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ; + + wire Bus_RNW_reg; + wire Bus_RNW_reg_i_1_n_0; + wire [31:0]D; + wire [0:0]E; + wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ; + wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ; + wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ; + wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ; + wire GPIO_xferAck_i; + wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ; + wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ; + wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ; + wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; + wire Q; + wire [2:0]\bus2ip_addr_i_reg[8] ; + wire bus2ip_rnw_i_reg; + wire ce_expnd_i_0; + wire ce_expnd_i_1; + wire ce_expnd_i_2; + wire ce_expnd_i_3; + wire cs_ce_clr; + wire gpio_xferAck_Reg; + wire \ip2bus_data_i_D1[0]_i_2_n_0 ; + wire \ip2bus_data_i_D1[0]_i_3_n_0 ; + wire \ip2bus_data_i_D1[0]_i_4_n_0 ; + wire ip2bus_rdack_i_D1; + wire ip2bus_wrack_i_D1; + wire is_read_reg; + wire is_write_reg; + wire p_73_in; + wire p_75_in; + wire s_axi_aclk; + wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_wready; + + LUT3 #( + .INIT(8'hB8)) + Bus_RNW_reg_i_1 + (.I0(bus2ip_rnw_i_reg), + .I1(Q), + .I2(Bus_RNW_reg), + .O(Bus_RNW_reg_i_1_n_0)); + FDRE Bus_RNW_reg_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(Bus_RNW_reg_i_1_n_0), + .Q(Bus_RNW_reg), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h1)) + \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1 + (.I0(\bus2ip_addr_i_reg[8] [0]), + .I1(\bus2ip_addr_i_reg[8] [1]), + .O(ce_expnd_i_3)); + FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] + (.C(s_axi_aclk), + .CE(Q), + .D(ce_expnd_i_3), + .Q(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ), + .R(cs_ce_clr)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1 + (.I0(\bus2ip_addr_i_reg[8] [0]), + .I1(\bus2ip_addr_i_reg[8] [1]), + .O(ce_expnd_i_2)); + FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] + (.C(s_axi_aclk), + .CE(Q), + .D(ce_expnd_i_2), + .Q(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), + .R(cs_ce_clr)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h2)) + \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1 + (.I0(\bus2ip_addr_i_reg[8] [1]), + .I1(\bus2ip_addr_i_reg[8] [0]), + .O(ce_expnd_i_1)); + FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] + (.C(s_axi_aclk), + .CE(Q), + .D(ce_expnd_i_1), + .Q(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ), + .R(cs_ce_clr)); + LUT3 #( + .INIT(8'hEF)) + \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1 + (.I0(s_axi_wready), + .I1(s_axi_arready), + .I2(s_axi_aresetn), + .O(cs_ce_clr)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h8)) + \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2 + (.I0(\bus2ip_addr_i_reg[8] [1]), + .I1(\bus2ip_addr_i_reg[8] [0]), + .O(ce_expnd_i_0)); + FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] + (.C(s_axi_aclk), + .CE(Q), + .D(ce_expnd_i_0), + .Q(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ), + .R(cs_ce_clr)); + LUT5 #( + .INIT(32'h000000E0)) + \MEM_DECODE_GEN[0].cs_out_i[0]_i_1 + (.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I1(Q), + .I2(s_axi_aresetn), + .I3(s_axi_arready), + .I4(s_axi_wready), + .O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 )); + FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ), + .Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .R(1'b0)); + LUT4 #( + .INIT(16'hFDFF)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_1 + (.I0(bus2ip_rnw_i_reg), + .I1(GPIO_xferAck_i), + .I2(gpio_xferAck_Reg), + .I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .O(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h0400)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_3 + (.I0(\bus2ip_addr_i_reg[8] [2]), + .I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I2(\bus2ip_addr_i_reg[8] [1]), + .I3(\bus2ip_addr_i_reg[8] [0]), + .O(p_73_in)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h0004)) + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_4 + (.I0(\bus2ip_addr_i_reg[8] [2]), + .I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I2(\bus2ip_addr_i_reg[8] [0]), + .I3(\bus2ip_addr_i_reg[8] [1]), + .O(p_75_in)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00000010)) + \Not_Dual.gpio_Data_Out[0]_i_1 + (.I0(bus2ip_rnw_i_reg), + .I1(\bus2ip_addr_i_reg[8] [2]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(\bus2ip_addr_i_reg[8] [0]), + .I4(\bus2ip_addr_i_reg[8] [1]), + .O(\Not_Dual.gpio_Data_Out_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00100000)) + \Not_Dual.gpio_OE[0]_i_1 + (.I0(bus2ip_rnw_i_reg), + .I1(\bus2ip_addr_i_reg[8] [2]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(\bus2ip_addr_i_reg[8] [1]), + .I4(\bus2ip_addr_i_reg[8] [0]), + .O(E)); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[0]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[31])); + LUT5 #( + .INIT(32'h00000400)) + \ip2bus_data_i_D1[0]_i_2 + (.I0(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), + .I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ), + .I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ), + .I3(Bus_RNW_reg), + .I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ), + .O(\ip2bus_data_i_D1[0]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00040000)) + \ip2bus_data_i_D1[0]_i_3 + (.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ), + .I1(Bus_RNW_reg), + .I2(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ), + .I3(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), + .I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ), + .O(\ip2bus_data_i_D1[0]_i_3_n_0 )); + LUT5 #( + .INIT(32'h00000400)) + \ip2bus_data_i_D1[0]_i_4 + (.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ), + .I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ), + .I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ), + .I3(Bus_RNW_reg), + .I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ), + .O(\ip2bus_data_i_D1[0]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[10]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[21])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[11]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[20])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[12]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[19])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[13]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[18])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[14]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[17])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[15]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[16])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[16]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[15])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[17]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[14])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[18]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[13])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[19]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[12])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[1]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[30])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[20]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[11])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[21]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[10])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[22]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[9])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[23]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[8])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[24]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[7])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[25]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[6])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[26]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[5])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[27]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[4])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[28]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[3])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[29]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[2])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[2]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[29])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[30]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[1])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[31]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[0])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[3]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[28])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[4]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[27])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[5]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[26])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[6]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[25])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[7]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[24])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[8]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[23])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \ip2bus_data_i_D1[9]_i_1 + (.I0(\ip2bus_data_i_D1[0]_i_2_n_0 ), + .I1(\ip2bus_data_i_D1[0]_i_3_n_0 ), + .I2(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ), + .I3(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ), + .I4(\ip2bus_data_i_D1[0]_i_4_n_0 ), + .O(D[22])); + LUT6 #( + .INIT(64'hAAAAAAAAAAAEAAAA)) + s_axi_arready_INST_0 + (.I0(ip2bus_rdack_i_D1), + .I1(is_read_reg), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]), + .I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]), + .O(s_axi_arready)); + LUT6 #( + .INIT(64'hAAAAAAAAAAAEAAAA)) + s_axi_wready_INST_0 + (.I0(ip2bus_wrack_i_D1), + .I1(is_write_reg), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]), + .I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]), + .O(s_axi_wready)); +endmodule + +(* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "0" *) (* C_ALL_OUTPUTS = "0" *) +(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *) +(* C_FAMILY = "kintex7" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "32" *) +(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *) +(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *) +(* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio + (s_axi_aclk, + s_axi_aresetn, + s_axi_awaddr, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready, + ip2intc_irpt, + gpio_io_i, + gpio_io_o, + gpio_io_t, + gpio2_io_i, + gpio2_io_o, + gpio2_io_t); + (* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk; + (* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn; + input [8:0]s_axi_awaddr; + input s_axi_awvalid; + output s_axi_awready; + input [31:0]s_axi_wdata; + input [3:0]s_axi_wstrb; + input s_axi_wvalid; + output s_axi_wready; + output [1:0]s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + input [8:0]s_axi_araddr; + input s_axi_arvalid; + output s_axi_arready; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rvalid; + input s_axi_rready; + (* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt; + input [31:0]gpio_io_i; + output [31:0]gpio_io_o; + output [31:0]gpio_io_t; + input [31:0]gpio2_io_i; + output [31:0]gpio2_io_o; + output [31:0]gpio2_io_t; + + wire \ ; + wire \ ; + wire AXI_LITE_IPIF_I_n_11; + wire AXI_LITE_IPIF_I_n_7; + wire AXI_LITE_IPIF_I_n_8; + wire GPIO_xferAck_i; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ; + wire bus2ip_cs; + wire bus2ip_reset; + wire bus2ip_rnw; + wire [31:0]gpio_io_i; + wire [31:0]gpio_io_o; + wire [31:0]gpio_io_t; + wire gpio_xferAck_Reg; + wire [0:31]ip2bus_data; + wire [0:31]ip2bus_data_i_D1; + wire ip2bus_rdack_i; + wire ip2bus_rdack_i_D1; + wire ip2bus_wrack_i; + wire ip2bus_wrack_i_D1; + wire p_73_in; + wire p_75_in; + (* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk; + wire [8:0]s_axi_araddr; + (* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [8:0]s_axi_awaddr; + wire s_axi_awvalid; + wire s_axi_bready; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire s_axi_wready; + wire s_axi_wvalid; + + assign gpio2_io_o[31] = \ ; + assign gpio2_io_o[30] = \ ; + assign gpio2_io_o[29] = \ ; + assign gpio2_io_o[28] = \ ; + assign gpio2_io_o[27] = \ ; + assign gpio2_io_o[26] = \ ; + assign gpio2_io_o[25] = \ ; + assign gpio2_io_o[24] = \ ; + assign gpio2_io_o[23] = \ ; + assign gpio2_io_o[22] = \ ; + assign gpio2_io_o[21] = \ ; + assign gpio2_io_o[20] = \ ; + assign gpio2_io_o[19] = \ ; + assign gpio2_io_o[18] = \ ; + assign gpio2_io_o[17] = \ ; + assign gpio2_io_o[16] = \ ; + assign gpio2_io_o[15] = \ ; + assign gpio2_io_o[14] = \ ; + assign gpio2_io_o[13] = \ ; + assign gpio2_io_o[12] = \ ; + assign gpio2_io_o[11] = \ ; + assign gpio2_io_o[10] = \ ; + assign gpio2_io_o[9] = \ ; + assign gpio2_io_o[8] = \ ; + assign gpio2_io_o[7] = \ ; + assign gpio2_io_o[6] = \ ; + assign gpio2_io_o[5] = \ ; + assign gpio2_io_o[4] = \ ; + assign gpio2_io_o[3] = \ ; + assign gpio2_io_o[2] = \ ; + assign gpio2_io_o[1] = \ ; + assign gpio2_io_o[0] = \ ; + assign gpio2_io_t[31] = \ ; + assign gpio2_io_t[30] = \ ; + assign gpio2_io_t[29] = \ ; + assign gpio2_io_t[28] = \ ; + assign gpio2_io_t[27] = \ ; + assign gpio2_io_t[26] = \ ; + assign gpio2_io_t[25] = \ ; + assign gpio2_io_t[24] = \ ; + assign gpio2_io_t[23] = \ ; + assign gpio2_io_t[22] = \ ; + assign gpio2_io_t[21] = \ ; + assign gpio2_io_t[20] = \ ; + assign gpio2_io_t[19] = \ ; + assign gpio2_io_t[18] = \ ; + assign gpio2_io_t[17] = \ ; + assign gpio2_io_t[16] = \ ; + assign gpio2_io_t[15] = \ ; + assign gpio2_io_t[14] = \ ; + assign gpio2_io_t[13] = \ ; + assign gpio2_io_t[12] = \ ; + assign gpio2_io_t[11] = \ ; + assign gpio2_io_t[10] = \ ; + assign gpio2_io_t[9] = \ ; + assign gpio2_io_t[8] = \ ; + assign gpio2_io_t[7] = \ ; + assign gpio2_io_t[6] = \ ; + assign gpio2_io_t[5] = \ ; + assign gpio2_io_t[4] = \ ; + assign gpio2_io_t[3] = \ ; + assign gpio2_io_t[2] = \ ; + assign gpio2_io_t[1] = \ ; + assign gpio2_io_t[0] = \ ; + assign ip2intc_irpt = \ ; + assign s_axi_awready = s_axi_wready; + assign s_axi_bresp[1] = \ ; + assign s_axi_bresp[0] = \ ; + assign s_axi_rresp[1] = \ ; + assign s_axi_rresp[0] = \ ; + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I + (.D({ip2bus_data[0],ip2bus_data[1],ip2bus_data[2],ip2bus_data[3],ip2bus_data[4],ip2bus_data[5],ip2bus_data[6],ip2bus_data[7],ip2bus_data[8],ip2bus_data[9],ip2bus_data[10],ip2bus_data[11],ip2bus_data[12],ip2bus_data[13],ip2bus_data[14],ip2bus_data[15],ip2bus_data[16],ip2bus_data[17],ip2bus_data[18],ip2bus_data[19],ip2bus_data[20],ip2bus_data[21],ip2bus_data[22],ip2bus_data[23],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}), + .E(AXI_LITE_IPIF_I_n_7), + .GPIO_xferAck_i(GPIO_xferAck_i), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] (AXI_LITE_IPIF_I_n_11), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ), + .\Not_Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_8), + .Q({ip2bus_data_i_D1[0],ip2bus_data_i_D1[1],ip2bus_data_i_D1[2],ip2bus_data_i_D1[3],ip2bus_data_i_D1[4],ip2bus_data_i_D1[5],ip2bus_data_i_D1[6],ip2bus_data_i_D1[7],ip2bus_data_i_D1[8],ip2bus_data_i_D1[9],ip2bus_data_i_D1[10],ip2bus_data_i_D1[11],ip2bus_data_i_D1[12],ip2bus_data_i_D1[13],ip2bus_data_i_D1[14],ip2bus_data_i_D1[15],ip2bus_data_i_D1[16],ip2bus_data_i_D1[17],ip2bus_data_i_D1[18],ip2bus_data_i_D1[19],ip2bus_data_i_D1[20],ip2bus_data_i_D1[21],ip2bus_data_i_D1[22],ip2bus_data_i_D1[23],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}), + .bus2ip_cs(bus2ip_cs), + .bus2ip_reset(bus2ip_reset), + .bus2ip_rnw(bus2ip_rnw), + .gpio_xferAck_Reg(gpio_xferAck_Reg), + .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), + .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), + .p_73_in(p_73_in), + .p_75_in(p_75_in), + .s_axi_aclk(s_axi_aclk), + .s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid)); + GND GND + (.G(\ )); + VCC VCC + (.P(\ )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1 + (.E(AXI_LITE_IPIF_I_n_7), + .GPIO_xferAck_i(GPIO_xferAck_i), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ), + .SR(bus2ip_reset), + .bus2ip_cs(bus2ip_cs), + .bus2ip_rnw(bus2ip_rnw), + .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_11), + .bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_8), + .gpio_io_i(gpio_io_i), + .gpio_io_o(gpio_io_o), + .gpio_io_t(gpio_io_t), + .gpio_xferAck_Reg(gpio_xferAck_Reg), + .ip2bus_rdack_i(ip2bus_rdack_i), + .ip2bus_wrack_i(ip2bus_wrack_i), + .p_73_in(p_73_in), + .p_75_in(p_75_in), + .s_axi_aclk(s_axi_aclk), + .s_axi_wdata(s_axi_wdata)); + FDRE \ip2bus_data_i_D1_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[0]), + .Q(ip2bus_data_i_D1[0]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[10] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[10]), + .Q(ip2bus_data_i_D1[10]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[11] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[11]), + .Q(ip2bus_data_i_D1[11]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[12] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[12]), + .Q(ip2bus_data_i_D1[12]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[13] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[13]), + .Q(ip2bus_data_i_D1[13]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[14] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[14]), + .Q(ip2bus_data_i_D1[14]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[15] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[15]), + .Q(ip2bus_data_i_D1[15]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[16] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[16]), + .Q(ip2bus_data_i_D1[16]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[17] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[17]), + .Q(ip2bus_data_i_D1[17]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[18] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[18]), + .Q(ip2bus_data_i_D1[18]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[19] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[19]), + .Q(ip2bus_data_i_D1[19]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[1]), + .Q(ip2bus_data_i_D1[1]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[20] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[20]), + .Q(ip2bus_data_i_D1[20]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[21] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[21]), + .Q(ip2bus_data_i_D1[21]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[22] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[22]), + .Q(ip2bus_data_i_D1[22]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[23] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[23]), + .Q(ip2bus_data_i_D1[23]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[24] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[24]), + .Q(ip2bus_data_i_D1[24]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[25] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[25]), + .Q(ip2bus_data_i_D1[25]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[26] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[26]), + .Q(ip2bus_data_i_D1[26]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[27] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[27]), + .Q(ip2bus_data_i_D1[27]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[28] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[28]), + .Q(ip2bus_data_i_D1[28]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[29] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[29]), + .Q(ip2bus_data_i_D1[29]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[2] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[2]), + .Q(ip2bus_data_i_D1[2]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[30] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[30]), + .Q(ip2bus_data_i_D1[30]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[31] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[31]), + .Q(ip2bus_data_i_D1[31]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[3] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[3]), + .Q(ip2bus_data_i_D1[3]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[4] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[4]), + .Q(ip2bus_data_i_D1[4]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[5] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[5]), + .Q(ip2bus_data_i_D1[5]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[6] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[6]), + .Q(ip2bus_data_i_D1[6]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[7] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[7]), + .Q(ip2bus_data_i_D1[7]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[8] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[8]), + .Q(ip2bus_data_i_D1[8]), + .R(bus2ip_reset)); + FDRE \ip2bus_data_i_D1_reg[9] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data[9]), + .Q(ip2bus_data_i_D1[9]), + .R(bus2ip_reset)); + FDRE ip2bus_rdack_i_D1_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_rdack_i), + .Q(ip2bus_rdack_i_D1), + .R(bus2ip_reset)); + FDRE ip2bus_wrack_i_D1_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_wrack_i), + .Q(ip2bus_wrack_i_D1), + .R(bus2ip_reset)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif + (bus2ip_reset, + bus2ip_rnw, + s_axi_rvalid, + s_axi_bvalid, + bus2ip_cs, + p_75_in, + p_73_in, + E, + \Not_Dual.gpio_Data_Out_reg[0] , + s_axi_arready, + s_axi_wready, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] , + s_axi_rdata, + D, + s_axi_aclk, + s_axi_arvalid, + s_axi_rready, + s_axi_bready, + s_axi_aresetn, + s_axi_awvalid, + s_axi_wvalid, + GPIO_xferAck_i, + gpio_xferAck_Reg, + Q, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg , + ip2bus_rdack_i_D1, + ip2bus_wrack_i_D1, + s_axi_araddr, + s_axi_awaddr); + output bus2ip_reset; + output bus2ip_rnw; + output s_axi_rvalid; + output s_axi_bvalid; + output bus2ip_cs; + output p_75_in; + output p_73_in; + output [0:0]E; + output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; + output s_axi_arready; + output s_axi_wready; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] ; + output [31:0]s_axi_rdata; + output [31:0]D; + input s_axi_aclk; + input s_axi_arvalid; + input s_axi_rready; + input s_axi_bready; + input s_axi_aresetn; + input s_axi_awvalid; + input s_axi_wvalid; + input GPIO_xferAck_i; + input gpio_xferAck_Reg; + input [31:0]Q; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ; + input ip2bus_rdack_i_D1; + input ip2bus_wrack_i_D1; + input [2:0]s_axi_araddr; + input [2:0]s_axi_awaddr; + + wire [31:0]D; + wire [0:0]E; + wire GPIO_xferAck_i; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ; + wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; + wire [31:0]Q; + wire bus2ip_cs; + wire bus2ip_reset; + wire bus2ip_rnw; + wire gpio_xferAck_Reg; + wire ip2bus_rdack_i_D1; + wire ip2bus_wrack_i_D1; + wire p_73_in; + wire p_75_in; + wire s_axi_aclk; + wire [2:0]s_axi_araddr; + wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [2:0]s_axi_awaddr; + wire s_axi_awvalid; + wire s_axi_bready; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + wire s_axi_rvalid; + wire s_axi_wready; + wire s_axi_wvalid; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT + (.D(D), + .E(E), + .GPIO_xferAck_i(GPIO_xferAck_i), + .\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] (bus2ip_rnw), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]_0 (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ), + .\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ), + .Q(Q), + .SR(bus2ip_reset), + .gpio_xferAck_Reg(gpio_xferAck_Reg), + .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), + .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), + .p_73_in(p_73_in), + .p_75_in(p_75_in), + .s_axi_aclk(s_axi_aclk), + .s_axi_araddr(s_axi_araddr), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync + (scndry_vect_out, + gpio_io_i, + s_axi_aclk); + output [31:0]scndry_vect_out; + input [31:0]gpio_io_i; + input s_axi_aclk; + + wire [31:0]gpio_io_i; + wire s_axi_aclk; + wire s_level_out_bus_d1_cdc_to_0; + wire s_level_out_bus_d1_cdc_to_1; + wire s_level_out_bus_d1_cdc_to_10; + wire s_level_out_bus_d1_cdc_to_11; + wire s_level_out_bus_d1_cdc_to_12; + wire s_level_out_bus_d1_cdc_to_13; + wire s_level_out_bus_d1_cdc_to_14; + wire s_level_out_bus_d1_cdc_to_15; + wire s_level_out_bus_d1_cdc_to_16; + wire s_level_out_bus_d1_cdc_to_17; + wire s_level_out_bus_d1_cdc_to_18; + wire s_level_out_bus_d1_cdc_to_19; + wire s_level_out_bus_d1_cdc_to_2; + wire s_level_out_bus_d1_cdc_to_20; + wire s_level_out_bus_d1_cdc_to_21; + wire s_level_out_bus_d1_cdc_to_22; + wire s_level_out_bus_d1_cdc_to_23; + wire s_level_out_bus_d1_cdc_to_24; + wire s_level_out_bus_d1_cdc_to_25; + wire s_level_out_bus_d1_cdc_to_26; + wire s_level_out_bus_d1_cdc_to_27; + wire s_level_out_bus_d1_cdc_to_28; + wire s_level_out_bus_d1_cdc_to_29; + wire s_level_out_bus_d1_cdc_to_3; + wire s_level_out_bus_d1_cdc_to_30; + wire s_level_out_bus_d1_cdc_to_31; + wire s_level_out_bus_d1_cdc_to_4; + wire s_level_out_bus_d1_cdc_to_5; + wire s_level_out_bus_d1_cdc_to_6; + wire s_level_out_bus_d1_cdc_to_7; + wire s_level_out_bus_d1_cdc_to_8; + wire s_level_out_bus_d1_cdc_to_9; + wire s_level_out_bus_d2_0; + wire s_level_out_bus_d2_1; + wire s_level_out_bus_d2_10; + wire s_level_out_bus_d2_11; + wire s_level_out_bus_d2_12; + wire s_level_out_bus_d2_13; + wire s_level_out_bus_d2_14; + wire s_level_out_bus_d2_15; + wire s_level_out_bus_d2_16; + wire s_level_out_bus_d2_17; + wire s_level_out_bus_d2_18; + wire s_level_out_bus_d2_19; + wire s_level_out_bus_d2_2; + wire s_level_out_bus_d2_20; + wire s_level_out_bus_d2_21; + wire s_level_out_bus_d2_22; + wire s_level_out_bus_d2_23; + wire s_level_out_bus_d2_24; + wire s_level_out_bus_d2_25; + wire s_level_out_bus_d2_26; + wire s_level_out_bus_d2_27; + wire s_level_out_bus_d2_28; + wire s_level_out_bus_d2_29; + wire s_level_out_bus_d2_3; + wire s_level_out_bus_d2_30; + wire s_level_out_bus_d2_31; + wire s_level_out_bus_d2_4; + wire s_level_out_bus_d2_5; + wire s_level_out_bus_d2_6; + wire s_level_out_bus_d2_7; + wire s_level_out_bus_d2_8; + wire s_level_out_bus_d2_9; + wire s_level_out_bus_d3_0; + wire s_level_out_bus_d3_1; + wire s_level_out_bus_d3_10; + wire s_level_out_bus_d3_11; + wire s_level_out_bus_d3_12; + wire s_level_out_bus_d3_13; + wire s_level_out_bus_d3_14; + wire s_level_out_bus_d3_15; + wire s_level_out_bus_d3_16; + wire s_level_out_bus_d3_17; + wire s_level_out_bus_d3_18; + wire s_level_out_bus_d3_19; + wire s_level_out_bus_d3_2; + wire s_level_out_bus_d3_20; + wire s_level_out_bus_d3_21; + wire s_level_out_bus_d3_22; + wire s_level_out_bus_d3_23; + wire s_level_out_bus_d3_24; + wire s_level_out_bus_d3_25; + wire s_level_out_bus_d3_26; + wire s_level_out_bus_d3_27; + wire s_level_out_bus_d3_28; + wire s_level_out_bus_d3_29; + wire s_level_out_bus_d3_3; + wire s_level_out_bus_d3_30; + wire s_level_out_bus_d3_31; + wire s_level_out_bus_d3_4; + wire s_level_out_bus_d3_5; + wire s_level_out_bus_d3_6; + wire s_level_out_bus_d3_7; + wire s_level_out_bus_d3_8; + wire s_level_out_bus_d3_9; + wire [31:0]scndry_vect_out; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_0), + .Q(s_level_out_bus_d2_0), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_10), + .Q(s_level_out_bus_d2_10), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_11), + .Q(s_level_out_bus_d2_11), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_12), + .Q(s_level_out_bus_d2_12), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_13), + .Q(s_level_out_bus_d2_13), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_14), + .Q(s_level_out_bus_d2_14), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_15), + .Q(s_level_out_bus_d2_15), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_16), + .Q(s_level_out_bus_d2_16), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_17), + .Q(s_level_out_bus_d2_17), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_18), + .Q(s_level_out_bus_d2_18), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_19), + .Q(s_level_out_bus_d2_19), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_1), + .Q(s_level_out_bus_d2_1), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_20), + .Q(s_level_out_bus_d2_20), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_21), + .Q(s_level_out_bus_d2_21), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_22), + .Q(s_level_out_bus_d2_22), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_23), + .Q(s_level_out_bus_d2_23), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_24), + .Q(s_level_out_bus_d2_24), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_25), + .Q(s_level_out_bus_d2_25), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_26), + .Q(s_level_out_bus_d2_26), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_27), + .Q(s_level_out_bus_d2_27), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_28), + .Q(s_level_out_bus_d2_28), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_29), + .Q(s_level_out_bus_d2_29), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_2), + .Q(s_level_out_bus_d2_2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_30), + .Q(s_level_out_bus_d2_30), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_31), + .Q(s_level_out_bus_d2_31), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_3), + .Q(s_level_out_bus_d2_3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_4), + .Q(s_level_out_bus_d2_4), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_5), + .Q(s_level_out_bus_d2_5), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_6), + .Q(s_level_out_bus_d2_6), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_7), + .Q(s_level_out_bus_d2_7), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_8), + .Q(s_level_out_bus_d2_8), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d1_cdc_to_9), + .Q(s_level_out_bus_d2_9), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_0), + .Q(s_level_out_bus_d3_0), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_10), + .Q(s_level_out_bus_d3_10), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_11), + .Q(s_level_out_bus_d3_11), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_12), + .Q(s_level_out_bus_d3_12), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_13), + .Q(s_level_out_bus_d3_13), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_14), + .Q(s_level_out_bus_d3_14), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_15), + .Q(s_level_out_bus_d3_15), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_16), + .Q(s_level_out_bus_d3_16), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_17), + .Q(s_level_out_bus_d3_17), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_18), + .Q(s_level_out_bus_d3_18), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_19), + .Q(s_level_out_bus_d3_19), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_1), + .Q(s_level_out_bus_d3_1), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_20), + .Q(s_level_out_bus_d3_20), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_21), + .Q(s_level_out_bus_d3_21), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_22), + .Q(s_level_out_bus_d3_22), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_23), + .Q(s_level_out_bus_d3_23), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_24), + .Q(s_level_out_bus_d3_24), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_25), + .Q(s_level_out_bus_d3_25), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_26), + .Q(s_level_out_bus_d3_26), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_27), + .Q(s_level_out_bus_d3_27), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_28), + .Q(s_level_out_bus_d3_28), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_29), + .Q(s_level_out_bus_d3_29), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_2), + .Q(s_level_out_bus_d3_2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_30), + .Q(s_level_out_bus_d3_30), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_31), + .Q(s_level_out_bus_d3_31), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_3), + .Q(s_level_out_bus_d3_3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_4), + .Q(s_level_out_bus_d3_4), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_5), + .Q(s_level_out_bus_d3_5), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_6), + .Q(s_level_out_bus_d3_6), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_7), + .Q(s_level_out_bus_d3_7), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_8), + .Q(s_level_out_bus_d3_8), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d2_9), + .Q(s_level_out_bus_d3_9), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_0), + .Q(scndry_vect_out[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_10), + .Q(scndry_vect_out[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_11), + .Q(scndry_vect_out[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_12), + .Q(scndry_vect_out[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_13), + .Q(scndry_vect_out[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_14), + .Q(scndry_vect_out[14]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_15), + .Q(scndry_vect_out[15]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_16), + .Q(scndry_vect_out[16]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_17), + .Q(scndry_vect_out[17]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_18), + .Q(scndry_vect_out[18]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_19), + .Q(scndry_vect_out[19]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_1), + .Q(scndry_vect_out[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_20), + .Q(scndry_vect_out[20]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_21), + .Q(scndry_vect_out[21]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_22), + .Q(scndry_vect_out[22]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_23), + .Q(scndry_vect_out[23]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_24), + .Q(scndry_vect_out[24]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_25), + .Q(scndry_vect_out[25]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_26), + .Q(scndry_vect_out[26]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_27), + .Q(scndry_vect_out[27]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_28), + .Q(scndry_vect_out[28]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_29), + .Q(scndry_vect_out[29]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_2), + .Q(scndry_vect_out[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_30), + .Q(scndry_vect_out[30]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_31), + .Q(scndry_vect_out[31]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_3), + .Q(scndry_vect_out[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_4), + .Q(scndry_vect_out[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_5), + .Q(scndry_vect_out[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_6), + .Q(scndry_vect_out[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_7), + .Q(scndry_vect_out[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_8), + .Q(scndry_vect_out[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_level_out_bus_d3_9), + .Q(scndry_vect_out[9]), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[0]), + .Q(s_level_out_bus_d1_cdc_to_0), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[10]), + .Q(s_level_out_bus_d1_cdc_to_10), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[11]), + .Q(s_level_out_bus_d1_cdc_to_11), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[12]), + .Q(s_level_out_bus_d1_cdc_to_12), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[13]), + .Q(s_level_out_bus_d1_cdc_to_13), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[14]), + .Q(s_level_out_bus_d1_cdc_to_14), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[15]), + .Q(s_level_out_bus_d1_cdc_to_15), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[16]), + .Q(s_level_out_bus_d1_cdc_to_16), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[17]), + .Q(s_level_out_bus_d1_cdc_to_17), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[18]), + .Q(s_level_out_bus_d1_cdc_to_18), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[19]), + .Q(s_level_out_bus_d1_cdc_to_19), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[1]), + .Q(s_level_out_bus_d1_cdc_to_1), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[20]), + .Q(s_level_out_bus_d1_cdc_to_20), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[21]), + .Q(s_level_out_bus_d1_cdc_to_21), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[22]), + .Q(s_level_out_bus_d1_cdc_to_22), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[23]), + .Q(s_level_out_bus_d1_cdc_to_23), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[24]), + .Q(s_level_out_bus_d1_cdc_to_24), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[25]), + .Q(s_level_out_bus_d1_cdc_to_25), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[26]), + .Q(s_level_out_bus_d1_cdc_to_26), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[27]), + .Q(s_level_out_bus_d1_cdc_to_27), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[28]), + .Q(s_level_out_bus_d1_cdc_to_28), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[29]), + .Q(s_level_out_bus_d1_cdc_to_29), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[2]), + .Q(s_level_out_bus_d1_cdc_to_2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[30]), + .Q(s_level_out_bus_d1_cdc_to_30), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[31]), + .Q(s_level_out_bus_d1_cdc_to_31), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[3]), + .Q(s_level_out_bus_d1_cdc_to_3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[4]), + .Q(s_level_out_bus_d1_cdc_to_4), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[5]), + .Q(s_level_out_bus_d1_cdc_to_5), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[6]), + .Q(s_level_out_bus_d1_cdc_to_6), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[7]), + .Q(s_level_out_bus_d1_cdc_to_7), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[8]), + .Q(s_level_out_bus_d1_cdc_to_8), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i[9]), + .Q(s_level_out_bus_d1_cdc_to_9), + .R(1'b0)); +endmodule + +(* CHECK_LICENSE_TYPE = "design_1_axi_gpio_0_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2018.2" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (s_axi_aclk, + s_axi_aresetn, + s_axi_awaddr, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready, + gpio_io_i, + gpio_io_o, + gpio_io_t); + (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0" *) input s_axi_aclk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW" *) input s_axi_aresetn; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [8:0]s_axi_awaddr; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready; + (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE" *) input [31:0]gpio_io_i; + (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [31:0]gpio_io_o; + (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_T" *) output [31:0]gpio_io_t; + + wire [31:0]gpio_io_i; + wire [31:0]gpio_io_o; + wire [31:0]gpio_io_t; + wire s_axi_aclk; + wire [8:0]s_axi_araddr; + wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [8:0]s_axi_awaddr; + wire s_axi_awready; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + wire [1:0]s_axi_rresp; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire s_axi_wready; + wire [3:0]s_axi_wstrb; + wire s_axi_wvalid; + wire NLW_U0_ip2intc_irpt_UNCONNECTED; + wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED; + wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED; + + (* C_ALL_INPUTS = "0" *) + (* C_ALL_INPUTS_2 = "0" *) + (* C_ALL_OUTPUTS = "0" *) + (* C_ALL_OUTPUTS_2 = "0" *) + (* C_DOUT_DEFAULT = "0" *) + (* C_DOUT_DEFAULT_2 = "0" *) + (* C_FAMILY = "kintex7" *) + (* C_GPIO2_WIDTH = "32" *) + (* C_GPIO_WIDTH = "32" *) + (* C_INTERRUPT_PRESENT = "0" *) + (* C_IS_DUAL = "0" *) + (* C_S_AXI_ADDR_WIDTH = "9" *) + (* C_S_AXI_DATA_WIDTH = "32" *) + (* C_TRI_DEFAULT = "-1" *) + (* C_TRI_DEFAULT_2 = "-1" *) + (* downgradeipidentifiedwarnings = "yes" *) + (* ip_group = "LOGICORE" *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0 + (.gpio2_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]), + .gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]), + .gpio_io_i(gpio_io_i), + .gpio_io_o(gpio_io_o), + .gpio_io_t(gpio_io_t), + .ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED), + .s_axi_aclk(s_axi_aclk), + .s_axi_araddr(s_axi_araddr), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment + (SR, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] , + s_axi_rvalid, + s_axi_bvalid, + \MEM_DECODE_GEN[0].cs_out_i_reg[0] , + p_75_in, + p_73_in, + E, + \Not_Dual.gpio_Data_Out_reg[0] , + s_axi_arready, + s_axi_wready, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]_0 , + s_axi_rdata, + D, + s_axi_aclk, + s_axi_arvalid, + s_axi_rready, + s_axi_bready, + s_axi_aresetn, + s_axi_awvalid, + s_axi_wvalid, + GPIO_xferAck_i, + gpio_xferAck_Reg, + Q, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg , + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg , + ip2bus_rdack_i_D1, + ip2bus_wrack_i_D1, + s_axi_araddr, + s_axi_awaddr); + output [0:0]SR; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] ; + output s_axi_rvalid; + output s_axi_bvalid; + output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ; + output p_75_in; + output p_73_in; + output [0:0]E; + output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; + output s_axi_arready; + output s_axi_wready; + output \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]_0 ; + output [31:0]s_axi_rdata; + output [31:0]D; + input s_axi_aclk; + input s_axi_arvalid; + input s_axi_rready; + input s_axi_bready; + input s_axi_aresetn; + input s_axi_awvalid; + input s_axi_wvalid; + input GPIO_xferAck_i; + input gpio_xferAck_Reg; + input [31:0]Q; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ; + input \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ; + input ip2bus_rdack_i_D1; + input ip2bus_wrack_i_D1; + input [2:0]s_axi_araddr; + input [2:0]s_axi_awaddr; + + wire [31:0]D; + wire [0:0]E; + wire \FSM_onehot_state[0]_i_1_n_0 ; + wire \FSM_onehot_state[1]_i_1_n_0 ; + wire \FSM_onehot_state[2]_i_1_n_0 ; + wire \FSM_onehot_state[3]_i_1_n_0 ; + (* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[0] ; + (* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[3] ; + wire GPIO_xferAck_i; + wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ; + wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]_0 ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ; + wire \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ; + wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; + wire [31:0]Q; + wire [0:0]SR; + wire [0:6]bus2ip_addr; + wire \bus2ip_addr_i[2]_i_1_n_0 ; + wire \bus2ip_addr_i[3]_i_1_n_0 ; + wire \bus2ip_addr_i[8]_i_1_n_0 ; + wire \bus2ip_addr_i[8]_i_2_n_0 ; + wire clear; + wire gpio_xferAck_Reg; + wire ip2bus_rdack_i_D1; + wire ip2bus_wrack_i_D1; + wire is_read_i_1_n_0; + wire is_read_reg_n_0; + wire is_write_i_1_n_0; + wire is_write_i_2_n_0; + wire is_write_reg_n_0; + wire [1:0]p_0_out; + wire p_5_in; + wire p_73_in; + wire p_75_in; + wire [3:0]plusOp; + wire rst_i_1_n_0; + wire s_axi_aclk; + wire [2:0]s_axi_araddr; + wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [2:0]s_axi_awaddr; + wire s_axi_awvalid; + wire s_axi_bready; + (* RTL_KEEP = "yes" *) wire s_axi_bresp_i; + wire s_axi_bvalid; + wire s_axi_bvalid_i_i_1_n_0; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + (* RTL_KEEP = "yes" *) wire s_axi_rresp_i; + wire s_axi_rvalid; + wire s_axi_rvalid_i_i_1_n_0; + wire s_axi_wready; + wire s_axi_wvalid; + wire start2; + wire start2_i_1_n_0; + wire [1:0]state; + wire state1__2; + + LUT6 #( + .INIT(64'hFFFF150015001500)) + \FSM_onehot_state[0]_i_1 + (.I0(s_axi_arvalid), + .I1(s_axi_wvalid), + .I2(s_axi_awvalid), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .I4(state1__2), + .I5(\FSM_onehot_state_reg_n_0_[3] ), + .O(\FSM_onehot_state[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'h8F88)) + \FSM_onehot_state[1]_i_1 + (.I0(s_axi_arvalid), + .I1(\FSM_onehot_state_reg_n_0_[0] ), + .I2(s_axi_arready), + .I3(s_axi_rresp_i), + .O(\FSM_onehot_state[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0800FFFF08000800)) + \FSM_onehot_state[2]_i_1 + (.I0(s_axi_wvalid), + .I1(s_axi_awvalid), + .I2(s_axi_arvalid), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .I4(s_axi_wready), + .I5(s_axi_bresp_i), + .O(\FSM_onehot_state[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF888F888FFFFF888)) + \FSM_onehot_state[3]_i_1 + (.I0(s_axi_wready), + .I1(s_axi_bresp_i), + .I2(s_axi_rresp_i), + .I3(s_axi_arready), + .I4(\FSM_onehot_state_reg_n_0_[3] ), + .I5(state1__2), + .O(\FSM_onehot_state[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \FSM_onehot_state[3]_i_2 + (.I0(s_axi_bready), + .I1(s_axi_bvalid), + .I2(s_axi_rready), + .I3(s_axi_rvalid), + .O(state1__2)); + (* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *) + (* KEEP = "yes" *) + FDSE #( + .INIT(1'b1)) + \FSM_onehot_state_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\FSM_onehot_state[0]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[0] ), + .S(SR)); + (* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\FSM_onehot_state[1]_i_1_n_0 ), + .Q(s_axi_rresp_i), + .R(SR)); + (* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[2] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\FSM_onehot_state[2]_i_1_n_0 ), + .Q(s_axi_bresp_i), + .R(SR)); + (* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[3] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\FSM_onehot_state[3]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[3] ), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT1 #( + .INIT(2'h1)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .O(plusOp[0])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h6)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .O(plusOp[1])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .O(plusOp[2])); + LUT2 #( + .INIT(4'h9)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 + (.I0(state[0]), + .I1(state[1]), + .O(clear)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h7F80)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]), + .O(plusOp[3])); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(plusOp[0]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(plusOp[1]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] + (.C(s_axi_aclk), + .CE(1'b1), + .D(plusOp[2]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] + (.C(s_axi_aclk), + .CE(1'b1), + .D(plusOp[3]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]), + .R(clear)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER + (.D(D), + .E(E), + .GPIO_xferAck_i(GPIO_xferAck_i), + .\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ), + .\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]_0 ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg ), + .\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg (\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg ), + .\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ), + .Q(start2), + .\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}), + .bus2ip_rnw_i_reg(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] ), + .gpio_xferAck_Reg(gpio_xferAck_Reg), + .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), + .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), + .is_read_reg(is_read_reg_n_0), + .is_write_reg(is_write_reg_n_0), + .p_73_in(p_73_in), + .p_75_in(p_75_in), + .s_axi_aclk(s_axi_aclk), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_arready(s_axi_arready), + .s_axi_wready(s_axi_wready)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT3 #( + .INIT(8'hAC)) + \bus2ip_addr_i[2]_i_1 + (.I0(s_axi_araddr[0]), + .I1(s_axi_awaddr[0]), + .I2(s_axi_arvalid), + .O(\bus2ip_addr_i[2]_i_1_n_0 )); + LUT3 #( + .INIT(8'hAC)) + \bus2ip_addr_i[3]_i_1 + (.I0(s_axi_araddr[1]), + .I1(s_axi_awaddr[1]), + .I2(s_axi_arvalid), + .O(\bus2ip_addr_i[3]_i_1_n_0 )); + LUT5 #( + .INIT(32'h000000EA)) + \bus2ip_addr_i[8]_i_1 + (.I0(s_axi_arvalid), + .I1(s_axi_awvalid), + .I2(s_axi_wvalid), + .I3(state[1]), + .I4(state[0]), + .O(\bus2ip_addr_i[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT3 #( + .INIT(8'hAC)) + \bus2ip_addr_i[8]_i_2 + (.I0(s_axi_araddr[2]), + .I1(s_axi_awaddr[2]), + .I2(s_axi_arvalid), + .O(\bus2ip_addr_i[8]_i_2_n_0 )); + FDRE \bus2ip_addr_i_reg[2] + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[2]_i_1_n_0 ), + .Q(bus2ip_addr[6]), + .R(SR)); + FDRE \bus2ip_addr_i_reg[3] + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[3]_i_1_n_0 ), + .Q(bus2ip_addr[5]), + .R(SR)); + FDRE \bus2ip_addr_i_reg[8] + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[8]_i_2_n_0 ), + .Q(bus2ip_addr[0]), + .R(SR)); + FDRE bus2ip_rnw_i_reg + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(s_axi_arvalid), + .Q(\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] ), + .R(SR)); + LUT5 #( + .INIT(32'h8BBB8888)) + is_read_i_1 + (.I0(s_axi_arvalid), + .I1(\FSM_onehot_state_reg_n_0_[0] ), + .I2(state1__2), + .I3(\FSM_onehot_state_reg_n_0_[3] ), + .I4(is_read_reg_n_0), + .O(is_read_i_1_n_0)); + FDRE is_read_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(is_read_i_1_n_0), + .Q(is_read_reg_n_0), + .R(SR)); + LUT6 #( + .INIT(64'h2000FFFF20000000)) + is_write_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(s_axi_arvalid), + .I2(s_axi_awvalid), + .I3(s_axi_wvalid), + .I4(is_write_i_2_n_0), + .I5(is_write_reg_n_0), + .O(is_write_i_1_n_0)); + LUT6 #( + .INIT(64'hFFEAEAEAAAAAAAAA)) + is_write_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(s_axi_bready), + .I2(s_axi_bvalid), + .I3(s_axi_rready), + .I4(s_axi_rvalid), + .I5(\FSM_onehot_state_reg_n_0_[3] ), + .O(is_write_i_2_n_0)); + FDRE is_write_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(is_write_i_1_n_0), + .Q(is_write_reg_n_0), + .R(SR)); + LUT1 #( + .INIT(2'h1)) + rst_i_1 + (.I0(s_axi_aresetn), + .O(rst_i_1_n_0)); + FDRE rst_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(rst_i_1_n_0), + .Q(SR), + .R(1'b0)); + LUT5 #( + .INIT(32'h08FF0808)) + s_axi_bvalid_i_i_1 + (.I0(s_axi_wready), + .I1(state[1]), + .I2(state[0]), + .I3(s_axi_bready), + .I4(s_axi_bvalid), + .O(s_axi_bvalid_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + s_axi_bvalid_i_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_axi_bvalid_i_i_1_n_0), + .Q(s_axi_bvalid), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[0] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[0]), + .Q(s_axi_rdata[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[10] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[10]), + .Q(s_axi_rdata[10]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[11] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[11]), + .Q(s_axi_rdata[11]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[12] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[12]), + .Q(s_axi_rdata[12]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[13] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[13]), + .Q(s_axi_rdata[13]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[14] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[14]), + .Q(s_axi_rdata[14]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[15] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[15]), + .Q(s_axi_rdata[15]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[16] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[16]), + .Q(s_axi_rdata[16]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[17] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[17]), + .Q(s_axi_rdata[17]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[18] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[18]), + .Q(s_axi_rdata[18]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[19] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[19]), + .Q(s_axi_rdata[19]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[1] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[1]), + .Q(s_axi_rdata[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[20] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[20]), + .Q(s_axi_rdata[20]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[21] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[21]), + .Q(s_axi_rdata[21]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[22] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[22]), + .Q(s_axi_rdata[22]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[23] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[23]), + .Q(s_axi_rdata[23]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[24] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[24]), + .Q(s_axi_rdata[24]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[25] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[25]), + .Q(s_axi_rdata[25]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[26] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[26]), + .Q(s_axi_rdata[26]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[27] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[27]), + .Q(s_axi_rdata[27]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[28] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[28]), + .Q(s_axi_rdata[28]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[29] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[29]), + .Q(s_axi_rdata[29]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[2] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[2]), + .Q(s_axi_rdata[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[30] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[30]), + .Q(s_axi_rdata[30]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[31] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[31]), + .Q(s_axi_rdata[31]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[3] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[3]), + .Q(s_axi_rdata[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[4] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[4]), + .Q(s_axi_rdata[4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[5] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[5]), + .Q(s_axi_rdata[5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[6] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[6]), + .Q(s_axi_rdata[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[7] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[7]), + .Q(s_axi_rdata[7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[8] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[8]), + .Q(s_axi_rdata[8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[9] + (.C(s_axi_aclk), + .CE(s_axi_rresp_i), + .D(Q[9]), + .Q(s_axi_rdata[9]), + .R(SR)); + LUT5 #( + .INIT(32'h08FF0808)) + s_axi_rvalid_i_i_1 + (.I0(s_axi_arready), + .I1(state[0]), + .I2(state[1]), + .I3(s_axi_rready), + .I4(s_axi_rvalid), + .O(s_axi_rvalid_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + s_axi_rvalid_i_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_axi_rvalid_i_i_1_n_0), + .Q(s_axi_rvalid), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'h000000F8)) + start2_i_1 + (.I0(s_axi_awvalid), + .I1(s_axi_wvalid), + .I2(s_axi_arvalid), + .I3(state[1]), + .I4(state[0]), + .O(start2_i_1_n_0)); + FDRE start2_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(start2_i_1_n_0), + .Q(start2), + .R(SR)); + LUT5 #( + .INIT(32'h77FC44FC)) + \state[0]_i_1 + (.I0(state1__2), + .I1(state[0]), + .I2(s_axi_arvalid), + .I3(state[1]), + .I4(s_axi_wready), + .O(p_0_out[0])); + LUT6 #( + .INIT(64'h55FFFF0C5500FF0C)) + \state[1]_i_1 + (.I0(state1__2), + .I1(p_5_in), + .I2(s_axi_arvalid), + .I3(state[1]), + .I4(state[0]), + .I5(s_axi_arready), + .O(p_0_out[1])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h8)) + \state[1]_i_2 + (.I0(s_axi_awvalid), + .I1(s_axi_wvalid), + .O(p_5_in)); + FDRE \state_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(p_0_out[0]), + .Q(state[0]), + .R(SR)); + FDRE \state_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(p_0_out[1]), + .Q(state[1]), + .R(SR)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_sim_netlist.vhdl b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..835122e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_sim_netlist.vhdl @@ -0,0 +1,7366 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 17:10:34 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_0_0_sim_netlist.vhdl +-- Design : design_1_axi_gpio_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is + port ( + \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC; + p_75_in : out STD_LOGIC; + p_73_in : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arready : out STD_LOGIC; + s_axi_wready : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 31 downto 0 ); + Q : in STD_LOGIC; + s_axi_aclk : in STD_LOGIC; + \bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + bus2ip_rnw_i_reg : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + GPIO_xferAck_i : in STD_LOGIC; + gpio_xferAck_Reg : in STD_LOGIC; + ip2bus_rdack_i_D1 : in STD_LOGIC; + is_read_reg : in STD_LOGIC; + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ip2bus_wrack_i_D1 : in STD_LOGIC; + is_write_reg : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\ : in STD_LOGIC + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is + signal Bus_RNW_reg : STD_LOGIC; + signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC; + signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC; + signal \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC; + signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC; + signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC; + signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC; + signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC; + signal ce_expnd_i_0 : STD_LOGIC; + signal ce_expnd_i_1 : STD_LOGIC; + signal ce_expnd_i_2 : STD_LOGIC; + signal ce_expnd_i_3 : STD_LOGIC; + signal cs_ce_clr : STD_LOGIC; + signal \ip2bus_data_i_D1[0]_i_2_n_0\ : STD_LOGIC; + signal \ip2bus_data_i_D1[0]_i_3_n_0\ : STD_LOGIC; + signal \ip2bus_data_i_D1[0]_i_4_n_0\ : STD_LOGIC; + signal \^s_axi_arready\ : STD_LOGIC; + signal \^s_axi_wready\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_3\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \Not_Dual.gpio_OE[0]_i_1\ : label is "soft_lutpair0"; +begin + \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\; + s_axi_arready <= \^s_axi_arready\; + s_axi_wready <= \^s_axi_wready\; +Bus_RNW_reg_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => bus2ip_rnw_i_reg, + I1 => Q, + I2 => Bus_RNW_reg, + O => Bus_RNW_reg_i_1_n_0 + ); +Bus_RNW_reg_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => Bus_RNW_reg_i_1_n_0, + Q => Bus_RNW_reg, + R => '0' + ); +\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(0), + I1 => \bus2ip_addr_i_reg[8]\(1), + O => ce_expnd_i_3 + ); +\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => ce_expnd_i_3, + Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, + R => cs_ce_clr + ); +\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(0), + I1 => \bus2ip_addr_i_reg[8]\(1), + O => ce_expnd_i_2 + ); +\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => ce_expnd_i_2, + Q => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, + R => cs_ce_clr + ); +\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(1), + I1 => \bus2ip_addr_i_reg[8]\(0), + O => ce_expnd_i_1 + ); +\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => ce_expnd_i_1, + Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, + R => cs_ce_clr + ); +\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EF" + ) + port map ( + I0 => \^s_axi_wready\, + I1 => \^s_axi_arready\, + I2 => s_axi_aresetn, + O => cs_ce_clr + ); +\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(1), + I1 => \bus2ip_addr_i_reg[8]\(0), + O => ce_expnd_i_0 + ); +\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => ce_expnd_i_0, + Q => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, + R => cs_ce_clr + ); +\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E0" + ) + port map ( + I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I1 => Q, + I2 => s_axi_aresetn, + I3 => \^s_axi_arready\, + I4 => \^s_axi_wready\, + O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ + ); +\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\, + Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + R => '0' + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FDFF" + ) + port map ( + I0 => bus2ip_rnw_i_reg, + I1 => GPIO_xferAck_i, + I2 => gpio_xferAck_Reg, + I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0400" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(2), + I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I2 => \bus2ip_addr_i_reg[8]\(1), + I3 => \bus2ip_addr_i_reg[8]\(0), + O => p_73_in + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(2), + I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I2 => \bus2ip_addr_i_reg[8]\(0), + I3 => \bus2ip_addr_i_reg[8]\(1), + O => p_75_in + ); +\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000010" + ) + port map ( + I0 => bus2ip_rnw_i_reg, + I1 => \bus2ip_addr_i_reg[8]\(2), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => \bus2ip_addr_i_reg[8]\(0), + I4 => \bus2ip_addr_i_reg[8]\(1), + O => \Not_Dual.gpio_Data_Out_reg[0]\(0) + ); +\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00100000" + ) + port map ( + I0 => bus2ip_rnw_i_reg, + I1 => \bus2ip_addr_i_reg[8]\(2), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => \bus2ip_addr_i_reg[8]\(1), + I4 => \bus2ip_addr_i_reg[8]\(0), + O => E(0) + ); +\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(31) + ); +\ip2bus_data_i_D1[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000400" + ) + port map ( + I0 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, + I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, + I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, + I3 => Bus_RNW_reg, + I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, + O => \ip2bus_data_i_D1[0]_i_2_n_0\ + ); +\ip2bus_data_i_D1[0]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00040000" + ) + port map ( + I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, + I1 => Bus_RNW_reg, + I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, + I3 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, + I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, + O => \ip2bus_data_i_D1[0]_i_3_n_0\ + ); +\ip2bus_data_i_D1[0]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000400" + ) + port map ( + I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, + I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, + I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, + I3 => Bus_RNW_reg, + I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, + O => \ip2bus_data_i_D1[0]_i_4_n_0\ + ); +\ip2bus_data_i_D1[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(21) + ); +\ip2bus_data_i_D1[11]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(20) + ); +\ip2bus_data_i_D1[12]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(19) + ); +\ip2bus_data_i_D1[13]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(18) + ); +\ip2bus_data_i_D1[14]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(17) + ); +\ip2bus_data_i_D1[15]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(16) + ); +\ip2bus_data_i_D1[16]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(15) + ); +\ip2bus_data_i_D1[17]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(14) + ); +\ip2bus_data_i_D1[18]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(13) + ); +\ip2bus_data_i_D1[19]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(12) + ); +\ip2bus_data_i_D1[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(30) + ); +\ip2bus_data_i_D1[20]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(11) + ); +\ip2bus_data_i_D1[21]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(10) + ); +\ip2bus_data_i_D1[22]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(9) + ); +\ip2bus_data_i_D1[23]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(8) + ); +\ip2bus_data_i_D1[24]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(7) + ); +\ip2bus_data_i_D1[25]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(6) + ); +\ip2bus_data_i_D1[26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(5) + ); +\ip2bus_data_i_D1[27]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(4) + ); +\ip2bus_data_i_D1[28]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(3) + ); +\ip2bus_data_i_D1[29]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(2) + ); +\ip2bus_data_i_D1[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(29) + ); +\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(1) + ); +\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(0) + ); +\ip2bus_data_i_D1[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(28) + ); +\ip2bus_data_i_D1[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(27) + ); +\ip2bus_data_i_D1[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(26) + ); +\ip2bus_data_i_D1[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(25) + ); +\ip2bus_data_i_D1[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(24) + ); +\ip2bus_data_i_D1[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(23) + ); +\ip2bus_data_i_D1[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2bus_data_i_D1[0]_i_2_n_0\, + I1 => \ip2bus_data_i_D1[0]_i_3_n_0\, + I2 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\, + I3 => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\, + I4 => \ip2bus_data_i_D1[0]_i_4_n_0\, + O => D(22) + ); +s_axi_arready_INST_0: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAEAAAA" + ) + port map ( + I0 => ip2bus_rdack_i_D1, + I1 => is_read_reg, + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3), + I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), + O => \^s_axi_arready\ + ); +s_axi_wready_INST_0: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAEAAAA" + ) + port map ( + I0 => ip2bus_wrack_i_D1, + I1 => is_write_reg, + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3), + I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), + O => \^s_axi_wready\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is + port ( + scndry_vect_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_aclk : in STD_LOGIC + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is + signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_10 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_11 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_12 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_13 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_14 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_15 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_16 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_17 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_18 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_19 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_20 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_21 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_22 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_23 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_24 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_25 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_26 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_27 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_28 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_29 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_30 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_31 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_8 : STD_LOGIC; + signal s_level_out_bus_d1_cdc_to_9 : STD_LOGIC; + signal s_level_out_bus_d2_0 : STD_LOGIC; + signal s_level_out_bus_d2_1 : STD_LOGIC; + signal s_level_out_bus_d2_10 : STD_LOGIC; + signal s_level_out_bus_d2_11 : STD_LOGIC; + signal s_level_out_bus_d2_12 : STD_LOGIC; + signal s_level_out_bus_d2_13 : STD_LOGIC; + signal s_level_out_bus_d2_14 : STD_LOGIC; + signal s_level_out_bus_d2_15 : STD_LOGIC; + signal s_level_out_bus_d2_16 : STD_LOGIC; + signal s_level_out_bus_d2_17 : STD_LOGIC; + signal s_level_out_bus_d2_18 : STD_LOGIC; + signal s_level_out_bus_d2_19 : STD_LOGIC; + signal s_level_out_bus_d2_2 : STD_LOGIC; + signal s_level_out_bus_d2_20 : STD_LOGIC; + signal s_level_out_bus_d2_21 : STD_LOGIC; + signal s_level_out_bus_d2_22 : STD_LOGIC; + signal s_level_out_bus_d2_23 : STD_LOGIC; + signal s_level_out_bus_d2_24 : STD_LOGIC; + signal s_level_out_bus_d2_25 : STD_LOGIC; + signal s_level_out_bus_d2_26 : STD_LOGIC; + signal s_level_out_bus_d2_27 : STD_LOGIC; + signal s_level_out_bus_d2_28 : STD_LOGIC; + signal s_level_out_bus_d2_29 : STD_LOGIC; + signal s_level_out_bus_d2_3 : STD_LOGIC; + signal s_level_out_bus_d2_30 : STD_LOGIC; + signal s_level_out_bus_d2_31 : STD_LOGIC; + signal s_level_out_bus_d2_4 : STD_LOGIC; + signal s_level_out_bus_d2_5 : STD_LOGIC; + signal s_level_out_bus_d2_6 : STD_LOGIC; + signal s_level_out_bus_d2_7 : STD_LOGIC; + signal s_level_out_bus_d2_8 : STD_LOGIC; + signal s_level_out_bus_d2_9 : STD_LOGIC; + signal s_level_out_bus_d3_0 : STD_LOGIC; + signal s_level_out_bus_d3_1 : STD_LOGIC; + signal s_level_out_bus_d3_10 : STD_LOGIC; + signal s_level_out_bus_d3_11 : STD_LOGIC; + signal s_level_out_bus_d3_12 : STD_LOGIC; + signal s_level_out_bus_d3_13 : STD_LOGIC; + signal s_level_out_bus_d3_14 : STD_LOGIC; + signal s_level_out_bus_d3_15 : STD_LOGIC; + signal s_level_out_bus_d3_16 : STD_LOGIC; + signal s_level_out_bus_d3_17 : STD_LOGIC; + signal s_level_out_bus_d3_18 : STD_LOGIC; + signal s_level_out_bus_d3_19 : STD_LOGIC; + signal s_level_out_bus_d3_2 : STD_LOGIC; + signal s_level_out_bus_d3_20 : STD_LOGIC; + signal s_level_out_bus_d3_21 : STD_LOGIC; + signal s_level_out_bus_d3_22 : STD_LOGIC; + signal s_level_out_bus_d3_23 : STD_LOGIC; + signal s_level_out_bus_d3_24 : STD_LOGIC; + signal s_level_out_bus_d3_25 : STD_LOGIC; + signal s_level_out_bus_d3_26 : STD_LOGIC; + signal s_level_out_bus_d3_27 : STD_LOGIC; + signal s_level_out_bus_d3_28 : STD_LOGIC; + signal s_level_out_bus_d3_29 : STD_LOGIC; + signal s_level_out_bus_d3_3 : STD_LOGIC; + signal s_level_out_bus_d3_30 : STD_LOGIC; + signal s_level_out_bus_d3_31 : STD_LOGIC; + signal s_level_out_bus_d3_4 : STD_LOGIC; + signal s_level_out_bus_d3_5 : STD_LOGIC; + signal s_level_out_bus_d3_6 : STD_LOGIC; + signal s_level_out_bus_d3_7 : STD_LOGIC; + signal s_level_out_bus_d3_8 : STD_LOGIC; + signal s_level_out_bus_d3_9 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_0, + Q => s_level_out_bus_d2_0, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_10, + Q => s_level_out_bus_d2_10, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_11, + Q => s_level_out_bus_d2_11, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_12, + Q => s_level_out_bus_d2_12, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_13, + Q => s_level_out_bus_d2_13, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_14, + Q => s_level_out_bus_d2_14, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_15, + Q => s_level_out_bus_d2_15, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_16, + Q => s_level_out_bus_d2_16, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_17, + Q => s_level_out_bus_d2_17, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_18, + Q => s_level_out_bus_d2_18, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_19, + Q => s_level_out_bus_d2_19, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_1, + Q => s_level_out_bus_d2_1, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_20, + Q => s_level_out_bus_d2_20, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_21, + Q => s_level_out_bus_d2_21, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_22, + Q => s_level_out_bus_d2_22, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_23, + Q => s_level_out_bus_d2_23, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_24, + Q => s_level_out_bus_d2_24, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_25, + Q => s_level_out_bus_d2_25, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_26, + Q => s_level_out_bus_d2_26, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_27, + Q => s_level_out_bus_d2_27, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_28, + Q => s_level_out_bus_d2_28, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_29, + Q => s_level_out_bus_d2_29, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_2, + Q => s_level_out_bus_d2_2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_30, + Q => s_level_out_bus_d2_30, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_31, + Q => s_level_out_bus_d2_31, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_3, + Q => s_level_out_bus_d2_3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_4, + Q => s_level_out_bus_d2_4, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_5, + Q => s_level_out_bus_d2_5, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_6, + Q => s_level_out_bus_d2_6, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_7, + Q => s_level_out_bus_d2_7, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_8, + Q => s_level_out_bus_d2_8, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d1_cdc_to_9, + Q => s_level_out_bus_d2_9, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_0, + Q => s_level_out_bus_d3_0, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_10, + Q => s_level_out_bus_d3_10, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_11, + Q => s_level_out_bus_d3_11, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_12, + Q => s_level_out_bus_d3_12, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_13, + Q => s_level_out_bus_d3_13, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_14, + Q => s_level_out_bus_d3_14, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_15, + Q => s_level_out_bus_d3_15, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_16, + Q => s_level_out_bus_d3_16, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_17, + Q => s_level_out_bus_d3_17, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_18, + Q => s_level_out_bus_d3_18, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_19, + Q => s_level_out_bus_d3_19, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_1, + Q => s_level_out_bus_d3_1, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_20, + Q => s_level_out_bus_d3_20, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_21, + Q => s_level_out_bus_d3_21, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_22, + Q => s_level_out_bus_d3_22, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_23, + Q => s_level_out_bus_d3_23, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_24, + Q => s_level_out_bus_d3_24, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_25, + Q => s_level_out_bus_d3_25, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_26, + Q => s_level_out_bus_d3_26, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_27, + Q => s_level_out_bus_d3_27, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_28, + Q => s_level_out_bus_d3_28, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_29, + Q => s_level_out_bus_d3_29, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_2, + Q => s_level_out_bus_d3_2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_30, + Q => s_level_out_bus_d3_30, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_31, + Q => s_level_out_bus_d3_31, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_3, + Q => s_level_out_bus_d3_3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_4, + Q => s_level_out_bus_d3_4, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_5, + Q => s_level_out_bus_d3_5, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_6, + Q => s_level_out_bus_d3_6, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_7, + Q => s_level_out_bus_d3_7, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_8, + Q => s_level_out_bus_d3_8, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d2_9, + Q => s_level_out_bus_d3_9, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_0, + Q => scndry_vect_out(0), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_10, + Q => scndry_vect_out(10), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_11, + Q => scndry_vect_out(11), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_12, + Q => scndry_vect_out(12), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_13, + Q => scndry_vect_out(13), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_14, + Q => scndry_vect_out(14), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_15, + Q => scndry_vect_out(15), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_16, + Q => scndry_vect_out(16), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_17, + Q => scndry_vect_out(17), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_18, + Q => scndry_vect_out(18), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_19, + Q => scndry_vect_out(19), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_1, + Q => scndry_vect_out(1), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_20, + Q => scndry_vect_out(20), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_21, + Q => scndry_vect_out(21), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_22, + Q => scndry_vect_out(22), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_23, + Q => scndry_vect_out(23), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_24, + Q => scndry_vect_out(24), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_25, + Q => scndry_vect_out(25), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_26, + Q => scndry_vect_out(26), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_27, + Q => scndry_vect_out(27), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_28, + Q => scndry_vect_out(28), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_29, + Q => scndry_vect_out(29), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_2, + Q => scndry_vect_out(2), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_30, + Q => scndry_vect_out(30), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_31, + Q => scndry_vect_out(31), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_3, + Q => scndry_vect_out(3), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_4, + Q => scndry_vect_out(4), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_5, + Q => scndry_vect_out(5), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_6, + Q => scndry_vect_out(6), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_7, + Q => scndry_vect_out(7), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_8, + Q => scndry_vect_out(8), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_level_out_bus_d3_9, + Q => scndry_vect_out(9), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(0), + Q => s_level_out_bus_d1_cdc_to_0, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(10), + Q => s_level_out_bus_d1_cdc_to_10, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(11), + Q => s_level_out_bus_d1_cdc_to_11, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(12), + Q => s_level_out_bus_d1_cdc_to_12, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(13), + Q => s_level_out_bus_d1_cdc_to_13, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(14), + Q => s_level_out_bus_d1_cdc_to_14, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(15), + Q => s_level_out_bus_d1_cdc_to_15, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(16), + Q => s_level_out_bus_d1_cdc_to_16, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(17), + Q => s_level_out_bus_d1_cdc_to_17, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(18), + Q => s_level_out_bus_d1_cdc_to_18, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(19), + Q => s_level_out_bus_d1_cdc_to_19, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(1), + Q => s_level_out_bus_d1_cdc_to_1, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[20].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(20), + Q => s_level_out_bus_d1_cdc_to_20, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[21].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(21), + Q => s_level_out_bus_d1_cdc_to_21, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[22].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(22), + Q => s_level_out_bus_d1_cdc_to_22, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[23].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(23), + Q => s_level_out_bus_d1_cdc_to_23, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[24].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(24), + Q => s_level_out_bus_d1_cdc_to_24, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[25].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(25), + Q => s_level_out_bus_d1_cdc_to_25, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[26].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(26), + Q => s_level_out_bus_d1_cdc_to_26, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[27].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(27), + Q => s_level_out_bus_d1_cdc_to_27, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[28].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(28), + Q => s_level_out_bus_d1_cdc_to_28, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[29].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(29), + Q => s_level_out_bus_d1_cdc_to_29, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(2), + Q => s_level_out_bus_d1_cdc_to_2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[30].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(30), + Q => s_level_out_bus_d1_cdc_to_30, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[31].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(31), + Q => s_level_out_bus_d1_cdc_to_31, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(3), + Q => s_level_out_bus_d1_cdc_to_3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(4), + Q => s_level_out_bus_d1_cdc_to_4, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(5), + Q => s_level_out_bus_d1_cdc_to_5, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(6), + Q => s_level_out_bus_d1_cdc_to_6, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(7), + Q => s_level_out_bus_d1_cdc_to_7, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(8), + Q => s_level_out_bus_d1_cdc_to_8, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(9), + Q => s_level_out_bus_d1_cdc_to_9, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is + port ( + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\ : out STD_LOGIC; + GPIO_xferAck_i : out STD_LOGIC; + gpio_xferAck_Reg : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\ : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\ : out STD_LOGIC; + gpio_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 ); + ip2bus_wrack_i : out STD_LOGIC; + ip2bus_rdack_i : out STD_LOGIC; + bus2ip_rnw_i_reg : in STD_LOGIC; + s_axi_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_73_in : in STD_LOGIC; + p_75_in : in STD_LOGIC; + bus2ip_rnw : in STD_LOGIC; + bus2ip_cs : in STD_LOGIC; + gpio_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + bus2ip_rnw_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is + signal \^gpio_xferack_i\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[0]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[0]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[0].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1[10]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2[10]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[10].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1[11]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2[11]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[11].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1[12]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2[12]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[12].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1[13]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2[13]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[13].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1[14]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2[14]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[14].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1[15]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2[15]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[15].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1[16]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2[16]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[16].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1[17]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2[17]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[17].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1[18]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2[18]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[18].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1[19]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2[19]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[19].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[1]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[1]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[1].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1[20]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2[20]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[20].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1[21]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2[21]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[21].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1[22]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2[22]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[22].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1[23]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2[23]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[23].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1[24]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2[24]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[24].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1[25]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2[25]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[25].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1[26]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2[26]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[26].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1[27]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2[27]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[27].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1[28]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2[28]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[28].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1[29]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2[29]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[29].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1[2]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2[2]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[2].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1[30]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2[30]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[30].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_2_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2[31]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[31].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1[3]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2[3]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[3].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1[4]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2[4]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[4].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1[5]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2[5]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[5].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1[6]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2[6]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[6].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1[7]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2[7]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[7].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1[8]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2[8]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[8].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1[9]_i_1_n_0\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2[9]_i_1_n_0\ : STD_LOGIC; + signal \^not_dual.allout0_nd.read_reg_gen[9].reg2_reg\ : STD_LOGIC; + signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 31 ); + signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 31 ); + signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^gpio_xferack_reg\ : STD_LOGIC; + signal iGPIO_xferAck : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of ip2bus_wrack_i_D1_i_1 : label is "soft_lutpair8"; +begin + GPIO_xferAck_i <= \^gpio_xferack_i\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[0].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[10].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[11].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[12].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[13].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[14].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[15].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[16].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[17].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[18].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[19].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[1].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[20].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[21].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[22].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[23].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[24].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[25].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[26].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[27].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[28].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[29].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[2].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[30].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[31].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[3].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[4].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[5].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[6].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[7].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[8].reg2_reg\; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\ <= \^not_dual.allout0_nd.read_reg_gen[9].reg2_reg\; + gpio_io_o(31 downto 0) <= \^gpio_io_o\(31 downto 0); + gpio_io_t(31 downto 0) <= \^gpio_io_t\(31 downto 0); + gpio_xferAck_Reg <= \^gpio_xferack_reg\; +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(31), + I1 => \^gpio_io_t\(31), + I2 => p_73_in, + I3 => gpio_Data_In(0), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[0]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[0]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[0].reg2_reg\, + I1 => \^gpio_io_t\(31), + I2 => p_73_in, + I3 => gpio_Data_In(0), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[0]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[0]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[0].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(21), + I1 => \^gpio_io_t\(21), + I2 => p_73_in, + I3 => gpio_Data_In(10), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1[10]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1[10]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[10].reg2_reg\, + I1 => \^gpio_io_t\(21), + I2 => p_73_in, + I3 => gpio_Data_In(10), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2[10]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2[10]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[10].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1[11]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(20), + I1 => \^gpio_io_t\(20), + I2 => p_73_in, + I3 => gpio_Data_In(11), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1[11]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1[11]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2[11]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[11].reg2_reg\, + I1 => \^gpio_io_t\(20), + I2 => p_73_in, + I3 => gpio_Data_In(11), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2[11]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2[11]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[11].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1[12]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(19), + I1 => \^gpio_io_t\(19), + I2 => p_73_in, + I3 => gpio_Data_In(12), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1[12]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1[12]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2[12]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[12].reg2_reg\, + I1 => \^gpio_io_t\(19), + I2 => p_73_in, + I3 => gpio_Data_In(12), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2[12]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2[12]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[12].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1[13]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(18), + I1 => \^gpio_io_t\(18), + I2 => p_73_in, + I3 => gpio_Data_In(13), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1[13]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1[13]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2[13]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[13].reg2_reg\, + I1 => \^gpio_io_t\(18), + I2 => p_73_in, + I3 => gpio_Data_In(13), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2[13]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2[13]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[13].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1[14]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(17), + I1 => \^gpio_io_t\(17), + I2 => p_73_in, + I3 => gpio_Data_In(14), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1[14]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1[14]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2[14]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[14].reg2_reg\, + I1 => \^gpio_io_t\(17), + I2 => p_73_in, + I3 => gpio_Data_In(14), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2[14]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2[14]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[14].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1[15]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(16), + I1 => \^gpio_io_t\(16), + I2 => p_73_in, + I3 => gpio_Data_In(15), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1[15]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1[15]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2[15]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[15].reg2_reg\, + I1 => \^gpio_io_t\(16), + I2 => p_73_in, + I3 => gpio_Data_In(15), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2[15]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2[15]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[15].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1[16]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(15), + I1 => \^gpio_io_t\(15), + I2 => p_73_in, + I3 => gpio_Data_In(16), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1[16]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1[16]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2[16]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[16].reg2_reg\, + I1 => \^gpio_io_t\(15), + I2 => p_73_in, + I3 => gpio_Data_In(16), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2[16]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2[16]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[16].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1[17]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(14), + I1 => \^gpio_io_t\(14), + I2 => p_73_in, + I3 => gpio_Data_In(17), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1[17]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1[17]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2[17]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[17].reg2_reg\, + I1 => \^gpio_io_t\(14), + I2 => p_73_in, + I3 => gpio_Data_In(17), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2[17]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2[17]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[17].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1[18]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(13), + I1 => \^gpio_io_t\(13), + I2 => p_73_in, + I3 => gpio_Data_In(18), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1[18]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1[18]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2[18]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[18].reg2_reg\, + I1 => \^gpio_io_t\(13), + I2 => p_73_in, + I3 => gpio_Data_In(18), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2[18]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2[18]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[18].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1[19]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(12), + I1 => \^gpio_io_t\(12), + I2 => p_73_in, + I3 => gpio_Data_In(19), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1[19]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1[19]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2[19]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[19].reg2_reg\, + I1 => \^gpio_io_t\(12), + I2 => p_73_in, + I3 => gpio_Data_In(19), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2[19]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2[19]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[19].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(30), + I1 => \^gpio_io_t\(30), + I2 => p_73_in, + I3 => gpio_Data_In(1), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[1]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[1]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[1].reg2_reg\, + I1 => \^gpio_io_t\(30), + I2 => p_73_in, + I3 => gpio_Data_In(1), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[1]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[1]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[1].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1[20]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(11), + I1 => \^gpio_io_t\(11), + I2 => p_73_in, + I3 => gpio_Data_In(20), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1[20]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1[20]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2[20]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[20].reg2_reg\, + I1 => \^gpio_io_t\(11), + I2 => p_73_in, + I3 => gpio_Data_In(20), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2[20]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2[20]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[20].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1[21]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(10), + I1 => \^gpio_io_t\(10), + I2 => p_73_in, + I3 => gpio_Data_In(21), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1[21]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1[21]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2[21]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[21].reg2_reg\, + I1 => \^gpio_io_t\(10), + I2 => p_73_in, + I3 => gpio_Data_In(21), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2[21]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2[21]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[21].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1[22]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(9), + I1 => \^gpio_io_t\(9), + I2 => p_73_in, + I3 => gpio_Data_In(22), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1[22]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1[22]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2[22]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[22].reg2_reg\, + I1 => \^gpio_io_t\(9), + I2 => p_73_in, + I3 => gpio_Data_In(22), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2[22]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2[22]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[22].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1[23]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(8), + I1 => \^gpio_io_t\(8), + I2 => p_73_in, + I3 => gpio_Data_In(23), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1[23]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1[23]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2[23]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[23].reg2_reg\, + I1 => \^gpio_io_t\(8), + I2 => p_73_in, + I3 => gpio_Data_In(23), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2[23]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2[23]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[23].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1[24]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(7), + I1 => \^gpio_io_t\(7), + I2 => p_73_in, + I3 => gpio_Data_In(24), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1[24]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1[24]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2[24]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[24].reg2_reg\, + I1 => \^gpio_io_t\(7), + I2 => p_73_in, + I3 => gpio_Data_In(24), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2[24]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2[24]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[24].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1[25]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(6), + I1 => \^gpio_io_t\(6), + I2 => p_73_in, + I3 => gpio_Data_In(25), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1[25]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1[25]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2[25]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[25].reg2_reg\, + I1 => \^gpio_io_t\(6), + I2 => p_73_in, + I3 => gpio_Data_In(25), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2[25]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2[25]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[25].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1[26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(5), + I1 => \^gpio_io_t\(5), + I2 => p_73_in, + I3 => gpio_Data_In(26), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1[26]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1[26]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2[26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[26].reg2_reg\, + I1 => \^gpio_io_t\(5), + I2 => p_73_in, + I3 => gpio_Data_In(26), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2[26]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2[26]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[26].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1[27]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(4), + I1 => \^gpio_io_t\(4), + I2 => p_73_in, + I3 => gpio_Data_In(27), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1[27]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1[27]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2[27]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[27].reg2_reg\, + I1 => \^gpio_io_t\(4), + I2 => p_73_in, + I3 => gpio_Data_In(27), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2[27]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2[27]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[27].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1[28]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(3), + I1 => \^gpio_io_t\(3), + I2 => p_73_in, + I3 => gpio_Data_In(28), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1[28]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1[28]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2[28]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[28].reg2_reg\, + I1 => \^gpio_io_t\(3), + I2 => p_73_in, + I3 => gpio_Data_In(28), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2[28]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2[28]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[28].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1[29]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(2), + I1 => \^gpio_io_t\(2), + I2 => p_73_in, + I3 => gpio_Data_In(29), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1[29]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1[29]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2[29]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[29].reg2_reg\, + I1 => \^gpio_io_t\(2), + I2 => p_73_in, + I3 => gpio_Data_In(29), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2[29]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2[29]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[29].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(29), + I1 => \^gpio_io_t\(29), + I2 => p_73_in, + I3 => gpio_Data_In(2), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1[2]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1[2]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[2].reg2_reg\, + I1 => \^gpio_io_t\(29), + I2 => p_73_in, + I3 => gpio_Data_In(2), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2[2]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2[2]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[2].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1[30]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(1), + I1 => \^gpio_io_t\(1), + I2 => p_73_in, + I3 => gpio_Data_In(30), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1[30]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1[30]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2[30]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[30].reg2_reg\, + I1 => \^gpio_io_t\(1), + I2 => p_73_in, + I3 => gpio_Data_In(30), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2[30]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2[30]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[30].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(0), + I1 => \^gpio_io_t\(0), + I2 => p_73_in, + I3 => gpio_Data_In(31), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_2_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_2_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2[31]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[31].reg2_reg\, + I1 => \^gpio_io_t\(0), + I2 => p_73_in, + I3 => gpio_Data_In(31), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2[31]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2[31]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[31].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(28), + I1 => \^gpio_io_t\(28), + I2 => p_73_in, + I3 => gpio_Data_In(3), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1[3]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1[3]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[3].reg2_reg\, + I1 => \^gpio_io_t\(28), + I2 => p_73_in, + I3 => gpio_Data_In(3), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2[3]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2[3]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[3].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(27), + I1 => \^gpio_io_t\(27), + I2 => p_73_in, + I3 => gpio_Data_In(4), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1[4]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1[4]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[4].reg2_reg\, + I1 => \^gpio_io_t\(27), + I2 => p_73_in, + I3 => gpio_Data_In(4), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2[4]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2[4]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[4].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(26), + I1 => \^gpio_io_t\(26), + I2 => p_73_in, + I3 => gpio_Data_In(5), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1[5]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1[5]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[5].reg2_reg\, + I1 => \^gpio_io_t\(26), + I2 => p_73_in, + I3 => gpio_Data_In(5), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2[5]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2[5]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[5].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(25), + I1 => \^gpio_io_t\(25), + I2 => p_73_in, + I3 => gpio_Data_In(6), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1[6]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1[6]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[6].reg2_reg\, + I1 => \^gpio_io_t\(25), + I2 => p_73_in, + I3 => gpio_Data_In(6), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2[6]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2[6]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[6].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(24), + I1 => \^gpio_io_t\(24), + I2 => p_73_in, + I3 => gpio_Data_In(7), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1[7]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1[7]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[7].reg2_reg\, + I1 => \^gpio_io_t\(24), + I2 => p_73_in, + I3 => gpio_Data_In(7), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2[7]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2[7]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[7].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(23), + I1 => \^gpio_io_t\(23), + I2 => p_73_in, + I3 => gpio_Data_In(8), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1[8]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1[8]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[8].reg2_reg\, + I1 => \^gpio_io_t\(23), + I2 => p_73_in, + I3 => gpio_Data_In(8), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2[8]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2[8]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[8].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^gpio_io_o\(22), + I1 => \^gpio_io_t\(22), + I2 => p_73_in, + I3 => gpio_Data_In(9), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1[9]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1[9]_i_1_n_0\, + Q => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE02C2C2" + ) + port map ( + I0 => \^not_dual.allout0_nd.read_reg_gen[9].reg2_reg\, + I1 => \^gpio_io_t\(22), + I2 => p_73_in, + I3 => gpio_Data_In(9), + I4 => p_75_in, + O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2[9]_i_1_n_0\ + ); +\Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2[9]_i_1_n_0\, + Q => \^not_dual.allout0_nd.read_reg_gen[9].reg2_reg\, + R => bus2ip_rnw_i_reg + ); +\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync + port map ( + gpio_io_i(31 downto 0) => gpio_io_i(31 downto 0), + s_axi_aclk => s_axi_aclk, + scndry_vect_out(31) => gpio_io_i_d2(0), + scndry_vect_out(30) => gpio_io_i_d2(1), + scndry_vect_out(29) => gpio_io_i_d2(2), + scndry_vect_out(28) => gpio_io_i_d2(3), + scndry_vect_out(27) => gpio_io_i_d2(4), + scndry_vect_out(26) => gpio_io_i_d2(5), + scndry_vect_out(25) => gpio_io_i_d2(6), + scndry_vect_out(24) => gpio_io_i_d2(7), + scndry_vect_out(23) => gpio_io_i_d2(8), + scndry_vect_out(22) => gpio_io_i_d2(9), + scndry_vect_out(21) => gpio_io_i_d2(10), + scndry_vect_out(20) => gpio_io_i_d2(11), + scndry_vect_out(19) => gpio_io_i_d2(12), + scndry_vect_out(18) => gpio_io_i_d2(13), + scndry_vect_out(17) => gpio_io_i_d2(14), + scndry_vect_out(16) => gpio_io_i_d2(15), + scndry_vect_out(15) => gpio_io_i_d2(16), + scndry_vect_out(14) => gpio_io_i_d2(17), + scndry_vect_out(13) => gpio_io_i_d2(18), + scndry_vect_out(12) => gpio_io_i_d2(19), + scndry_vect_out(11) => gpio_io_i_d2(20), + scndry_vect_out(10) => gpio_io_i_d2(21), + scndry_vect_out(9) => gpio_io_i_d2(22), + scndry_vect_out(8) => gpio_io_i_d2(23), + scndry_vect_out(7) => gpio_io_i_d2(24), + scndry_vect_out(6) => gpio_io_i_d2(25), + scndry_vect_out(5) => gpio_io_i_d2(26), + scndry_vect_out(4) => gpio_io_i_d2(27), + scndry_vect_out(3) => gpio_io_i_d2(28), + scndry_vect_out(2) => gpio_io_i_d2(29), + scndry_vect_out(1) => gpio_io_i_d2(30), + scndry_vect_out(0) => gpio_io_i_d2(31) + ); +\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(0), + Q => gpio_Data_In(0), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(10), + Q => gpio_Data_In(10), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(11), + Q => gpio_Data_In(11), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(12), + Q => gpio_Data_In(12), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(13), + Q => gpio_Data_In(13), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(14), + Q => gpio_Data_In(14), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(15), + Q => gpio_Data_In(15), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(16), + Q => gpio_Data_In(16), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(17), + Q => gpio_Data_In(17), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(18), + Q => gpio_Data_In(18), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(19), + Q => gpio_Data_In(19), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(1), + Q => gpio_Data_In(1), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(20), + Q => gpio_Data_In(20), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(21), + Q => gpio_Data_In(21), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(22), + Q => gpio_Data_In(22), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(23), + Q => gpio_Data_In(23), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(24), + Q => gpio_Data_In(24), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(25), + Q => gpio_Data_In(25), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(26), + Q => gpio_Data_In(26), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(27), + Q => gpio_Data_In(27), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(28), + Q => gpio_Data_In(28), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(29), + Q => gpio_Data_In(29), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(2), + Q => gpio_Data_In(2), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(30), + Q => gpio_Data_In(30), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(31), + Q => gpio_Data_In(31), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(3), + Q => gpio_Data_In(3), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(4), + Q => gpio_Data_In(4), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(5), + Q => gpio_Data_In(5), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(6), + Q => gpio_Data_In(6), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(7), + Q => gpio_Data_In(7), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(8), + Q => gpio_Data_In(8), + R => '0' + ); +\Not_Dual.gpio_Data_In_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2(9), + Q => gpio_Data_In(9), + R => '0' + ); +\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(31), + Q => \^gpio_io_o\(31), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(21), + Q => \^gpio_io_o\(21), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(20), + Q => \^gpio_io_o\(20), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(19), + Q => \^gpio_io_o\(19), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(18), + Q => \^gpio_io_o\(18), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(17), + Q => \^gpio_io_o\(17), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(16), + Q => \^gpio_io_o\(16), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(15), + Q => \^gpio_io_o\(15), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(14), + Q => \^gpio_io_o\(14), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(13), + Q => \^gpio_io_o\(13), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(12), + Q => \^gpio_io_o\(12), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(30), + Q => \^gpio_io_o\(30), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(11), + Q => \^gpio_io_o\(11), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(10), + Q => \^gpio_io_o\(10), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(9), + Q => \^gpio_io_o\(9), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(8), + Q => \^gpio_io_o\(8), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(7), + Q => \^gpio_io_o\(7), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(6), + Q => \^gpio_io_o\(6), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(5), + Q => \^gpio_io_o\(5), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(4), + Q => \^gpio_io_o\(4), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(3), + Q => \^gpio_io_o\(3), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(2), + Q => \^gpio_io_o\(2), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(29), + Q => \^gpio_io_o\(29), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(1), + Q => \^gpio_io_o\(1), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(0), + Q => \^gpio_io_o\(0), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(28), + Q => \^gpio_io_o\(28), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(27), + Q => \^gpio_io_o\(27), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(26), + Q => \^gpio_io_o\(26), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(25), + Q => \^gpio_io_o\(25), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(24), + Q => \^gpio_io_o\(24), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(23), + Q => \^gpio_io_o\(23), + R => SR(0) + ); +\Not_Dual.gpio_Data_Out_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => bus2ip_rnw_i_reg_0(0), + D => s_axi_wdata(22), + Q => \^gpio_io_o\(22), + R => SR(0) + ); +\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(31), + Q => \^gpio_io_t\(31), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(21), + Q => \^gpio_io_t\(21), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[11]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(20), + Q => \^gpio_io_t\(20), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[12]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(19), + Q => \^gpio_io_t\(19), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[13]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(18), + Q => \^gpio_io_t\(18), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[14]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(17), + Q => \^gpio_io_t\(17), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[15]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(16), + Q => \^gpio_io_t\(16), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[16]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(15), + Q => \^gpio_io_t\(15), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[17]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(14), + Q => \^gpio_io_t\(14), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[18]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(13), + Q => \^gpio_io_t\(13), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[19]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(12), + Q => \^gpio_io_t\(12), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(30), + Q => \^gpio_io_t\(30), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[20]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(11), + Q => \^gpio_io_t\(11), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[21]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(10), + Q => \^gpio_io_t\(10), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[22]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(9), + Q => \^gpio_io_t\(9), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[23]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(8), + Q => \^gpio_io_t\(8), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[24]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(7), + Q => \^gpio_io_t\(7), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[25]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(6), + Q => \^gpio_io_t\(6), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[26]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(5), + Q => \^gpio_io_t\(5), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[27]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(4), + Q => \^gpio_io_t\(4), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[28]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(3), + Q => \^gpio_io_t\(3), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[29]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(2), + Q => \^gpio_io_t\(2), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(29), + Q => \^gpio_io_t\(29), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[30]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(1), + Q => \^gpio_io_t\(1), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[31]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(0), + Q => \^gpio_io_t\(0), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(28), + Q => \^gpio_io_t\(28), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(27), + Q => \^gpio_io_t\(27), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(26), + Q => \^gpio_io_t\(26), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(25), + Q => \^gpio_io_t\(25), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(24), + Q => \^gpio_io_t\(24), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(23), + Q => \^gpio_io_t\(23), + S => SR(0) + ); +\Not_Dual.gpio_OE_reg[9]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => E(0), + D => s_axi_wdata(22), + Q => \^gpio_io_t\(22), + S => SR(0) + ); +gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \^gpio_xferack_i\, + Q => \^gpio_xferack_reg\, + R => SR(0) + ); +iGPIO_xferAck_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \^gpio_xferack_reg\, + I1 => bus2ip_cs, + I2 => \^gpio_xferack_i\, + O => iGPIO_xferAck + ); +iGPIO_xferAck_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => iGPIO_xferAck, + Q => \^gpio_xferack_i\, + R => SR(0) + ); +ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^gpio_xferack_i\, + I1 => bus2ip_rnw, + O => ip2bus_rdack_i + ); +ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^gpio_xferack_i\, + I1 => bus2ip_rnw, + O => ip2bus_wrack_i + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is + port ( + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]\ : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_bvalid : out STD_LOGIC; + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC; + p_75_in : out STD_LOGIC; + p_73_in : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arready : out STD_LOGIC; + s_axi_wready : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]_0\ : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + D : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_aclk : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + GPIO_xferAck_i : in STD_LOGIC; + gpio_xferAck_Reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\ : in STD_LOGIC; + ip2bus_rdack_i_D1 : in STD_LOGIC; + ip2bus_wrack_i_D1 : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is + signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_state[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_state_reg_n_0_[0]\ : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[0]\ : signal is "yes"; + signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC; + attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes"; + signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^not_dual.allout0_nd.read_reg_gen[0].reg2_reg[0]\ : STD_LOGIC; + signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 ); + signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC; + signal clear : STD_LOGIC; + signal is_read_i_1_n_0 : STD_LOGIC; + signal is_read_reg_n_0 : STD_LOGIC; + signal is_write_i_1_n_0 : STD_LOGIC; + signal is_write_i_2_n_0 : STD_LOGIC; + signal is_write_reg_n_0 : STD_LOGIC; + signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal p_5_in : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rst_i_1_n_0 : STD_LOGIC; + signal \^s_axi_arready\ : STD_LOGIC; + signal s_axi_bresp_i : STD_LOGIC; + attribute RTL_KEEP of s_axi_bresp_i : signal is "yes"; + signal \^s_axi_bvalid\ : STD_LOGIC; + signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC; + signal s_axi_rresp_i : STD_LOGIC; + attribute RTL_KEEP of s_axi_rresp_i : signal is "yes"; + signal \^s_axi_rvalid\ : STD_LOGIC; + signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC; + signal \^s_axi_wready\ : STD_LOGIC; + signal start2 : STD_LOGIC; + signal start2_i_1_n_0 : STD_LOGIC; + signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \state1__2\ : STD_LOGIC; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[0]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001"; + attribute KEEP : string; + attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes"; + attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[1]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001"; + attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes"; + attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[2]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001"; + attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes"; + attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[3]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001"; + attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \bus2ip_addr_i[2]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \state[1]_i_2\ : label is "soft_lutpair4"; +begin + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]\ <= \^not_dual.allout0_nd.read_reg_gen[0].reg2_reg[0]\; + SR(0) <= \^sr\(0); + s_axi_arready <= \^s_axi_arready\; + s_axi_bvalid <= \^s_axi_bvalid\; + s_axi_rvalid <= \^s_axi_rvalid\; + s_axi_wready <= \^s_axi_wready\; +\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF150015001500" + ) + port map ( + I0 => s_axi_arvalid, + I1 => s_axi_wvalid, + I2 => s_axi_awvalid, + I3 => \FSM_onehot_state_reg_n_0_[0]\, + I4 => \state1__2\, + I5 => \FSM_onehot_state_reg_n_0_[3]\, + O => \FSM_onehot_state[0]_i_1_n_0\ + ); +\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8F88" + ) + port map ( + I0 => s_axi_arvalid, + I1 => \FSM_onehot_state_reg_n_0_[0]\, + I2 => \^s_axi_arready\, + I3 => s_axi_rresp_i, + O => \FSM_onehot_state[1]_i_1_n_0\ + ); +\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800FFFF08000800" + ) + port map ( + I0 => s_axi_wvalid, + I1 => s_axi_awvalid, + I2 => s_axi_arvalid, + I3 => \FSM_onehot_state_reg_n_0_[0]\, + I4 => \^s_axi_wready\, + I5 => s_axi_bresp_i, + O => \FSM_onehot_state[2]_i_1_n_0\ + ); +\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F888F888FFFFF888" + ) + port map ( + I0 => \^s_axi_wready\, + I1 => s_axi_bresp_i, + I2 => s_axi_rresp_i, + I3 => \^s_axi_arready\, + I4 => \FSM_onehot_state_reg_n_0_[3]\, + I5 => \state1__2\, + O => \FSM_onehot_state[3]_i_1_n_0\ + ); +\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => s_axi_bready, + I1 => \^s_axi_bvalid\, + I2 => s_axi_rready, + I3 => \^s_axi_rvalid\, + O => \state1__2\ + ); +\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => \FSM_onehot_state[0]_i_1_n_0\, + Q => \FSM_onehot_state_reg_n_0_[0]\, + S => \^sr\(0) + ); +\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => \FSM_onehot_state[1]_i_1_n_0\, + Q => s_axi_rresp_i, + R => \^sr\(0) + ); +\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => \FSM_onehot_state[2]_i_1_n_0\, + Q => s_axi_bresp_i, + R => \^sr\(0) + ); +\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => \FSM_onehot_state[3]_i_1_n_0\, + Q => \FSM_onehot_state_reg_n_0_[3]\, + R => \^sr\(0) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + O => plusOp(0) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + O => plusOp(1) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + O => plusOp(2) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => state(0), + I1 => state(1), + O => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), + O => plusOp(3) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => plusOp(0), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => plusOp(1), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => plusOp(2), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => plusOp(3), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), + R => clear + ); +I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder + port map ( + D(31 downto 0) => D(31 downto 0), + E(0) => E(0), + GPIO_xferAck_i => GPIO_xferAck_i, + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]_0\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\, + \Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0), + Q => start2, + \bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(0), + \bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5), + \bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6), + bus2ip_rnw_i_reg => \^not_dual.allout0_nd.read_reg_gen[0].reg2_reg[0]\, + gpio_xferAck_Reg => gpio_xferAck_Reg, + ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, + ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, + is_read_reg => is_read_reg_n_0, + is_write_reg => is_write_reg_n_0, + p_73_in => p_73_in, + p_75_in => p_75_in, + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_arready => \^s_axi_arready\, + s_axi_wready => \^s_axi_wready\ + ); +\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => s_axi_araddr(0), + I1 => s_axi_awaddr(0), + I2 => s_axi_arvalid, + O => \bus2ip_addr_i[2]_i_1_n_0\ + ); +\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => s_axi_araddr(1), + I1 => s_axi_awaddr(1), + I2 => s_axi_arvalid, + O => \bus2ip_addr_i[3]_i_1_n_0\ + ); +\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000EA" + ) + port map ( + I0 => s_axi_arvalid, + I1 => s_axi_awvalid, + I2 => s_axi_wvalid, + I3 => state(1), + I4 => state(0), + O => \bus2ip_addr_i[8]_i_1_n_0\ + ); +\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => s_axi_araddr(2), + I1 => s_axi_awaddr(2), + I2 => s_axi_arvalid, + O => \bus2ip_addr_i[8]_i_2_n_0\ + ); +\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[2]_i_1_n_0\, + Q => bus2ip_addr(6), + R => \^sr\(0) + ); +\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[3]_i_1_n_0\, + Q => bus2ip_addr(5), + R => \^sr\(0) + ); +\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[8]_i_2_n_0\, + Q => bus2ip_addr(0), + R => \^sr\(0) + ); +bus2ip_rnw_i_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => s_axi_arvalid, + Q => \^not_dual.allout0_nd.read_reg_gen[0].reg2_reg[0]\, + R => \^sr\(0) + ); +is_read_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"8BBB8888" + ) + port map ( + I0 => s_axi_arvalid, + I1 => \FSM_onehot_state_reg_n_0_[0]\, + I2 => \state1__2\, + I3 => \FSM_onehot_state_reg_n_0_[3]\, + I4 => is_read_reg_n_0, + O => is_read_i_1_n_0 + ); +is_read_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => is_read_i_1_n_0, + Q => is_read_reg_n_0, + R => \^sr\(0) + ); +is_write_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"2000FFFF20000000" + ) + port map ( + I0 => \FSM_onehot_state_reg_n_0_[0]\, + I1 => s_axi_arvalid, + I2 => s_axi_awvalid, + I3 => s_axi_wvalid, + I4 => is_write_i_2_n_0, + I5 => is_write_reg_n_0, + O => is_write_i_1_n_0 + ); +is_write_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFEAEAEAAAAAAAAA" + ) + port map ( + I0 => \FSM_onehot_state_reg_n_0_[0]\, + I1 => s_axi_bready, + I2 => \^s_axi_bvalid\, + I3 => s_axi_rready, + I4 => \^s_axi_rvalid\, + I5 => \FSM_onehot_state_reg_n_0_[3]\, + O => is_write_i_2_n_0 + ); +is_write_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => is_write_i_1_n_0, + Q => is_write_reg_n_0, + R => \^sr\(0) + ); +rst_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => s_axi_aresetn, + O => rst_i_1_n_0 + ); +rst_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => rst_i_1_n_0, + Q => \^sr\(0), + R => '0' + ); +s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"08FF0808" + ) + port map ( + I0 => \^s_axi_wready\, + I1 => state(1), + I2 => state(0), + I3 => s_axi_bready, + I4 => \^s_axi_bvalid\, + O => s_axi_bvalid_i_i_1_n_0 + ); +s_axi_bvalid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_axi_bvalid_i_i_1_n_0, + Q => \^s_axi_bvalid\, + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(0), + Q => s_axi_rdata(0), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(10), + Q => s_axi_rdata(10), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(11), + Q => s_axi_rdata(11), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(12), + Q => s_axi_rdata(12), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(13), + Q => s_axi_rdata(13), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(14), + Q => s_axi_rdata(14), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(15), + Q => s_axi_rdata(15), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(16), + Q => s_axi_rdata(16), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(17), + Q => s_axi_rdata(17), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(18), + Q => s_axi_rdata(18), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(19), + Q => s_axi_rdata(19), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(1), + Q => s_axi_rdata(1), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(20), + Q => s_axi_rdata(20), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(21), + Q => s_axi_rdata(21), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(22), + Q => s_axi_rdata(22), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(23), + Q => s_axi_rdata(23), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(24), + Q => s_axi_rdata(24), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(25), + Q => s_axi_rdata(25), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(26), + Q => s_axi_rdata(26), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(27), + Q => s_axi_rdata(27), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(28), + Q => s_axi_rdata(28), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(29), + Q => s_axi_rdata(29), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(2), + Q => s_axi_rdata(2), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(30), + Q => s_axi_rdata(30), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(31), + Q => s_axi_rdata(31), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(3), + Q => s_axi_rdata(3), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(4), + Q => s_axi_rdata(4), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(5), + Q => s_axi_rdata(5), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(6), + Q => s_axi_rdata(6), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(7), + Q => s_axi_rdata(7), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(8), + Q => s_axi_rdata(8), + R => \^sr\(0) + ); +\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => s_axi_rresp_i, + D => Q(9), + Q => s_axi_rdata(9), + R => \^sr\(0) + ); +s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"08FF0808" + ) + port map ( + I0 => \^s_axi_arready\, + I1 => state(0), + I2 => state(1), + I3 => s_axi_rready, + I4 => \^s_axi_rvalid\, + O => s_axi_rvalid_i_i_1_n_0 + ); +s_axi_rvalid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_axi_rvalid_i_i_1_n_0, + Q => \^s_axi_rvalid\, + R => \^sr\(0) + ); +start2_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000F8" + ) + port map ( + I0 => s_axi_awvalid, + I1 => s_axi_wvalid, + I2 => s_axi_arvalid, + I3 => state(1), + I4 => state(0), + O => start2_i_1_n_0 + ); +start2_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => start2_i_1_n_0, + Q => start2, + R => \^sr\(0) + ); +\state[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"77FC44FC" + ) + port map ( + I0 => \state1__2\, + I1 => state(0), + I2 => s_axi_arvalid, + I3 => state(1), + I4 => \^s_axi_wready\, + O => p_0_out(0) + ); +\state[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"55FFFF0C5500FF0C" + ) + port map ( + I0 => \state1__2\, + I1 => p_5_in, + I2 => s_axi_arvalid, + I3 => state(1), + I4 => state(0), + I5 => \^s_axi_arready\, + O => p_0_out(1) + ); +\state[1]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => s_axi_awvalid, + I1 => s_axi_wvalid, + O => p_5_in + ); +\state_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => p_0_out(0), + Q => state(0), + R => \^sr\(0) + ); +\state_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => p_0_out(1), + Q => state(1), + R => \^sr\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is + port ( + bus2ip_reset : out STD_LOGIC; + bus2ip_rnw : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_bvalid : out STD_LOGIC; + bus2ip_cs : out STD_LOGIC; + p_75_in : out STD_LOGIC; + p_73_in : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arready : out STD_LOGIC; + s_axi_wready : out STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]\ : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + D : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_aclk : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + GPIO_xferAck_i : in STD_LOGIC; + gpio_xferAck_Reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\ : in STD_LOGIC; + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\ : in STD_LOGIC; + ip2bus_rdack_i_D1 : in STD_LOGIC; + ip2bus_wrack_i_D1 : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is +begin +I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment + port map ( + D(31 downto 0) => D(31 downto 0), + E(0) => E(0), + GPIO_xferAck_i => GPIO_xferAck_i, + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]\ => bus2ip_rnw, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]_0\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\, + \Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0), + Q(31 downto 0) => Q(31 downto 0), + SR(0) => bus2ip_reset, + gpio_xferAck_Reg => gpio_xferAck_Reg, + ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, + ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, + p_73_in => p_73_in, + p_75_in => p_75_in, + s_axi_aclk => s_axi_aclk, + s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0), + s_axi_aresetn => s_axi_aresetn, + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0), + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_rready => s_axi_rready, + s_axi_rvalid => s_axi_rvalid, + s_axi_wready => s_axi_wready, + s_axi_wvalid => s_axi_wvalid + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + ip2intc_irpt : out STD_LOGIC; + gpio_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + attribute C_ALL_INPUTS : integer; + attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; + attribute C_ALL_INPUTS_2 : integer; + attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; + attribute C_ALL_OUTPUTS : integer; + attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; + attribute C_ALL_OUTPUTS_2 : integer; + attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; + attribute C_DOUT_DEFAULT : integer; + attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; + attribute C_DOUT_DEFAULT_2 : integer; + attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "kintex7"; + attribute C_GPIO2_WIDTH : integer; + attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32; + attribute C_GPIO_WIDTH : integer; + attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32; + attribute C_INTERRUPT_PRESENT : integer; + attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; + attribute C_IS_DUAL : integer; + attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; + attribute C_S_AXI_ADDR_WIDTH : integer; + attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9; + attribute C_S_AXI_DATA_WIDTH : integer; + attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32; + attribute C_TRI_DEFAULT : integer; + attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1; + attribute C_TRI_DEFAULT_2 : integer; + attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes"; + attribute ip_group : string; + attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is + signal \\ : STD_LOGIC; + signal \\ : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_8 : STD_LOGIC; + signal GPIO_xferAck_i : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\ : STD_LOGIC; + signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\ : STD_LOGIC; + signal bus2ip_cs : STD_LOGIC; + signal bus2ip_reset : STD_LOGIC; + signal bus2ip_rnw : STD_LOGIC; + signal gpio_xferAck_Reg : STD_LOGIC; + signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 ); + signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 ); + signal ip2bus_rdack_i : STD_LOGIC; + signal ip2bus_rdack_i_D1 : STD_LOGIC; + signal ip2bus_wrack_i : STD_LOGIC; + signal ip2bus_wrack_i_D1 : STD_LOGIC; + signal p_73_in : STD_LOGIC; + signal p_75_in : STD_LOGIC; + signal \^s_axi_wready\ : STD_LOGIC; + attribute sigis : string; + attribute sigis of ip2intc_irpt : signal is "INTR_LEVEL_HIGH"; + attribute max_fanout : string; + attribute max_fanout of s_axi_aclk : signal is "10000"; + attribute sigis of s_axi_aclk : signal is "Clk"; + attribute max_fanout of s_axi_aresetn : signal is "10000"; + attribute sigis of s_axi_aresetn : signal is "Rst"; +begin + gpio2_io_o(31) <= \\; + gpio2_io_o(30) <= \\; + gpio2_io_o(29) <= \\; + gpio2_io_o(28) <= \\; + gpio2_io_o(27) <= \\; + gpio2_io_o(26) <= \\; + gpio2_io_o(25) <= \\; + gpio2_io_o(24) <= \\; + gpio2_io_o(23) <= \\; + gpio2_io_o(22) <= \\; + gpio2_io_o(21) <= \\; + gpio2_io_o(20) <= \\; + gpio2_io_o(19) <= \\; + gpio2_io_o(18) <= \\; + gpio2_io_o(17) <= \\; + gpio2_io_o(16) <= \\; + gpio2_io_o(15) <= \\; + gpio2_io_o(14) <= \\; + gpio2_io_o(13) <= \\; + gpio2_io_o(12) <= \\; + gpio2_io_o(11) <= \\; + gpio2_io_o(10) <= \\; + gpio2_io_o(9) <= \\; + gpio2_io_o(8) <= \\; + gpio2_io_o(7) <= \\; + gpio2_io_o(6) <= \\; + gpio2_io_o(5) <= \\; + gpio2_io_o(4) <= \\; + gpio2_io_o(3) <= \\; + gpio2_io_o(2) <= \\; + gpio2_io_o(1) <= \\; + gpio2_io_o(0) <= \\; + gpio2_io_t(31) <= \\; + gpio2_io_t(30) <= \\; + gpio2_io_t(29) <= \\; + gpio2_io_t(28) <= \\; + gpio2_io_t(27) <= \\; + gpio2_io_t(26) <= \\; + gpio2_io_t(25) <= \\; + gpio2_io_t(24) <= \\; + gpio2_io_t(23) <= \\; + gpio2_io_t(22) <= \\; + gpio2_io_t(21) <= \\; + gpio2_io_t(20) <= \\; + gpio2_io_t(19) <= \\; + gpio2_io_t(18) <= \\; + gpio2_io_t(17) <= \\; + gpio2_io_t(16) <= \\; + gpio2_io_t(15) <= \\; + gpio2_io_t(14) <= \\; + gpio2_io_t(13) <= \\; + gpio2_io_t(12) <= \\; + gpio2_io_t(11) <= \\; + gpio2_io_t(10) <= \\; + gpio2_io_t(9) <= \\; + gpio2_io_t(8) <= \\; + gpio2_io_t(7) <= \\; + gpio2_io_t(6) <= \\; + gpio2_io_t(5) <= \\; + gpio2_io_t(4) <= \\; + gpio2_io_t(3) <= \\; + gpio2_io_t(2) <= \\; + gpio2_io_t(1) <= \\; + gpio2_io_t(0) <= \\; + ip2intc_irpt <= \\; + s_axi_awready <= \^s_axi_wready\; + s_axi_bresp(1) <= \\; + s_axi_bresp(0) <= \\; + s_axi_rresp(1) <= \\; + s_axi_rresp(0) <= \\; + s_axi_wready <= \^s_axi_wready\; +AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif + port map ( + D(31) => ip2bus_data(0), + D(30) => ip2bus_data(1), + D(29) => ip2bus_data(2), + D(28) => ip2bus_data(3), + D(27) => ip2bus_data(4), + D(26) => ip2bus_data(5), + D(25) => ip2bus_data(6), + D(24) => ip2bus_data(7), + D(23) => ip2bus_data(8), + D(22) => ip2bus_data(9), + D(21) => ip2bus_data(10), + D(20) => ip2bus_data(11), + D(19) => ip2bus_data(12), + D(18) => ip2bus_data(13), + D(17) => ip2bus_data(14), + D(16) => ip2bus_data(15), + D(15) => ip2bus_data(16), + D(14) => ip2bus_data(17), + D(13) => ip2bus_data(18), + D(12) => ip2bus_data(19), + D(11) => ip2bus_data(20), + D(10) => ip2bus_data(21), + D(9) => ip2bus_data(22), + D(8) => ip2bus_data(23), + D(7) => ip2bus_data(24), + D(6) => ip2bus_data(25), + D(5) => ip2bus_data(26), + D(4) => ip2bus_data(27), + D(3) => ip2bus_data(28), + D(2) => ip2bus_data(29), + D(1) => ip2bus_data(30), + D(0) => ip2bus_data(31), + E(0) => AXI_LITE_IPIF_I_n_7, + GPIO_xferAck_i => GPIO_xferAck_i, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0]\ => AXI_LITE_IPIF_I_n_11, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\, + \Not_Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_8, + Q(31) => ip2bus_data_i_D1(0), + Q(30) => ip2bus_data_i_D1(1), + Q(29) => ip2bus_data_i_D1(2), + Q(28) => ip2bus_data_i_D1(3), + Q(27) => ip2bus_data_i_D1(4), + Q(26) => ip2bus_data_i_D1(5), + Q(25) => ip2bus_data_i_D1(6), + Q(24) => ip2bus_data_i_D1(7), + Q(23) => ip2bus_data_i_D1(8), + Q(22) => ip2bus_data_i_D1(9), + Q(21) => ip2bus_data_i_D1(10), + Q(20) => ip2bus_data_i_D1(11), + Q(19) => ip2bus_data_i_D1(12), + Q(18) => ip2bus_data_i_D1(13), + Q(17) => ip2bus_data_i_D1(14), + Q(16) => ip2bus_data_i_D1(15), + Q(15) => ip2bus_data_i_D1(16), + Q(14) => ip2bus_data_i_D1(17), + Q(13) => ip2bus_data_i_D1(18), + Q(12) => ip2bus_data_i_D1(19), + Q(11) => ip2bus_data_i_D1(20), + Q(10) => ip2bus_data_i_D1(21), + Q(9) => ip2bus_data_i_D1(22), + Q(8) => ip2bus_data_i_D1(23), + Q(7) => ip2bus_data_i_D1(24), + Q(6) => ip2bus_data_i_D1(25), + Q(5) => ip2bus_data_i_D1(26), + Q(4) => ip2bus_data_i_D1(27), + Q(3) => ip2bus_data_i_D1(28), + Q(2) => ip2bus_data_i_D1(29), + Q(1) => ip2bus_data_i_D1(30), + Q(0) => ip2bus_data_i_D1(31), + bus2ip_cs => bus2ip_cs, + bus2ip_reset => bus2ip_reset, + bus2ip_rnw => bus2ip_rnw, + gpio_xferAck_Reg => gpio_xferAck_Reg, + ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, + ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, + p_73_in => p_73_in, + p_75_in => p_75_in, + s_axi_aclk => s_axi_aclk, + s_axi_araddr(2) => s_axi_araddr(8), + s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2), + s_axi_aresetn => s_axi_aresetn, + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(2) => s_axi_awaddr(8), + s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2), + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_rready => s_axi_rready, + s_axi_rvalid => s_axi_rvalid, + s_axi_wready => \^s_axi_wready\, + s_axi_wvalid => s_axi_wvalid + ); +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +VCC: unisim.vcomponents.VCC + port map ( + P => \\ + ); +gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core + port map ( + E(0) => AXI_LITE_IPIF_I_n_7, + GPIO_xferAck_i => GPIO_xferAck_i, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].reg2_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg1_reg\, + \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].reg2_reg\, + SR(0) => bus2ip_reset, + bus2ip_cs => bus2ip_cs, + bus2ip_rnw => bus2ip_rnw, + bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_11, + bus2ip_rnw_i_reg_0(0) => AXI_LITE_IPIF_I_n_8, + gpio_io_i(31 downto 0) => gpio_io_i(31 downto 0), + gpio_io_o(31 downto 0) => gpio_io_o(31 downto 0), + gpio_io_t(31 downto 0) => gpio_io_t(31 downto 0), + gpio_xferAck_Reg => gpio_xferAck_Reg, + ip2bus_rdack_i => ip2bus_rdack_i, + ip2bus_wrack_i => ip2bus_wrack_i, + p_73_in => p_73_in, + p_75_in => p_75_in, + s_axi_aclk => s_axi_aclk, + s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0) + ); +\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(0), + Q => ip2bus_data_i_D1(0), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(10), + Q => ip2bus_data_i_D1(10), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(11), + Q => ip2bus_data_i_D1(11), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(12), + Q => ip2bus_data_i_D1(12), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(13), + Q => ip2bus_data_i_D1(13), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(14), + Q => ip2bus_data_i_D1(14), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(15), + Q => ip2bus_data_i_D1(15), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(16), + Q => ip2bus_data_i_D1(16), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(17), + Q => ip2bus_data_i_D1(17), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(18), + Q => ip2bus_data_i_D1(18), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(19), + Q => ip2bus_data_i_D1(19), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(1), + Q => ip2bus_data_i_D1(1), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(20), + Q => ip2bus_data_i_D1(20), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(21), + Q => ip2bus_data_i_D1(21), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(22), + Q => ip2bus_data_i_D1(22), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(23), + Q => ip2bus_data_i_D1(23), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(24), + Q => ip2bus_data_i_D1(24), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(25), + Q => ip2bus_data_i_D1(25), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(26), + Q => ip2bus_data_i_D1(26), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(27), + Q => ip2bus_data_i_D1(27), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(28), + Q => ip2bus_data_i_D1(28), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(29), + Q => ip2bus_data_i_D1(29), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(2), + Q => ip2bus_data_i_D1(2), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(30), + Q => ip2bus_data_i_D1(30), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(31), + Q => ip2bus_data_i_D1(31), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(3), + Q => ip2bus_data_i_D1(3), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(4), + Q => ip2bus_data_i_D1(4), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(5), + Q => ip2bus_data_i_D1(5), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(6), + Q => ip2bus_data_i_D1(6), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(7), + Q => ip2bus_data_i_D1(7), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(8), + Q => ip2bus_data_i_D1(8), + R => bus2ip_reset + ); +\ip2bus_data_i_D1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data(9), + Q => ip2bus_data_i_D1(9), + R => bus2ip_reset + ); +ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_rdack_i, + Q => ip2bus_rdack_i_D1, + R => bus2ip_reset + ); +ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_wrack_i, + Q => ip2bus_wrack_i_D1, + R => bus2ip_reset + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + gpio_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_axi_gpio_0_0,axi_gpio,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2018.2"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC; + signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute C_ALL_INPUTS : integer; + attribute C_ALL_INPUTS of U0 : label is 0; + attribute C_ALL_INPUTS_2 : integer; + attribute C_ALL_INPUTS_2 of U0 : label is 0; + attribute C_ALL_OUTPUTS : integer; + attribute C_ALL_OUTPUTS of U0 : label is 0; + attribute C_ALL_OUTPUTS_2 : integer; + attribute C_ALL_OUTPUTS_2 of U0 : label is 0; + attribute C_DOUT_DEFAULT : integer; + attribute C_DOUT_DEFAULT of U0 : label is 0; + attribute C_DOUT_DEFAULT_2 : integer; + attribute C_DOUT_DEFAULT_2 of U0 : label is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "kintex7"; + attribute C_GPIO2_WIDTH : integer; + attribute C_GPIO2_WIDTH of U0 : label is 32; + attribute C_GPIO_WIDTH : integer; + attribute C_GPIO_WIDTH of U0 : label is 32; + attribute C_INTERRUPT_PRESENT : integer; + attribute C_INTERRUPT_PRESENT of U0 : label is 0; + attribute C_IS_DUAL : integer; + attribute C_IS_DUAL of U0 : label is 0; + attribute C_S_AXI_ADDR_WIDTH : integer; + attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9; + attribute C_S_AXI_DATA_WIDTH : integer; + attribute C_S_AXI_DATA_WIDTH of U0 : label is 32; + attribute C_TRI_DEFAULT : integer; + attribute C_TRI_DEFAULT of U0 : label is -1; + attribute C_TRI_DEFAULT_2 : integer; + attribute C_TRI_DEFAULT_2 of U0 : label is -1; + attribute downgradeipidentifiedwarnings of U0 : label is "yes"; + attribute ip_group : string; + attribute ip_group of U0 : label is "LOGICORE"; + attribute x_interface_info : string; + attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0"; + attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; + attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW"; + attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; + attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; + attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; + attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; + attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; + attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; + attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; + attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; + attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; + attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; + attribute x_interface_info of gpio_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_I"; + attribute x_interface_parameter of gpio_io_i : signal is "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE"; + attribute x_interface_info of gpio_io_o : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; + attribute x_interface_info of gpio_io_t : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_T"; + attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; + attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; + attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; + attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; + attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; + attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; + attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; + attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; +begin +U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio + port map ( + gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000", + gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0), + gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0), + gpio_io_i(31 downto 0) => gpio_io_i(31 downto 0), + gpio_io_o(31 downto 0) => gpio_io_o(31 downto 0), + gpio_io_t(31 downto 0) => gpio_io_t(31 downto 0), + ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED, + s_axi_aclk => s_axi_aclk, + s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0), + s_axi_aresetn => s_axi_aresetn, + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0), + s_axi_awready => s_axi_awready, + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_rready => s_axi_rready, + s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), + s_axi_rvalid => s_axi_rvalid, + s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), + s_axi_wready => s_axi_wready, + s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), + s_axi_wvalid => s_axi_wvalid + ); +end STRUCTURE; diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_stub.v b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_stub.v new file mode 100644 index 0000000..20271fd --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_stub.v @@ -0,0 +1,44 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 17:10:34 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_0_0_stub.v +// Design : design_1_axi_gpio_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "axi_gpio,Vivado 2018.2" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, + s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, + s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, + s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t) +/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[31:0],gpio_io_o[31:0],gpio_io_t[31:0]" */; + input s_axi_aclk; + input s_axi_aresetn; + input [8:0]s_axi_awaddr; + input s_axi_awvalid; + output s_axi_awready; + input [31:0]s_axi_wdata; + input [3:0]s_axi_wstrb; + input s_axi_wvalid; + output s_axi_wready; + output [1:0]s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + input [8:0]s_axi_araddr; + input s_axi_arvalid; + output s_axi_arready; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rvalid; + input s_axi_rready; + input [31:0]gpio_io_i; + output [31:0]gpio_io_o; + output [31:0]gpio_io_t; +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_stub.vhdl b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_stub.vhdl new file mode 100644 index 0000000..39d8b7c --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/design_1_axi_gpio_0_0_stub.vhdl @@ -0,0 +1,51 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 17:10:34 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_0_0_stub.vhdl +-- Design : design_1_axi_gpio_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + gpio_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[31:0],gpio_io_o[31:0],gpio_io_t[31:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2018.2"; +begin +end; diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/fdc082bfb7d23a9e.xci b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/fdc082bfb7d23a9e.xci new file mode 100644 index 0000000..74df734 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/fdc082bfb7d23a9e.xci @@ -0,0 +1,54 @@ + + + xilinx.com + ipcache + fdc082bfb7d23a9e + 0 + + + design_1_axi_gpio_0_0 + + + 100000000 + 100000000 + 0 + 0 + 0 + 0 + 0x00000000 + 0x00000000 + 32 + 32 + 0 + 0 + 0xFFFFFFFF + 0xFFFFFFFF + design_1_axi_gpio_0_0 + Custom + Custom + false + kintex7 + + xc7k160t + ffg676 + VERILOG + + MIXED + -2 + + TRUE + TRUE + fdc082bfb7d23a9e + 46e72df7 + IP_Unknown + 19 + TRUE + . + + . + 2018.2 + GLOBAL + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/stats.txt b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/stats.txt new file mode 100644 index 0000000..8433b0a --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/ip/2018.2/fdc082bfb7d23a9e/stats.txt @@ -0,0 +1,4 @@ +NumberHits:0 +Timestamp: Sun Jun 28 09:10:34 UTC 2020 +VLNV: xilinx.com:ip:axi_gpio:2.0 +SynthRuntime: 33 diff --git a/axi_bus_demo/prj/axi_bus_demo.cache/wt/gui_handlers.wdf b/axi_bus_demo/prj/axi_bus_demo.cache/wt/gui_handlers.wdf new file mode 100644 index 0000000..f211eb5 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.cache/wt/gui_handlers.wdf @@ -0,0 +1,65 @@ +version:1 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+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/axi_bus_demo/prj/axi_bus_demo.hw/axi_bus_demo.lpr b/axi_bus_demo/prj/axi_bus_demo.hw/axi_bus_demo.lpr new file mode 100644 index 0000000..68b7fe8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.hw/axi_bus_demo.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.hw/hw_1/hw.xml b/axi_bus_demo/prj/axi_bus_demo.hw/hw_1/hw.xml new file mode 100644 index 0000000..d9131ca --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.hw/hw_1/hw.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd new file mode 100644 index 0000000..a4f2370 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd @@ -0,0 +1,209 @@ +-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_gpio:2.0 +-- IP Revision: 19 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY axi_gpio_v2_0_19; +USE axi_gpio_v2_0_19.axi_gpio; + +ENTITY design_1_axi_gpio_0_0 IS + PORT ( + s_axi_aclk : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END design_1_axi_gpio_0_0; + +ARCHITECTURE design_1_axi_gpio_0_0_arch OF design_1_axi_gpio_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axi_gpio IS + GENERIC ( + C_FAMILY : STRING; + C_S_AXI_ADDR_WIDTH : INTEGER; + C_S_AXI_DATA_WIDTH : INTEGER; + C_GPIO_WIDTH : INTEGER; + C_GPIO2_WIDTH : INTEGER; + C_ALL_INPUTS : INTEGER; + C_ALL_INPUTS_2 : INTEGER; + C_ALL_OUTPUTS : INTEGER; + C_ALL_OUTPUTS_2 : INTEGER; + C_INTERRUPT_PRESENT : INTEGER; + C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_IS_DUAL : INTEGER; + C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + PORT ( + s_axi_aclk : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + ip2intc_irpt : OUT STD_LOGIC; + gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + END COMPONENT axi_gpio; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T"; + ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; + ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE"; + ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0, NUM_READ_THREADS 1, NUM_WRITE_THRE" & +"ADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; +BEGIN + U0 : axi_gpio + GENERIC MAP ( + C_FAMILY => "kintex7", + C_S_AXI_ADDR_WIDTH => 9, + C_S_AXI_DATA_WIDTH => 32, + C_GPIO_WIDTH => 32, + C_GPIO2_WIDTH => 32, + C_ALL_INPUTS => 0, + C_ALL_INPUTS_2 => 0, + C_ALL_OUTPUTS => 0, + C_ALL_OUTPUTS_2 => 0, + C_INTERRUPT_PRESENT => 0, + C_DOUT_DEFAULT => X"00000000", + C_TRI_DEFAULT => X"FFFFFFFF", + C_IS_DUAL => 0, + C_DOUT_DEFAULT_2 => X"00000000", + C_TRI_DEFAULT_2 => X"FFFFFFFF" + ) + PORT MAP ( + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_awready => s_axi_awready, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + gpio_io_i => gpio_io_i, + gpio_io_o => gpio_io_o, + gpio_io_t => gpio_io_t, + gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)) + ); +END design_1_axi_gpio_0_0_arch; diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v new file mode 100644 index 0000000..d99b83f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v @@ -0,0 +1,153 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:user:xjtag_axi:1.0 +// IP Revision: 2 + +`timescale 1ns/1ps + +(* IP_DEFINITION_SOURCE = "package_project" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xjtag_axi_0_0 ( + m00_axi_aclk, + m00_axi_aresetn, + m00_axi_awaddr, + m00_axi_awprot, + m00_axi_awvalid, + m00_axi_awready, + m00_axi_wdata, + m00_axi_wstrb, + m00_axi_wvalid, + m00_axi_wready, + m00_axi_bresp, + m00_axi_bvalid, + m00_axi_bready, + m00_axi_araddr, + m00_axi_arprot, + m00_axi_arvalid, + m00_axi_arready, + m00_axi_rdata, + m00_axi_rresp, + m00_axi_rvalid, + m00_axi_rready +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_BUSIF m00_axi, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m00_axi_aclk CLK" *) +input wire m00_axi_aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m00_axi_aresetn RST" *) +input wire m00_axi_aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWADDR" *) +output wire [31 : 0] m00_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWPROT" *) +output wire [2 : 0] m00_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWVALID" *) +output wire m00_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWREADY" *) +input wire m00_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WDATA" *) +output wire [31 : 0] m00_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WSTRB" *) +output wire [3 : 0] m00_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WVALID" *) +output wire m00_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WREADY" *) +input wire m00_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BRESP" *) +input wire [1 : 0] m00_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BVALID" *) +input wire m00_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BREADY" *) +output wire m00_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARADDR" *) +output wire [31 : 0] m00_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARPROT" *) +output wire [2 : 0] m00_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARVALID" *) +output wire m00_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARREADY" *) +input wire m00_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RDATA" *) +input wire [31 : 0] m00_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RRESP" *) +input wire [1 : 0] m00_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RVALID" *) +input wire m00_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0, NUM_READ_THREADS 1, NUM_WRITE_T\ +HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RREADY" *) +output wire m00_axi_rready; + + xjtag_axi #( + .JTAG_SEL(3) + ) inst ( + .m00_axi_aclk(m00_axi_aclk), + .m00_axi_aresetn(m00_axi_aresetn), + .m00_axi_awaddr(m00_axi_awaddr), + .m00_axi_awprot(m00_axi_awprot), + .m00_axi_awvalid(m00_axi_awvalid), + .m00_axi_awready(m00_axi_awready), + .m00_axi_wdata(m00_axi_wdata), + .m00_axi_wstrb(m00_axi_wstrb), + .m00_axi_wvalid(m00_axi_wvalid), + .m00_axi_wready(m00_axi_wready), + .m00_axi_bresp(m00_axi_bresp), + .m00_axi_bvalid(m00_axi_bvalid), + .m00_axi_bready(m00_axi_bready), + .m00_axi_araddr(m00_axi_araddr), + .m00_axi_arprot(m00_axi_arprot), + .m00_axi_arvalid(m00_axi_arvalid), + .m00_axi_arready(m00_axi_arready), + .m00_axi_rdata(m00_axi_rdata), + .m00_axi_rresp(m00_axi_rresp), + .m00_axi_rvalid(m00_axi_rvalid), + .m00_axi_rready(m00_axi_rready) + ); +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/ipshared/2284/src/xjtag_axi.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/ipshared/2284/src/xjtag_axi.v new file mode 100644 index 0000000..2a4ec61 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/ipshared/2284/src/xjtag_axi.v @@ -0,0 +1,39 @@ + +`timescale 1 ns / 1 ps + + module xjtag_axi # + ( + parameter JTAG_SEL =3 + + ) + ( + // Users to add ports here + // Ports of Axi Master Bus Interface M00_AXI + //input wire m00_axi_init_axi_txn, + //output wire m00_axi_error, + //output wire m00_axi_txn_done, + input wire m00_axi_aclk, + input wire m00_axi_aresetn, + output wire [31 : 0] m00_axi_awaddr, + output wire [2 : 0] m00_axi_awprot, + output wire m00_axi_awvalid, + input wire m00_axi_awready, + output wire [31 : 0] m00_axi_wdata, + output wire [3 : 0] m00_axi_wstrb, + output wire m00_axi_wvalid, + input wire m00_axi_wready, + input wire [1 : 0] m00_axi_bresp, + input wire m00_axi_bvalid, + output wire m00_axi_bready, + output wire [31 : 0] m00_axi_araddr, + output wire [2 : 0] m00_axi_arprot, + output wire m00_axi_arvalid, + input wire m00_axi_arready, + input wire [31 : 0] m00_axi_rdata, + input wire [1 : 0] m00_axi_rresp, + input wire m00_axi_rvalid, + output wire m00_axi_rready + ); + + + endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/sim/design_1.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/sim/design_1.v new file mode 100644 index 0000000..80e6e94 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/bd/design_1/sim/design_1.v @@ -0,0 +1,96 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +//Date : Tue Jun 30 17:32:55 2020 +//Host : PC2018 running 64-bit Service Pack 1 (build 7601) +//Command : generate_target design_1.bd +//Design : design_1 +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}" *) (* HW_HANDOFF = "design_1.hwdef" *) +module design_1 + (clk, + gpio_in, + gpio_io_t_0, + gpio_out, + rstn); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_RESET rstn, CLK_DOMAIN design_1_m00_axi_aclk_0, FREQ_HZ 100000000, PHASE 0.000" *) input clk; + input [31:0]gpio_in; + output [31:0]gpio_io_t_0; + output [31:0]gpio_out; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RSTN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RSTN, POLARITY ACTIVE_LOW" *) input rstn; + + wire [31:0]axi_gpio_0_gpio_io_o; + wire [31:0]axi_gpio_0_gpio_io_t; + wire [31:0]gpio_io_i_0_1; + wire m00_axi_aclk_0_1; + wire m00_axi_aresetn_0_1; + wire [31:0]xjtag_axi_0_m00_axi_ARADDR; + wire xjtag_axi_0_m00_axi_ARREADY; + wire xjtag_axi_0_m00_axi_ARVALID; + wire [31:0]xjtag_axi_0_m00_axi_AWADDR; + wire xjtag_axi_0_m00_axi_AWREADY; + wire xjtag_axi_0_m00_axi_AWVALID; + wire xjtag_axi_0_m00_axi_BREADY; + wire [1:0]xjtag_axi_0_m00_axi_BRESP; + wire xjtag_axi_0_m00_axi_BVALID; + wire [31:0]xjtag_axi_0_m00_axi_RDATA; + wire xjtag_axi_0_m00_axi_RREADY; + wire [1:0]xjtag_axi_0_m00_axi_RRESP; + wire xjtag_axi_0_m00_axi_RVALID; + wire [31:0]xjtag_axi_0_m00_axi_WDATA; + wire xjtag_axi_0_m00_axi_WREADY; + wire [3:0]xjtag_axi_0_m00_axi_WSTRB; + wire xjtag_axi_0_m00_axi_WVALID; + + assign gpio_io_i_0_1 = gpio_in[31:0]; + assign gpio_io_t_0[31:0] = axi_gpio_0_gpio_io_t; + assign gpio_out[31:0] = axi_gpio_0_gpio_io_o; + assign m00_axi_aclk_0_1 = clk; + assign m00_axi_aresetn_0_1 = rstn; + design_1_axi_gpio_0_0 axi_gpio_0 + (.gpio_io_i(gpio_io_i_0_1), + .gpio_io_o(axi_gpio_0_gpio_io_o), + .gpio_io_t(axi_gpio_0_gpio_io_t), + .s_axi_aclk(m00_axi_aclk_0_1), + .s_axi_araddr(xjtag_axi_0_m00_axi_ARADDR[8:0]), + .s_axi_aresetn(m00_axi_aresetn_0_1), + .s_axi_arready(xjtag_axi_0_m00_axi_ARREADY), + .s_axi_arvalid(xjtag_axi_0_m00_axi_ARVALID), + .s_axi_awaddr(xjtag_axi_0_m00_axi_AWADDR[8:0]), + .s_axi_awready(xjtag_axi_0_m00_axi_AWREADY), + .s_axi_awvalid(xjtag_axi_0_m00_axi_AWVALID), + .s_axi_bready(xjtag_axi_0_m00_axi_BREADY), + .s_axi_bresp(xjtag_axi_0_m00_axi_BRESP), + .s_axi_bvalid(xjtag_axi_0_m00_axi_BVALID), + .s_axi_rdata(xjtag_axi_0_m00_axi_RDATA), + .s_axi_rready(xjtag_axi_0_m00_axi_RREADY), + .s_axi_rresp(xjtag_axi_0_m00_axi_RRESP), + .s_axi_rvalid(xjtag_axi_0_m00_axi_RVALID), + .s_axi_wdata(xjtag_axi_0_m00_axi_WDATA), + .s_axi_wready(xjtag_axi_0_m00_axi_WREADY), + .s_axi_wstrb(xjtag_axi_0_m00_axi_WSTRB), + .s_axi_wvalid(xjtag_axi_0_m00_axi_WVALID)); + design_1_xjtag_axi_0_0 xjtag_axi_0 + (.m00_axi_aclk(m00_axi_aclk_0_1), + .m00_axi_araddr(xjtag_axi_0_m00_axi_ARADDR), + .m00_axi_aresetn(m00_axi_aresetn_0_1), + .m00_axi_arready(xjtag_axi_0_m00_axi_ARREADY), + .m00_axi_arvalid(xjtag_axi_0_m00_axi_ARVALID), + .m00_axi_awaddr(xjtag_axi_0_m00_axi_AWADDR), + .m00_axi_awready(xjtag_axi_0_m00_axi_AWREADY), + .m00_axi_awvalid(xjtag_axi_0_m00_axi_AWVALID), + .m00_axi_bready(xjtag_axi_0_m00_axi_BREADY), + .m00_axi_bresp(xjtag_axi_0_m00_axi_BRESP), + .m00_axi_bvalid(xjtag_axi_0_m00_axi_BVALID), + .m00_axi_rdata(xjtag_axi_0_m00_axi_RDATA), + .m00_axi_rready(xjtag_axi_0_m00_axi_RREADY), + .m00_axi_rresp(xjtag_axi_0_m00_axi_RRESP), + .m00_axi_rvalid(xjtag_axi_0_m00_axi_RVALID), + .m00_axi_wdata(xjtag_axi_0_m00_axi_WDATA), + .m00_axi_wready(xjtag_axi_0_m00_axi_WREADY), + .m00_axi_wstrb(xjtag_axi_0_m00_axi_WSTRB), + .m00_axi_wvalid(xjtag_axi_0_m00_axi_WVALID)); +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo new file mode 100644 index 0000000..3bd2de6 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo @@ -0,0 +1,80 @@ + +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1___100.000______0.000______50.0______112.316_____89.971 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________200.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clk_wiz_0 instance_name + ( + // Clock out ports + .clk_out1(clk_out1), // output clk_out1 + // Status and control signals + .locked(locked), // output locked + // Clock in ports + .clk_in1_p(clk_in1_p), // input clk_in1_p + .clk_in1_n(clk_in1_n)); // input clk_in1_n +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100644 index 0000000..9c1015a --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 17:10:06 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub +// d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module clk_wiz_0(clk_out1, locked, clk_in1_p, clk_in1_n) +/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1_p,clk_in1_n" */; + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..d31e7c5 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 17:10:06 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub +-- d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + +end clk_wiz_0; + +architecture stub of clk_wiz_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1_p,clk_in1_n"; +begin +end; diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/README.txt new file mode 100644 index 0000000..31ae1c2 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt new file mode 100644 index 0000000..78517ff --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 17:09:31 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh new file mode 100644 index 0000000..d481123 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 17:09:31 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/compile_simlib/activehdl" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do new file mode 100644 index 0000000..4bc69ae --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt new file mode 100644 index 0000000..039ac3b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do new file mode 100644 index 0000000..a31d6d9 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+clk_wiz_0 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {clk_wiz_0.udo} + +run -all + +endsim + +quit -force diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt new file mode 100644 index 0000000..84cefb9 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 17:09:31 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh new file mode 100644 index 0000000..6f92e90 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 17:09:31 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.clk_wiz_0 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic" \ + +incdir+"../../../ipstatic" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt new file mode 100644 index 0000000..60fd468 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f new file mode 100644 index 0000000..80e44a8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib ies_lib/xpm \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ + "../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt new file mode 100644 index 0000000..78517ff --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 17:09:31 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh new file mode 100644 index 0000000..bda3ab3 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 17:09:31 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do new file mode 100644 index 0000000..bd33709 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do @@ -0,0 +1,22 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm + +vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt new file mode 100644 index 0000000..039ac3b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do new file mode 100644 index 0000000..a44f519 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {clk_wiz_0.udo} + +run -all + +quit -force diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt new file mode 100644 index 0000000..78517ff --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 17:09:31 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh new file mode 100644 index 0000000..f845e82 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 17:09:31 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do new file mode 100644 index 0000000..a3afe77 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do new file mode 100644 index 0000000..b2b0781 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_opt diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt new file mode 100644 index 0000000..039ac3b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do new file mode 100644 index 0000000..77fdf30 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib clk_wiz_0_opt + +do {wave.do} + +view wave +view structure +view signals + +do {clk_wiz_0.udo} + +run -all + +quit -force diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt new file mode 100644 index 0000000..78517ff --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 17:09:31 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh new file mode 100644 index 0000000..2c33e21 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 17:09:31 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do new file mode 100644 index 0000000..ae251d7 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt new file mode 100644 index 0000000..039ac3b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do new file mode 100644 index 0000000..a31d6d9 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+clk_wiz_0 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {clk_wiz_0.udo} + +run -all + +endsim + +quit -force diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt new file mode 100644 index 0000000..78517ff --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 17:09:31 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh new file mode 100644 index 0000000..3022869 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh @@ -0,0 +1,229 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 17:09:31 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ipstatic" \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic" \ + "$ref_dir/../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ + "$ref_dir/../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_simv +} + +# RUN_STEP: +simulate() +{ + ./clk_wiz_0_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key clk_wiz_0_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc clk_wiz_0_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt new file mode 100644 index 0000000..60fd468 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt new file mode 100644 index 0000000..84cefb9 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 17:09:31 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh new file mode 100644 index 0000000..ef5317c --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 17:09:31 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.clk_wiz_0 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic" \ + +incdir+"../../../ipstatic" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt new file mode 100644 index 0000000..60fd468 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f new file mode 100644 index 0000000..706d6e4 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ + "../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt new file mode 100644 index 0000000..78517ff --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 17:09:31 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh new file mode 100644 index 0000000..5ec9541 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh @@ -0,0 +1,211 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 17:09:31 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xvlog_opts="--relax" + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot clk_wiz_0 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim clk_wiz_0 -key {Behavioral:sim_1:Functional:clk_wiz_0} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="E:/Xilinx/Vivado/2018.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb clk_wiz_0.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/elab.opt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/elab.opt new file mode 100644 index 0000000..6114c45 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/elab.opt @@ -0,0 +1 @@ +--relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot clk_wiz_0 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -log elaborate.log diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt new file mode 100644 index 0000000..84ffa25 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt @@ -0,0 +1,3 @@ +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj new file mode 100644 index 0000000..755efc9 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj @@ -0,0 +1,7 @@ +verilog xil_defaultlib --include "../../../ipstatic" \ +"../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/xsim.ini b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/xsim.ini new file mode 100644 index 0000000..85c72ed --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/xsim.ini @@ -0,0 +1,349 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +v_mix_v3_0_1=$RDI_DATADIR/xsim/ip/v_mix_v3_0_1 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +etrnic_v1_1_0=$RDI_DATADIR/xsim/ip/etrnic_v1_1_0 +vfb_v1_0_11=$RDI_DATADIR/xsim/ip/vfb_v1_0_11 +tmr_manager_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_3 +xbip_bram18k_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_5 +jesd204c_v3_0_1=$RDI_DATADIR/xsim/ip/jesd204c_v3_0_1 +pc_cfr_v6_0_7=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_7 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +lte_rach_detector_v3_1_3=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_3 +axi_apb_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_14 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +v_ccm_v6_0_14=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_14 +c_gate_bit_v12_0_5=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_5 +g709_rs_encoder_v2_2_5=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_5 +g709_fec_v2_3_3=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_3 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +canfd_v1_0_10=$RDI_DATADIR/xsim/ip/canfd_v1_0_10 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +ten_gig_eth_mac_v15_1_6=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_6 +ibert_lib_v1_0_5=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_5 +flexo_100g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_7 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +mipi_dsi_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_6 +axi_mmu_v2_1_15=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_15 +cmac_usplus_v2_4_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_3 +v_vcresampler_v1_0_11=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_11 +sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 +mutex_v2_1_9=$RDI_DATADIR/xsim/ip/mutex_v2_1_9 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +v_deinterlacer_v5_0_11=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_11 +xdma_v4_1_1=$RDI_DATADIR/xsim/ip/xdma_v4_1_1 +srio_gen2_v4_1_4=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_4 +ten_gig_eth_pcs_pma_v6_0_13=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_13 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +axis_clock_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_18 +axi_quad_spi_v3_2_16=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_16 +mipi_dphy_v4_1_1=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_1 +v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +axi_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_3 +axi_ethernet_buffer_v2_0_18=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_18 +ieee802d3_200g_rs_fec_v1_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_3 +dds_compiler_v6_0_16=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_16 +pc_cfr_v6_1_3=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_3 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +mult_gen_v12_0_14=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_14 +axi_fifo_mm_s_v4_1_14=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_14 +axi_epc_v2_0_20=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_20 +v_gamma_lut_v1_0_3=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_3 +tmr_comparator_v1_0_1=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_1 +can_v5_0_20=$RDI_DATADIR/xsim/ip/can_v5_0_20 +interlaken_v2_4_1=$RDI_DATADIR/xsim/ip/interlaken_v2_4_1 +axi_intc_v4_1_11=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_11 +ieee802d3_25g_rs_fec_v1_0_9=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_9 +v_csc_v1_0_11=$RDI_DATADIR/xsim/ip/v_csc_v1_0_11 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +xbip_dsp48_acc_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_5 +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +v_frmbuf_rd_v2_1_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_0 +compact_gt_v1_0_3=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_3 +c_compare_v12_0_5=$RDI_DATADIR/xsim/ip/c_compare_v12_0_5 +tri_mode_ethernet_mac_v9_0_12=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_12 +lte_ul_channel_decoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_14 +ieee802d3_50g_rs_fec_v1_0_9=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_9 +g709_rs_decoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_6 +cmac_v2_3_3=$RDI_DATADIR/xsim/ip/cmac_v2_3_3 +rs_toolbox_v9_0_5=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_5 +i2s_transmitter_v1_0_1=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_1 +floating_point_v7_0_15=$RDI_DATADIR/xsim/ip/floating_point_v7_0_15 +g975_efec_i7_v2_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_17 +axi_pcie3_v3_0_7=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_7 +axi_traffic_gen_v3_0_3=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_3 +axi_crossbar_v2_1_18=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_18 +sd_fec_v1_0_1=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_1 +xbip_dsp48_addsub_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_5 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +c_reg_fd_v12_0_5=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_5 +pc_cfr_v6_2_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_0 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +axi_vip_v1_1_3=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_3 +xlconcat_v2_1_1=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_1 +tmr_voter_v1_0_1=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_1 +xlconstant_v1_1_5=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_5 +c_shift_ram_v12_0_12=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_12 +duc_ddc_compiler_v3_0_14=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_14 +v_tc_v6_1_12=$RDI_DATADIR/xsim/ip/v_tc_v6_1_12 +ieee802d3_clause74_fec_v1_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_1 +xhmc_v1_0_7=$RDI_DATADIR/xsim/ip/xhmc_v1_0_7 +vid_phy_controller_v2_2_1=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_1 +uhdsdi_gt_v1_0_2=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_2 +lte_3gpp_mimo_decoder_v3_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_14 +axi_firewall_v1_0_5=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_5 +axi_usb2_device_v5_0_18=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_18 +xbip_dsp48_mult_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_5 +v_hscaler_v1_0_11=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_11 +axis_data_fifo_v1_1_18=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_18 +floating_point_v7_1_6=$RDI_DATADIR/xsim/ip/floating_point_v7_1_6 +axi_clock_converter_v2_1_16=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_16 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +tcc_decoder_3gppmm_v2_0_17=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_17 +v_vscaler_v1_0_11=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_11 +qdma_v2_0_0=$RDI_DATADIR/xsim/ip/qdma_v2_0_0 +axi_emc_v3_0_17=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_17 +dft_v4_0_15=$RDI_DATADIR/xsim/ip/dft_v4_0_15 +rst_vip_v1_0_1=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_1 +xxv_ethernet_v2_4_1=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_1 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +axi_dwidth_converter_v2_1_17=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_17 +sid_v8_0_12=$RDI_DATADIR/xsim/ip/sid_v8_0_12 +v_vid_in_axi4s_v4_0_8=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_8 +v_cfa_v7_0_13=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_13 +v_enhance_v8_0_14=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_14 +displayport_v8_0_1=$RDI_DATADIR/xsim/ip/displayport_v8_0_1 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +axi_sideband_util_v1_0_1=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_1 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +lib_bmg_v1_0_10=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_10 +fir_compiler_v7_2_11=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_11 +blk_mem_gen_v8_4_1=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_1 +ecc_v2_0_12=$RDI_DATADIR/xsim/ip/ecc_v2_0_12 +axi_datamover_v5_1_19=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_19 +displayport_v7_0_9=$RDI_DATADIR/xsim/ip/displayport_v7_0_9 +v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 +tmr_inject_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_2 +i2s_receiver_v1_0_1=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_1 +axis_protocol_checker_v1_2_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v1_2_3 +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +gig_ethernet_pcs_pma_v16_1_4=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_4 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +pci32_v5_0_11=$RDI_DATADIR/xsim/ip/pci32_v5_0_11 +xbip_dsp48_macro_v3_0_16=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_16 +v_smpte_uhdsdi_v1_0_5=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_5 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +axi4svideo_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_9 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 +sd_fec_v1_1_1=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_1 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +div_gen_v5_1_13=$RDI_DATADIR/xsim/ip/div_gen_v5_1_13 +high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 +sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 +axi_utils_v2_0_5=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_5 +gtwizard_ultrascale_v1_6_10=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_10 +g975_efec_i4_v1_0_15=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_15 +mii_to_rmii_v2_0_19=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_19 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +cpri_v8_9_1=$RDI_DATADIR/xsim/ip/cpri_v8_9_1 +axi_timebase_wdt_v3_0_9=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_9 +quadsgmii_v3_4_4=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_4 +tcc_encoder_3gpplte_v4_0_14=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_14 +cmpy_v6_0_15=$RDI_DATADIR/xsim/ip/cmpy_v6_0_15 +axi_cdma_v4_1_17=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_17 +axi_uartlite_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_21 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +xbip_pipe_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_5 +axis_accelerator_adapter_v2_1_13=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_13 +ieee802d3_400g_rs_fec_v1_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_3 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +v_rgb2ycrcb_v7_1_12=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_12 +ats_switch_v1_0_0=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_0 +v_gamma_v7_0_14=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_14 +lte_dl_channel_encoder_v3_0_14=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_14 +gmii_to_rgmii_v4_0_6=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_6 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +fit_timer_v2_0_8=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_8 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +convolution_v9_0_13=$RDI_DATADIR/xsim/ip/convolution_v9_0_13 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +xfft_v9_0_15=$RDI_DATADIR/xsim/ip/xfft_v9_0_15 +axi_register_slice_v2_1_17=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_17 +axi4stream_vip_v1_1_3=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_3 +xfft_v7_2_7=$RDI_DATADIR/xsim/ip/xfft_v7_2_7 +xbip_utils_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_9 +axi_tft_v2_0_20=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_20 +l_ethernet_v2_3_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_3 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +v_frmbuf_wr_v2_0_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_0_3 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +axi_data_fifo_v2_1_16=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_16 +audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 +usxgmii_v1_0_3=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_3 +dist_mem_gen_v8_0_12=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_12 +mailbox_v2_1_10=$RDI_DATADIR/xsim/ip/mailbox_v2_1_10 +v_demosaic_v1_0_3=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_3 +ethernet_1_10_25g_v2_1_0=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_0 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +axi_traffic_gen_v2_0_18=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_18 +axi_dma_v7_1_18=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_18 +axi_ahblite_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_14 +axi_sg_v4_1_10=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_10 +xbip_dsp48_multadd_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_5 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +rxaui_v4_4_4=$RDI_DATADIR/xsim/ip/rxaui_v4_4_4 +v_ycrcb2rgb_v7_1_12=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_12 +video_frame_crc_v1_0_0=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_0 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +pr_decoupler_v1_0_6=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_6 +tcc_encoder_3gpp_v5_0_13=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_13 +microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 +lib_fifo_v1_0_11=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_11 +v_letterbox_v1_0_11=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_11 +v_cresample_v4_0_13=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_13 +axi_msg_v1_0_3=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_3 +gtwizard_ultrascale_v1_7_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_4 +zynq_ultra_ps_e_v3_2_1=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_1 +c_mux_bit_v12_0_5=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_5 +axis_register_slice_v1_1_17=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_17 +hdcp22_cipher_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_2 +xfft_v9_1_0=$RDI_DATADIR/xsim/ip/xfft_v9_1_0 +axis_combiner_v1_1_15=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_15 +xbip_dsp48_multacc_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_5 +lmb_bram_if_cntlr_v4_0_15=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_15 +zynq_ultra_ps_e_vip_v1_0_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_3 +axi_protocol_checker_v1_1_17=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v1_1_17 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +axis_protocol_checker_v2_0_1=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_1 +ieee802d3_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_13 +v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 +tsn_temac_v1_0_3=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_3 +xlslice_v1_0_1=$RDI_DATADIR/xsim/ip/xlslice_v1_0_1 +fec_5g_common_v1_0_0=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_0 +oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 +rs_decoder_v9_0_14=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_14 +v_axi4s_remap_v1_0_9=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_9 +v_frmbuf_rd_v2_0_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_0_3 +ahblite_axi_bridge_v3_0_13=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_13 +axi_protocol_converter_v2_1_17=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_17 +axi_vfifo_ctrl_v2_0_19=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_19 +iomodule_v3_1_3=$RDI_DATADIR/xsim/ip/iomodule_v3_1_3 +xbip_multadd_v3_0_12=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_12 +rs_encoder_v9_0_13=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_13 +axis_switch_v1_1_17=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_17 +cordic_v6_0_14=$RDI_DATADIR/xsim/ip/cordic_v6_0_14 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +v_osd_v6_0_15=$RDI_DATADIR/xsim/ip/v_osd_v6_0_15 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +lte_fft_v2_0_16=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_16 +axi_gpio_v2_0_19=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_19 +xaui_v12_3_4=$RDI_DATADIR/xsim/ip/xaui_v12_3_4 +axis_subset_converter_v1_1_17=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_17 +axi_uart16550_v2_0_19=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_19 +ldpc_v2_0_1=$RDI_DATADIR/xsim/ip/ldpc_v2_0_1 +tsn_endpoint_ethernet_mac_block_v1_0_2=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_2 +v_frmbuf_wr_v2_1_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_0 +pr_bitstream_monitor_v1_0_0=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_0 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +axi_interconnect_v1_7_14=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_14 +lte_3gpp_channel_estimator_v2_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_15 +vid_phy_controller_v2_1_0=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_0 +xbip_counter_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_5 +etrnic_v1_0_1=$RDI_DATADIR/xsim/ip/etrnic_v1_0_1 +axi_timer_v2_0_19=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_19 +ta_dma_v1_0_1=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_1 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +axis_broadcaster_v1_1_16=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_16 +amm_axi_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_3 +fec_5g_common_v1_1_0=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +v_uhdsdi_vidgen_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_0 +lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 +lte_3gpp_mimo_encoder_v4_0_13=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_13 +c_addsub_v12_0_12=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_12 +c_mux_bus_v12_0_5=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_5 +axi_chip2chip_v5_0_3=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_3 +axis_dwidth_converter_v1_1_16=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_16 +processing_system7_vip_v1_0_5=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_5 +spdif_v2_0_19=$RDI_DATADIR/xsim/ip/spdif_v2_0_19 +v_tpg_v7_0_11=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_11 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +fifo_generator_v13_2_2=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_2 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +pr_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_0 +in_system_ibert_v1_0_7=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_7 +axi_amm_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_7 +xbip_accum_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_5 +sem_ultra_v3_1_8=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_8 +viterbi_v9_1_9=$RDI_DATADIR/xsim/ip/viterbi_v9_1_9 +high_speed_selectio_wiz_v3_4_0=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_0 +v_axi4s_vid_out_v4_0_9=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_9 +axi_iic_v2_0_20=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_20 +axi_hwicap_v3_0_21=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_21 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +system_cache_v4_0_5=$RDI_DATADIR/xsim/ip/system_cache_v4_0_5 +ieee802d3_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_1 +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +axis_interconnect_v1_1_15=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_15 +v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 +c_counter_binary_v12_0_12=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_12 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +fc32_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_7 +axi_vdma_v6_3_5=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_5 +fir_compiler_v5_2_5=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_5 +xpm=$RDI_DATADIR/xsim/ip/xpm +axi_mcdma_v1_0_3=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_3 +lte_pucch_receiver_v2_0_14=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_14 +proc_sys_reset_v5_0_12=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_12 +polar_v1_0_1=$RDI_DATADIR/xsim/ip/polar_v1_0_1 +tmr_sem_v1_0_5=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_5 +cic_compiler_v4_0_13=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_13 +mdm_v3_2_14=$RDI_DATADIR/xsim/ip/mdm_v3_2_14 +prc_v1_3_1=$RDI_DATADIR/xsim/ip/prc_v1_3_1 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +jesd204_v7_2_3=$RDI_DATADIR/xsim/ip/jesd204_v7_2_3 +axi_perf_mon_v5_0_19=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_19 +av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0 +axi_ethernetlite_v3_0_15=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_15 +sem_v4_1_11=$RDI_DATADIR/xsim/ip/sem_v4_1_11 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +switch_core_top_v1_0_5=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_5 +axi_pcie_v2_8_9=$RDI_DATADIR/xsim/ip/axi_pcie_v2_8_9 +v_dual_splitter_v1_0_8=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_8 +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +xbip_addsub_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_5 +ethernet_1_10_25g_v2_0_1=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_1 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +axi_mm2s_mapper_v1_1_16=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_16 +axis_protocol_checker_v1_1_16=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v1_1_16 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +c_accum_v12_0_12=$RDI_DATADIR/xsim/ip/c_accum_v12_0_12 +clk_vip_v1_0_1=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_1 +v_hcresampler_v1_0_11=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_11 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/README.txt new file mode 100644 index 0000000..31ae1c2 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/README.txt new file mode 100644 index 0000000..1851a3b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Jun 30 17:32:55 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./design_1.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './design_1.sh' script. + +./design_1.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./design_1.sh -noclean_files + +For more information on the script, please type './design_1.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/compile.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/compile.do new file mode 100644 index 0000000..8f90d63 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/compile.do @@ -0,0 +1,48 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm +vlib activehdl/axi_lite_ipif_v3_0_4 +vlib activehdl/lib_cdc_v1_0_2 +vlib activehdl/interrupt_control_v3_1_4 +vlib activehdl/axi_gpio_v2_0_19 + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm +vmap axi_lite_ipif_v3_0_4 activehdl/axi_lite_ipif_v3_0_4 +vmap lib_cdc_v1_0_2 activehdl/lib_cdc_v1_0_2 +vmap interrupt_control_v3_1_4 activehdl/interrupt_control_v3_1_4 +vmap axi_gpio_v2_0_19 activehdl/axi_gpio_v2_0_19 + +vlog -work xil_defaultlib -sv2k12 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../bd/design_1/ipshared/2284/src/xjtag_axi.v" \ +"../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v" \ + +vcom -work axi_lite_ipif_v3_0_4 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd" \ + +vcom -work lib_cdc_v1_0_2 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work interrupt_control_v3_1_4 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd" \ + +vcom -work axi_gpio_v2_0_19 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../bd/design_1/sim/design_1.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/design_1.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/design_1.sh new file mode 100644 index 0000000..6fdbf93 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/design_1.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : design_1.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Jun 30 17:32:55 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: design_1.sh [-help] +# usage: design_1.sh [-lib_map_path] +# usage: design_1.sh [-noclean_files] +# usage: design_1.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'design_1.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "design_1.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/compile_simlib/activehdl" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: design_1.sh [-help]\n\ +Usage: design_1.sh [-lib_map_path]\n\ +Usage: design_1.sh [-reset_run]\n\ +Usage: design_1.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/design_1.udo b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/design_1.udo new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/file_info.txt new file mode 100644 index 0000000..53170c8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd, +xjtag_axi.v,verilog,xil_defaultlib,../../../bd/design_1/ipshared/2284/src/xjtag_axi.v, +design_1_xjtag_axi_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v, +axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd, +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd, +interrupt_control_v3_1_vh_rfs.vhd,vhdl,interrupt_control_v3_1_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd, +axi_gpio_v2_0_vh_rfs.vhd,vhdl,axi_gpio_v2_0_19,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd, +design_1_axi_gpio_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd, +design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/simulate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/simulate.do new file mode 100644 index 0000000..cb95af8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+design_1 -L xil_defaultlib -L xpm -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_19 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.design_1 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {design_1.udo} + +run -all + +endsim + +quit -force diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/wave.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/README.txt new file mode 100644 index 0000000..d871436 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Jun 30 17:32:55 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./design_1.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './design_1.sh' script. + +./design_1.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./design_1.sh -noclean_files + +For more information on the script, please type './design_1.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/design_1.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/design_1.sh new file mode 100644 index 0000000..c5a58c7 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/design_1.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : design_1.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Jun 30 17:32:55 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: design_1.sh [-help] +# usage: design_1.sh [-lib_map_path] +# usage: design_1.sh [-noclean_files] +# usage: design_1.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'design_1.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm axi_lite_ipif_v3_0_4 lib_cdc_v1_0_2 interrupt_control_v3_1_4 axi_gpio_v2_0_19) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "design_1.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.design_1 \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: design_1.sh [-help]\n\ +Usage: design_1.sh [-lib_map_path]\n\ +Usage: design_1.sh [-reset_run]\n\ +Usage: design_1.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/file_info.txt new file mode 100644 index 0000000..53170c8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd, +xjtag_axi.v,verilog,xil_defaultlib,../../../bd/design_1/ipshared/2284/src/xjtag_axi.v, +design_1_xjtag_axi_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v, +axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd, +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd, +interrupt_control_v3_1_vh_rfs.vhd,vhdl,interrupt_control_v3_1_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd, +axi_gpio_v2_0_vh_rfs.vhd,vhdl,axi_gpio_v2_0_19,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd, +design_1_axi_gpio_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd, +design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/run.f b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/run.f new file mode 100644 index 0000000..b6e9030 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/ies/run.f @@ -0,0 +1,32 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib ies_lib/xpm \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../bd/design_1/ipshared/2284/src/xjtag_axi.v" \ + "../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v" \ +-endlib +-makelib ies_lib/axi_lite_ipif_v3_0_4 \ + "../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/lib_cdc_v1_0_2 \ + "../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \ +-endlib +-makelib ies_lib/interrupt_control_v3_1_4 \ + "../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/axi_gpio_v2_0_19 \ + "../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../bd/design_1/sim/design_1.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/README.txt new file mode 100644 index 0000000..1851a3b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Jun 30 17:32:55 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./design_1.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './design_1.sh' script. + +./design_1.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./design_1.sh -noclean_files + +For more information on the script, please type './design_1.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/compile.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/compile.do new file mode 100644 index 0000000..1c0650c --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/compile.do @@ -0,0 +1,48 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/axi_lite_ipif_v3_0_4 +vlib modelsim_lib/msim/lib_cdc_v1_0_2 +vlib modelsim_lib/msim/interrupt_control_v3_1_4 +vlib modelsim_lib/msim/axi_gpio_v2_0_19 + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm +vmap axi_lite_ipif_v3_0_4 modelsim_lib/msim/axi_lite_ipif_v3_0_4 +vmap lib_cdc_v1_0_2 modelsim_lib/msim/lib_cdc_v1_0_2 +vmap interrupt_control_v3_1_4 modelsim_lib/msim/interrupt_control_v3_1_4 +vmap axi_gpio_v2_0_19 modelsim_lib/msim/axi_gpio_v2_0_19 + +vlog -work xil_defaultlib -64 -incr -sv \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 -incr \ +"../../../bd/design_1/ipshared/2284/src/xjtag_axi.v" \ +"../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v" \ + +vcom -work axi_lite_ipif_v3_0_4 -64 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd" \ + +vcom -work lib_cdc_v1_0_2 -64 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work interrupt_control_v3_1_4 -64 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd" \ + +vcom -work axi_gpio_v2_0_19 -64 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd" \ + +vlog -work xil_defaultlib -64 -incr \ +"../../../bd/design_1/sim/design_1.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/design_1.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/design_1.sh new file mode 100644 index 0000000..26bd5fe --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/design_1.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : design_1.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Jun 30 17:32:55 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: design_1.sh [-help] +# usage: design_1.sh [-lib_map_path] +# usage: design_1.sh [-noclean_files] +# usage: design_1.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'design_1.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "design_1.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: design_1.sh [-help]\n\ +Usage: design_1.sh [-lib_map_path]\n\ +Usage: design_1.sh [-reset_run]\n\ +Usage: design_1.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/design_1.udo b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/design_1.udo new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/file_info.txt new file mode 100644 index 0000000..53170c8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd, +xjtag_axi.v,verilog,xil_defaultlib,../../../bd/design_1/ipshared/2284/src/xjtag_axi.v, +design_1_xjtag_axi_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v, +axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd, +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd, +interrupt_control_v3_1_vh_rfs.vhd,vhdl,interrupt_control_v3_1_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd, +axi_gpio_v2_0_vh_rfs.vhd,vhdl,axi_gpio_v2_0_19,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd, +design_1_axi_gpio_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd, +design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/simulate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/simulate.do new file mode 100644 index 0000000..a975844 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_19 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.design_1 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {design_1.udo} + +run -all + +quit -force diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/wave.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/README.txt new file mode 100644 index 0000000..1851a3b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Jun 30 17:32:55 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./design_1.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './design_1.sh' script. + +./design_1.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./design_1.sh -noclean_files + +For more information on the script, please type './design_1.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/compile.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/compile.do new file mode 100644 index 0000000..5585fbd --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/compile.do @@ -0,0 +1,48 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm +vlib questa_lib/msim/axi_lite_ipif_v3_0_4 +vlib questa_lib/msim/lib_cdc_v1_0_2 +vlib questa_lib/msim/interrupt_control_v3_1_4 +vlib questa_lib/msim/axi_gpio_v2_0_19 + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm +vmap axi_lite_ipif_v3_0_4 questa_lib/msim/axi_lite_ipif_v3_0_4 +vmap lib_cdc_v1_0_2 questa_lib/msim/lib_cdc_v1_0_2 +vmap interrupt_control_v3_1_4 questa_lib/msim/interrupt_control_v3_1_4 +vmap axi_gpio_v2_0_19 questa_lib/msim/axi_gpio_v2_0_19 + +vlog -work xil_defaultlib -64 -sv \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 \ +"../../../bd/design_1/ipshared/2284/src/xjtag_axi.v" \ +"../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v" \ + +vcom -work axi_lite_ipif_v3_0_4 -64 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd" \ + +vcom -work lib_cdc_v1_0_2 -64 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work interrupt_control_v3_1_4 -64 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd" \ + +vcom -work axi_gpio_v2_0_19 -64 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd" \ + +vlog -work xil_defaultlib -64 \ +"../../../bd/design_1/sim/design_1.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/design_1.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/design_1.sh new file mode 100644 index 0000000..e0b1de1 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/design_1.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : design_1.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Jun 30 17:32:55 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: design_1.sh [-help] +# usage: design_1.sh [-lib_map_path] +# usage: design_1.sh [-noclean_files] +# usage: design_1.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'design_1.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "design_1.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: design_1.sh [-help]\n\ +Usage: design_1.sh [-lib_map_path]\n\ +Usage: design_1.sh [-reset_run]\n\ +Usage: design_1.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/design_1.udo b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/design_1.udo new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/elaborate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/elaborate.do new file mode 100644 index 0000000..ff0feee --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_19 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.design_1 xil_defaultlib.glbl -o design_1_opt diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/file_info.txt new file mode 100644 index 0000000..53170c8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd, +xjtag_axi.v,verilog,xil_defaultlib,../../../bd/design_1/ipshared/2284/src/xjtag_axi.v, +design_1_xjtag_axi_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v, +axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd, +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd, +interrupt_control_v3_1_vh_rfs.vhd,vhdl,interrupt_control_v3_1_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd, +axi_gpio_v2_0_vh_rfs.vhd,vhdl,axi_gpio_v2_0_19,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd, +design_1_axi_gpio_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd, +design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/simulate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/simulate.do new file mode 100644 index 0000000..cc17c1b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib design_1_opt + +do {wave.do} + +view wave +view structure +view signals + +do {design_1.udo} + +run -all + +quit -force diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/wave.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/README.txt new file mode 100644 index 0000000..1851a3b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Jun 30 17:32:55 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./design_1.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './design_1.sh' script. + +./design_1.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./design_1.sh -noclean_files + +For more information on the script, please type './design_1.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/compile.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/compile.do new file mode 100644 index 0000000..e9a6d20 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/compile.do @@ -0,0 +1,48 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm +vlib riviera/axi_lite_ipif_v3_0_4 +vlib riviera/lib_cdc_v1_0_2 +vlib riviera/interrupt_control_v3_1_4 +vlib riviera/axi_gpio_v2_0_19 + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm +vmap axi_lite_ipif_v3_0_4 riviera/axi_lite_ipif_v3_0_4 +vmap lib_cdc_v1_0_2 riviera/lib_cdc_v1_0_2 +vmap interrupt_control_v3_1_4 riviera/interrupt_control_v3_1_4 +vmap axi_gpio_v2_0_19 riviera/axi_gpio_v2_0_19 + +vlog -work xil_defaultlib -sv2k12 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../bd/design_1/ipshared/2284/src/xjtag_axi.v" \ +"../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v" \ + +vcom -work axi_lite_ipif_v3_0_4 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd" \ + +vcom -work lib_cdc_v1_0_2 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \ + +vcom -work interrupt_control_v3_1_4 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd" \ + +vcom -work axi_gpio_v2_0_19 -93 \ +"../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../bd/design_1/sim/design_1.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/design_1.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/design_1.sh new file mode 100644 index 0000000..22bf30a --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/design_1.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : design_1.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Jun 30 17:32:55 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: design_1.sh [-help] +# usage: design_1.sh [-lib_map_path] +# usage: design_1.sh [-noclean_files] +# usage: design_1.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'design_1.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "design_1.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: design_1.sh [-help]\n\ +Usage: design_1.sh [-lib_map_path]\n\ +Usage: design_1.sh [-reset_run]\n\ +Usage: design_1.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/design_1.udo b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/design_1.udo new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/file_info.txt new file mode 100644 index 0000000..53170c8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd, +xjtag_axi.v,verilog,xil_defaultlib,../../../bd/design_1/ipshared/2284/src/xjtag_axi.v, +design_1_xjtag_axi_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v, +axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd, +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd, +interrupt_control_v3_1_vh_rfs.vhd,vhdl,interrupt_control_v3_1_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd, +axi_gpio_v2_0_vh_rfs.vhd,vhdl,axi_gpio_v2_0_19,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd, +design_1_axi_gpio_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd, +design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/simulate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/simulate.do new file mode 100644 index 0000000..cb95af8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+design_1 -L xil_defaultlib -L xpm -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_19 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.design_1 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {design_1.udo} + +run -all + +endsim + +quit -force diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/wave.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/README.txt new file mode 100644 index 0000000..1851a3b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Jun 30 17:32:55 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./design_1.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './design_1.sh' script. + +./design_1.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./design_1.sh -noclean_files + +For more information on the script, please type './design_1.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/design_1.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/design_1.sh new file mode 100644 index 0000000..467c28c --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/design_1.sh @@ -0,0 +1,253 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : design_1.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Jun 30 17:32:55 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: design_1.sh [-help] +# usage: design_1.sh [-lib_map_path] +# usage: design_1.sh [-noclean_files] +# usage: design_1.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'design_1.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm axi_lite_ipif_v3_0_4 lib_cdc_v1_0_2 interrupt_control_v3_1_4 axi_gpio_v2_0_19) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "design_1.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../bd/design_1/ipshared/2284/src/xjtag_axi.v" \ + "$ref_dir/../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work axi_lite_ipif_v3_0_4 $vhdlan_opts \ + "$ref_dir/../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \ + "$ref_dir/../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work interrupt_control_v3_1_4 $vhdlan_opts \ + "$ref_dir/../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work axi_gpio_v2_0_19 $vhdlan_opts \ + "$ref_dir/../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../bd/design_1/sim/design_1.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.design_1 xil_defaultlib.glbl -o design_1_simv +} + +# RUN_STEP: +simulate() +{ + ./design_1_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key design_1_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc design_1_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: design_1.sh [-help]\n\ +Usage: design_1.sh [-lib_map_path]\n\ +Usage: design_1.sh [-reset_run]\n\ +Usage: design_1.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/file_info.txt new file mode 100644 index 0000000..53170c8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd, +xjtag_axi.v,verilog,xil_defaultlib,../../../bd/design_1/ipshared/2284/src/xjtag_axi.v, +design_1_xjtag_axi_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v, +axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd, +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd, +interrupt_control_v3_1_vh_rfs.vhd,vhdl,interrupt_control_v3_1_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd, +axi_gpio_v2_0_vh_rfs.vhd,vhdl,axi_gpio_v2_0_19,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd, +design_1_axi_gpio_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd, +design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/simulate.do b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/README.txt new file mode 100644 index 0000000..d871436 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Jun 30 17:32:55 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./design_1.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './design_1.sh' script. + +./design_1.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./design_1.sh -noclean_files + +For more information on the script, please type './design_1.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/design_1.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/design_1.sh new file mode 100644 index 0000000..a607fba --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/design_1.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : design_1.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Jun 30 17:32:55 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: design_1.sh [-help] +# usage: design_1.sh [-lib_map_path] +# usage: design_1.sh [-noclean_files] +# usage: design_1.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'design_1.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm axi_lite_ipif_v3_0_4 lib_cdc_v1_0_2 interrupt_control_v3_1_4 axi_gpio_v2_0_19) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "design_1.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.design_1 \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: design_1.sh [-help]\n\ +Usage: design_1.sh [-lib_map_path]\n\ +Usage: design_1.sh [-reset_run]\n\ +Usage: design_1.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/file_info.txt new file mode 100644 index 0000000..53170c8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/file_info.txt @@ -0,0 +1,11 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd, +xjtag_axi.v,verilog,xil_defaultlib,../../../bd/design_1/ipshared/2284/src/xjtag_axi.v, +design_1_xjtag_axi_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v, +axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd, +lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd, +interrupt_control_v3_1_vh_rfs.vhd,vhdl,interrupt_control_v3_1_4,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd, +axi_gpio_v2_0_vh_rfs.vhd,vhdl,axi_gpio_v2_0_19,../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd, +design_1_axi_gpio_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd, +design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/run.f b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/run.f new file mode 100644 index 0000000..023808f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xcelium/run.f @@ -0,0 +1,32 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../bd/design_1/ipshared/2284/src/xjtag_axi.v" \ + "../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v" \ +-endlib +-makelib xcelium_lib/axi_lite_ipif_v3_0_4 \ + "../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/lib_cdc_v1_0_2 \ + "../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \ +-endlib +-makelib xcelium_lib/interrupt_control_v3_1_4 \ + "../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/axi_gpio_v2_0_19 \ + "../../../../axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../bd/design_1/sim/design_1.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/README.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/README.txt new file mode 100644 index 0000000..1851a3b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Tue Jun 30 17:32:55 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./design_1.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './design_1.sh' script. + +./design_1.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./design_1.sh -noclean_files + +For more information on the script, please type './design_1.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/cmd.tcl b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/design_1.sh b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/design_1.sh new file mode 100644 index 0000000..1d6eb2b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/design_1.sh @@ -0,0 +1,213 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : design_1.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Tue Jun 30 17:32:55 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: design_1.sh [-help] +# usage: design_1.sh [-lib_map_path] +# usage: design_1.sh [-noclean_files] +# usage: design_1.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xvlog_opts="--relax" +xvhdl_opts="--relax" + + +# Script info +echo -e "design_1.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_19 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot design_1 xil_defaultlib.design_1 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim design_1 -key {Behavioral:sim_1:Functional:design_1} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="E:/Xilinx/Vivado/2018.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb design_1.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./design_1.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: design_1.sh [-help]\n\ +Usage: design_1.sh [-lib_map_path]\n\ +Usage: design_1.sh [-reset_run]\n\ +Usage: design_1.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/elab.opt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/elab.opt new file mode 100644 index 0000000..a885c60 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/elab.opt @@ -0,0 +1 @@ +--relax --debug typical --mt auto -L xil_defaultlib -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_19 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot design_1 xil_defaultlib.design_1 xil_defaultlib.glbl -log elaborate.log diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/file_info.txt b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/file_info.txt new file mode 100644 index 0000000..660b010 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/file_info.txt @@ -0,0 +1,5 @@ +xjtag_axi.v,verilog,xil_defaultlib,../../../bd/design_1/ipshared/2284/src/xjtag_axi.v, +design_1_xjtag_axi_0_0.v,verilog,xil_defaultlib,../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v, +design_1_axi_gpio_0_0.vhd,vhdl,xil_defaultlib,../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd, +design_1.v,verilog,xil_defaultlib,../../../bd/design_1/sim/design_1.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/glbl.v b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/vhdl.prj b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/vhdl.prj new file mode 100644 index 0000000..d469a1e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/vhdl.prj @@ -0,0 +1,4 @@ +vhdl xil_defaultlib \ +"../../../bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd" \ + +nosort diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/vlog.prj b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/vlog.prj new file mode 100644 index 0000000..6ec482d --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/vlog.prj @@ -0,0 +1,8 @@ +verilog xil_defaultlib \ +"../../../bd/design_1/ipshared/2284/src/xjtag_axi.v" \ +"../../../bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v" \ +"../../../bd/design_1/sim/design_1.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/xsim.ini b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/xsim.ini new file mode 100644 index 0000000..85c72ed --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.ip_user_files/sim_scripts/design_1/xsim/xsim.ini @@ -0,0 +1,349 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +v_mix_v3_0_1=$RDI_DATADIR/xsim/ip/v_mix_v3_0_1 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +etrnic_v1_1_0=$RDI_DATADIR/xsim/ip/etrnic_v1_1_0 +vfb_v1_0_11=$RDI_DATADIR/xsim/ip/vfb_v1_0_11 +tmr_manager_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_3 +xbip_bram18k_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_5 +jesd204c_v3_0_1=$RDI_DATADIR/xsim/ip/jesd204c_v3_0_1 +pc_cfr_v6_0_7=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_7 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +lte_rach_detector_v3_1_3=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_3 +axi_apb_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_14 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +v_ccm_v6_0_14=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_14 +c_gate_bit_v12_0_5=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_5 +g709_rs_encoder_v2_2_5=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_5 +g709_fec_v2_3_3=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_3 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +canfd_v1_0_10=$RDI_DATADIR/xsim/ip/canfd_v1_0_10 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +ten_gig_eth_mac_v15_1_6=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_6 +ibert_lib_v1_0_5=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_5 +flexo_100g_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_7 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +mipi_dsi_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_6 +axi_mmu_v2_1_15=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_15 +cmac_usplus_v2_4_3=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_3 +v_vcresampler_v1_0_11=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_11 +sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 +mutex_v2_1_9=$RDI_DATADIR/xsim/ip/mutex_v2_1_9 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +v_deinterlacer_v5_0_11=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_11 +xdma_v4_1_1=$RDI_DATADIR/xsim/ip/xdma_v4_1_1 +srio_gen2_v4_1_4=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_4 +ten_gig_eth_pcs_pma_v6_0_13=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_13 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +axis_clock_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_18 +axi_quad_spi_v3_2_16=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_16 +mipi_dphy_v4_1_1=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_1 +v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +axi_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_3 +axi_ethernet_buffer_v2_0_18=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_18 +ieee802d3_200g_rs_fec_v1_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_3 +dds_compiler_v6_0_16=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_16 +pc_cfr_v6_1_3=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_3 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +mult_gen_v12_0_14=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_14 +axi_fifo_mm_s_v4_1_14=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_14 +axi_epc_v2_0_20=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_20 +v_gamma_lut_v1_0_3=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_3 +tmr_comparator_v1_0_1=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_1 +can_v5_0_20=$RDI_DATADIR/xsim/ip/can_v5_0_20 +interlaken_v2_4_1=$RDI_DATADIR/xsim/ip/interlaken_v2_4_1 +axi_intc_v4_1_11=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_11 +ieee802d3_25g_rs_fec_v1_0_9=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_9 +v_csc_v1_0_11=$RDI_DATADIR/xsim/ip/v_csc_v1_0_11 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +xbip_dsp48_acc_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_5 +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +v_frmbuf_rd_v2_1_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_0 +compact_gt_v1_0_3=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_3 +c_compare_v12_0_5=$RDI_DATADIR/xsim/ip/c_compare_v12_0_5 +tri_mode_ethernet_mac_v9_0_12=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_12 +lte_ul_channel_decoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_14 +ieee802d3_50g_rs_fec_v1_0_9=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_9 +g709_rs_decoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_6 +cmac_v2_3_3=$RDI_DATADIR/xsim/ip/cmac_v2_3_3 +rs_toolbox_v9_0_5=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_5 +i2s_transmitter_v1_0_1=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_1 +floating_point_v7_0_15=$RDI_DATADIR/xsim/ip/floating_point_v7_0_15 +g975_efec_i7_v2_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_17 +axi_pcie3_v3_0_7=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_7 +axi_traffic_gen_v3_0_3=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_3 +axi_crossbar_v2_1_18=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_18 +sd_fec_v1_0_1=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_1 +xbip_dsp48_addsub_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_5 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +c_reg_fd_v12_0_5=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_5 +pc_cfr_v6_2_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_0 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +axi_vip_v1_1_3=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_3 +xlconcat_v2_1_1=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_1 +tmr_voter_v1_0_1=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_1 +xlconstant_v1_1_5=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_5 +c_shift_ram_v12_0_12=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_12 +duc_ddc_compiler_v3_0_14=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_14 +v_tc_v6_1_12=$RDI_DATADIR/xsim/ip/v_tc_v6_1_12 +ieee802d3_clause74_fec_v1_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_1 +xhmc_v1_0_7=$RDI_DATADIR/xsim/ip/xhmc_v1_0_7 +vid_phy_controller_v2_2_1=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_1 +uhdsdi_gt_v1_0_2=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_2 +lte_3gpp_mimo_decoder_v3_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_14 +axi_firewall_v1_0_5=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_5 +axi_usb2_device_v5_0_18=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_18 +xbip_dsp48_mult_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_5 +v_hscaler_v1_0_11=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_11 +axis_data_fifo_v1_1_18=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_18 +floating_point_v7_1_6=$RDI_DATADIR/xsim/ip/floating_point_v7_1_6 +axi_clock_converter_v2_1_16=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_16 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +tcc_decoder_3gppmm_v2_0_17=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_17 +v_vscaler_v1_0_11=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_11 +qdma_v2_0_0=$RDI_DATADIR/xsim/ip/qdma_v2_0_0 +axi_emc_v3_0_17=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_17 +dft_v4_0_15=$RDI_DATADIR/xsim/ip/dft_v4_0_15 +rst_vip_v1_0_1=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_1 +xxv_ethernet_v2_4_1=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_1 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +axi_dwidth_converter_v2_1_17=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_17 +sid_v8_0_12=$RDI_DATADIR/xsim/ip/sid_v8_0_12 +v_vid_in_axi4s_v4_0_8=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_8 +v_cfa_v7_0_13=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_13 +v_enhance_v8_0_14=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_14 +displayport_v8_0_1=$RDI_DATADIR/xsim/ip/displayport_v8_0_1 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +axi_sideband_util_v1_0_1=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_1 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +lib_bmg_v1_0_10=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_10 +fir_compiler_v7_2_11=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_11 +blk_mem_gen_v8_4_1=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_1 +ecc_v2_0_12=$RDI_DATADIR/xsim/ip/ecc_v2_0_12 +axi_datamover_v5_1_19=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_19 +displayport_v7_0_9=$RDI_DATADIR/xsim/ip/displayport_v7_0_9 +v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 +tmr_inject_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_2 +i2s_receiver_v1_0_1=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_1 +axis_protocol_checker_v1_2_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v1_2_3 +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +gig_ethernet_pcs_pma_v16_1_4=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_4 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +pci32_v5_0_11=$RDI_DATADIR/xsim/ip/pci32_v5_0_11 +xbip_dsp48_macro_v3_0_16=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_16 +v_smpte_uhdsdi_v1_0_5=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_5 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +axi4svideo_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_9 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 +sd_fec_v1_1_1=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_1 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +div_gen_v5_1_13=$RDI_DATADIR/xsim/ip/div_gen_v5_1_13 +high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 +sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 +axi_utils_v2_0_5=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_5 +gtwizard_ultrascale_v1_6_10=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_10 +g975_efec_i4_v1_0_15=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_15 +mii_to_rmii_v2_0_19=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_19 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +cpri_v8_9_1=$RDI_DATADIR/xsim/ip/cpri_v8_9_1 +axi_timebase_wdt_v3_0_9=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_9 +quadsgmii_v3_4_4=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_4 +tcc_encoder_3gpplte_v4_0_14=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_14 +cmpy_v6_0_15=$RDI_DATADIR/xsim/ip/cmpy_v6_0_15 +axi_cdma_v4_1_17=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_17 +axi_uartlite_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_21 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +xbip_pipe_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_5 +axis_accelerator_adapter_v2_1_13=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_13 +ieee802d3_400g_rs_fec_v1_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_3 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +v_rgb2ycrcb_v7_1_12=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_12 +ats_switch_v1_0_0=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_0 +v_gamma_v7_0_14=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_14 +lte_dl_channel_encoder_v3_0_14=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_14 +gmii_to_rgmii_v4_0_6=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_6 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +fit_timer_v2_0_8=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_8 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +convolution_v9_0_13=$RDI_DATADIR/xsim/ip/convolution_v9_0_13 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +xfft_v9_0_15=$RDI_DATADIR/xsim/ip/xfft_v9_0_15 +axi_register_slice_v2_1_17=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_17 +axi4stream_vip_v1_1_3=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_3 +xfft_v7_2_7=$RDI_DATADIR/xsim/ip/xfft_v7_2_7 +xbip_utils_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_9 +axi_tft_v2_0_20=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_20 +l_ethernet_v2_3_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_3 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +v_frmbuf_wr_v2_0_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_0_3 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +axi_data_fifo_v2_1_16=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_16 +audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 +usxgmii_v1_0_3=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_3 +dist_mem_gen_v8_0_12=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_12 +mailbox_v2_1_10=$RDI_DATADIR/xsim/ip/mailbox_v2_1_10 +v_demosaic_v1_0_3=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_3 +ethernet_1_10_25g_v2_1_0=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_0 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +axi_traffic_gen_v2_0_18=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_18 +axi_dma_v7_1_18=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_18 +axi_ahblite_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_14 +axi_sg_v4_1_10=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_10 +xbip_dsp48_multadd_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_5 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +rxaui_v4_4_4=$RDI_DATADIR/xsim/ip/rxaui_v4_4_4 +v_ycrcb2rgb_v7_1_12=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_12 +video_frame_crc_v1_0_0=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_0 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +pr_decoupler_v1_0_6=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_6 +tcc_encoder_3gpp_v5_0_13=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_13 +microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 +lib_fifo_v1_0_11=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_11 +v_letterbox_v1_0_11=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_11 +v_cresample_v4_0_13=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_13 +axi_msg_v1_0_3=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_3 +gtwizard_ultrascale_v1_7_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_4 +zynq_ultra_ps_e_v3_2_1=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_1 +c_mux_bit_v12_0_5=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_5 +axis_register_slice_v1_1_17=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_17 +hdcp22_cipher_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_2 +xfft_v9_1_0=$RDI_DATADIR/xsim/ip/xfft_v9_1_0 +axis_combiner_v1_1_15=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_15 +xbip_dsp48_multacc_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_5 +lmb_bram_if_cntlr_v4_0_15=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_15 +zynq_ultra_ps_e_vip_v1_0_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_3 +axi_protocol_checker_v1_1_17=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v1_1_17 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +axis_protocol_checker_v2_0_1=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_1 +ieee802d3_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_13 +v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 +tsn_temac_v1_0_3=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_3 +xlslice_v1_0_1=$RDI_DATADIR/xsim/ip/xlslice_v1_0_1 +fec_5g_common_v1_0_0=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_0 +oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 +rs_decoder_v9_0_14=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_14 +v_axi4s_remap_v1_0_9=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_9 +v_frmbuf_rd_v2_0_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_0_3 +ahblite_axi_bridge_v3_0_13=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_13 +axi_protocol_converter_v2_1_17=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_17 +axi_vfifo_ctrl_v2_0_19=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_19 +iomodule_v3_1_3=$RDI_DATADIR/xsim/ip/iomodule_v3_1_3 +xbip_multadd_v3_0_12=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_12 +rs_encoder_v9_0_13=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_13 +axis_switch_v1_1_17=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_17 +cordic_v6_0_14=$RDI_DATADIR/xsim/ip/cordic_v6_0_14 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +v_osd_v6_0_15=$RDI_DATADIR/xsim/ip/v_osd_v6_0_15 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +lte_fft_v2_0_16=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_16 +axi_gpio_v2_0_19=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_19 +xaui_v12_3_4=$RDI_DATADIR/xsim/ip/xaui_v12_3_4 +axis_subset_converter_v1_1_17=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_17 +axi_uart16550_v2_0_19=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_19 +ldpc_v2_0_1=$RDI_DATADIR/xsim/ip/ldpc_v2_0_1 +tsn_endpoint_ethernet_mac_block_v1_0_2=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_2 +v_frmbuf_wr_v2_1_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_0 +pr_bitstream_monitor_v1_0_0=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_0 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +axi_interconnect_v1_7_14=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_14 +lte_3gpp_channel_estimator_v2_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_15 +vid_phy_controller_v2_1_0=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_0 +xbip_counter_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_5 +etrnic_v1_0_1=$RDI_DATADIR/xsim/ip/etrnic_v1_0_1 +axi_timer_v2_0_19=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_19 +ta_dma_v1_0_1=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_1 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +axis_broadcaster_v1_1_16=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_16 +amm_axi_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_3 +fec_5g_common_v1_1_0=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +v_uhdsdi_vidgen_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_0 +lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 +lte_3gpp_mimo_encoder_v4_0_13=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_13 +c_addsub_v12_0_12=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_12 +c_mux_bus_v12_0_5=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_5 +axi_chip2chip_v5_0_3=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_3 +axis_dwidth_converter_v1_1_16=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_16 +processing_system7_vip_v1_0_5=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_5 +spdif_v2_0_19=$RDI_DATADIR/xsim/ip/spdif_v2_0_19 +v_tpg_v7_0_11=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_11 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +fifo_generator_v13_2_2=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_2 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +pr_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_0 +in_system_ibert_v1_0_7=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_7 +axi_amm_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_7 +xbip_accum_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_5 +sem_ultra_v3_1_8=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_8 +viterbi_v9_1_9=$RDI_DATADIR/xsim/ip/viterbi_v9_1_9 +high_speed_selectio_wiz_v3_4_0=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_0 +v_axi4s_vid_out_v4_0_9=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_9 +axi_iic_v2_0_20=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_20 +axi_hwicap_v3_0_21=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_21 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +system_cache_v4_0_5=$RDI_DATADIR/xsim/ip/system_cache_v4_0_5 +ieee802d3_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_1 +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +axis_interconnect_v1_1_15=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_15 +v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 +c_counter_binary_v12_0_12=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_12 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +fc32_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_7 +axi_vdma_v6_3_5=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_5 +fir_compiler_v5_2_5=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_5 +xpm=$RDI_DATADIR/xsim/ip/xpm +axi_mcdma_v1_0_3=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_3 +lte_pucch_receiver_v2_0_14=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_14 +proc_sys_reset_v5_0_12=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_12 +polar_v1_0_1=$RDI_DATADIR/xsim/ip/polar_v1_0_1 +tmr_sem_v1_0_5=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_5 +cic_compiler_v4_0_13=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_13 +mdm_v3_2_14=$RDI_DATADIR/xsim/ip/mdm_v3_2_14 +prc_v1_3_1=$RDI_DATADIR/xsim/ip/prc_v1_3_1 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +jesd204_v7_2_3=$RDI_DATADIR/xsim/ip/jesd204_v7_2_3 +axi_perf_mon_v5_0_19=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_19 +av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0 +axi_ethernetlite_v3_0_15=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_15 +sem_v4_1_11=$RDI_DATADIR/xsim/ip/sem_v4_1_11 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +switch_core_top_v1_0_5=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_5 +axi_pcie_v2_8_9=$RDI_DATADIR/xsim/ip/axi_pcie_v2_8_9 +v_dual_splitter_v1_0_8=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_8 +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +xbip_addsub_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_5 +ethernet_1_10_25g_v2_0_1=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_1 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +axi_mm2s_mapper_v1_1_16=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_16 +axis_protocol_checker_v1_1_16=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v1_1_16 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +c_accum_v12_0_12=$RDI_DATADIR/xsim/ip/c_accum_v12_0_12 +clk_vip_v1_0_1=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_1 +v_hcresampler_v1_0_11=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_11 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_1.xml b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..c05a117 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_10.xml b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..9808d4e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_2.xml b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..2d99861 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_3.xml b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..9808d4e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_4.xml b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..2bff947 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_5.xml b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..9808d4e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_6.xml b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..2bff947 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_7.xml b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..d4fb1ed --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_8.xml b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..9808d4e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_9.xml b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..9808d4e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc new file mode 100644 index 0000000..97ae30d --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc @@ -0,0 +1,3 @@ +set_property SRC_FILE_INFO {cfile:d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc rfile:../../../axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc id:1 order:EARLY scoped_inst:inst} [current_design] +set_property src_info {type:SCOPED_XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.05 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/.vivado.begin.rst b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/.vivado.begin.rst new file mode 100644 index 0000000..b2b9740 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/.vivado.end.rst b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/ISEWrap.js b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/ISEWrap.js new file mode 100644 index 0000000..898ddd7 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/ISEWrap.sh b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/__synthesis_is_complete__ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp new file mode 100644 index 0000000..df33166 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl new file mode 100644 index 0000000..49f1e3f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl @@ -0,0 +1,173 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7k160tffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/wt [current_project] +set_property parent.project_path D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.xpr [current_project] +set_property XPM_LIBRARIES XPM_CDC [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_repo_paths d:/Xilinx/xjtag/xjtag_ip/axi_bus_ip [current_project] +set_property ip_output_repo d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 0 + +set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1 -new_name clk_wiz_0 -ip [get_ips clk_wiz_0]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top clk_wiz_0 -part xc7k160tffg676-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix clk_wiz_0_ clk_wiz_0.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v + lappend ipCachedFiles clk_wiz_0_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl + lappend ipCachedFiles clk_wiz_0_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v + lappend ipCachedFiles clk_wiz_0_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl + lappend ipCachedFiles clk_wiz_0_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp clk_wiz_0.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips clk_wiz_0] +} + +rename_ref -prefix_all clk_wiz_0_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef clk_wiz_0.dcp +create_report "clk_wiz_0_synth_1_synth_report_utilization_0" "report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb" + +if { [catch { + file copy -force D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.v d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.vhdl d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.v d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.vhdl d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +}; # end if cached_ip + +if {[file isdir D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0]} { + catch { + file copy -force d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0 + } +} + +if {[file isdir D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0]} { + catch { + file copy -force d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.ip_user_files/ip/clk_wiz_0 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.vds b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.vds new file mode 100644 index 0000000..dc08b72 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.vds @@ -0,0 +1,334 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun Jun 28 17:09:33 2020 +# Process ID: 6452 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1 +# Command line: vivado.exe -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl +# Log file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.vds +# Journal file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1\vivado.jou +#----------------------------------------------------------- +source clk_wiz_0.tcl -notrace +Command: synth_design -top clk_wiz_0 -part xc7k160tffg676-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 8224 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 394.207 ; gain = 93.684 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] + Parameter CAPACITANCE bound to: DONT_CARE - type: string + Parameter DIFF_TERM bound to: FALSE - type: string + Parameter DQS_BIAS bound to: FALSE - type: string + Parameter IBUF_DELAY_VALUE bound to: 0 - type: string + Parameter IBUF_LOW_PWR bound to: TRUE - type: string + Parameter IFD_DELAY_VALUE bound to: AUTO - type: string + Parameter IOSTANDARD bound to: DEFAULT - type: string +INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (1#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: float + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float + Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float + Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string + Parameter COMPENSATION bound to: ZHOLD - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 + Parameter IS_PSEN_INVERTED bound to: 1'b0 + Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 + Parameter IS_PWRDWN_INVERTED bound to: 1'b0 + Parameter IS_RST_INVERTED bound to: 1'b0 + Parameter REF_JITTER1 bound to: 0.010000 - type: float + Parameter REF_JITTER2 bound to: 0.010000 - type: float + Parameter SS_EN bound to: FALSE - type: string + Parameter SS_MODE bound to: CENTER_HIGH - type: string + Parameter SS_MOD_PERIOD bound to: 10000 - type: integer + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (2#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (3#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (5#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.281 ; gain = 143.758 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.281 ; gain = 143.758 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.281 ; gain = 143.758 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 715.059 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 779.535 ; gain = 479.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 779.535 ; gain = 479.012 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 779.535 ; gain = 479.012 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |BUFG | 2| +|2 |MMCME2_ADV | 1| +|3 |IBUFDS | 1| ++------+-----------+------+ + +Report Instance Areas: ++------+---------+------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------+------+ +|1 |top | | 4| +|2 | inst |clk_wiz_0_clk_wiz | 4| ++------+---------+------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 781.172 ; gain = 209.871 +Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 781.180 ; gain = 480.648 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 802.621 ; gain = 513.566 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 806.949 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Sun Jun 28 17:10:06 2020... diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb new file mode 100644 index 0000000..c36a500 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt new file mode 100644 index 0000000..e3e1150 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt @@ -0,0 +1,175 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:10:06 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb +| Design : clk_wiz_0 +| Device : 7k160tffg676-2 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 0 | 0 | 101400 | 0.00 | +| LUT as Logic | 0 | 0 | 101400 | 0.00 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 0 | 0 | 202800 | 0.00 | +| Register as Flip Flop | 0 | 0 | 202800 | 0.00 | +| Register as Latch | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 2 | 0 | 400 | 0.50 | +| Bonded IPADs | 0 | 0 | 26 | 0.00 | +| Bonded OPADs | 0 | 0 | 16 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 1 | 0 | 384 | 0.26 | +| GTXE2_COMMON | 0 | 0 | 2 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 8 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 400 | 0.00 | +| OLOGIC | 0 | 0 | 400 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 2 | 0 | 32 | 6.25 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 1 | 0 | 8 | 12.50 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++------------+------+---------------------+ +| Ref Name | Used | Functional Category | ++------------+------+---------------------+ +| BUFG | 2 | Clock | +| MMCME2_ADV | 1 | Clock | +| IBUFDS | 1 | IO | ++------------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc new file mode 100644 index 0000000..e75204f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# IP: d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/gen_run.xml b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/gen_run.xml new file mode 100644 index 0000000..6493304 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/gen_run.xml @@ -0,0 +1,39 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/htr.txt b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/htr.txt new file mode 100644 index 0000000..fb945d9 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/project.wdf b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/project.wdf new file mode 100644 index 0000000..c6d0e70 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/project.wdf @@ -0,0 +1,34 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:32:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:32:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f315c636c6b5f77697a5f30:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c6178695f6770696f5f76325f305f31395c64657369676e5f315f6178695f6770696f5f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c786a7461675f6178695f76315f305f325c64657369676e5f315f786a7461675f6178695f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3733626362646633346363363435333262303965343637633530383430373331:506172656e742050412070726f6a656374204944:00 +eof:3060103038 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/rundef.js b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/rundef.js new file mode 100644 index 0000000..c2880b8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;"; +} else { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/runme.bat b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/runme.bat new file mode 100644 index 0000000..73c8b46 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/runme.log b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/runme.log new file mode 100644 index 0000000..2eccac6 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/runme.log @@ -0,0 +1,333 @@ + +*** Running vivado + with args -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source clk_wiz_0.tcl -notrace +Command: synth_design -top clk_wiz_0 -part xc7k160tffg676-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 8224 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 394.207 ; gain = 93.684 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] + Parameter CAPACITANCE bound to: DONT_CARE - type: string + Parameter DIFF_TERM bound to: FALSE - type: string + Parameter DQS_BIAS bound to: FALSE - type: string + Parameter IBUF_DELAY_VALUE bound to: 0 - type: string + Parameter IBUF_LOW_PWR bound to: TRUE - type: string + Parameter IFD_DELAY_VALUE bound to: AUTO - type: string + Parameter IOSTANDARD bound to: DEFAULT - type: string +INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (1#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: float + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float + Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float + Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string + Parameter COMPENSATION bound to: ZHOLD - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 + Parameter IS_PSEN_INVERTED bound to: 1'b0 + Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 + Parameter IS_PWRDWN_INVERTED bound to: 1'b0 + Parameter IS_RST_INVERTED bound to: 1'b0 + Parameter REF_JITTER1 bound to: 0.010000 - type: float + Parameter REF_JITTER2 bound to: 0.010000 - type: float + Parameter SS_EN bound to: FALSE - type: string + Parameter SS_MODE bound to: CENTER_HIGH - type: string + Parameter SS_MOD_PERIOD bound to: 10000 - type: integer + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (2#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (3#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (5#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.281 ; gain = 143.758 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.281 ; gain = 143.758 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.281 ; gain = 143.758 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 715.059 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 715.059 ; gain = 414.535 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 779.535 ; gain = 479.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 779.535 ; gain = 479.012 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 779.535 ; gain = 479.012 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |BUFG | 2| +|2 |MMCME2_ADV | 1| +|3 |IBUFDS | 1| ++------+-----------+------+ + +Report Instance Areas: ++------+---------+------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------+------+ +|1 |top | | 4| +|2 | inst |clk_wiz_0_clk_wiz | 4| ++------+---------+------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 781.172 ; gain = 480.648 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 781.172 ; gain = 209.871 +Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 781.180 ; gain = 480.648 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 802.621 ; gain = 513.566 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 806.949 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Sun Jun 28 17:10:06 2020... diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/runme.sh b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/runme.sh new file mode 100644 index 0000000..fe203a8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin +else + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/vivado.jou b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/vivado.jou new file mode 100644 index 0000000..53420fc --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun Jun 28 17:09:33 2020 +# Process ID: 6452 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1 +# Command line: vivado.exe -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl +# Log file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.vds +# Journal file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1\vivado.jou +#----------------------------------------------------------- +source clk_wiz_0.tcl -notrace diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/vivado.pb b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/vivado.pb new file mode 100644 index 0000000..cc3a52d Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/clk_wiz_0_synth_1/vivado.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.Vivado_Implementation.queue.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.init_design.begin.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..abc0986 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.init_design.end.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.opt_design.begin.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..abc0986 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.opt_design.end.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.place_design.begin.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..abc0986 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.place_design.end.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.route_design.begin.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..abc0986 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.route_design.end.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.vivado.begin.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..4d0861e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.vivado.end.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.write_bitstream.begin.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.write_bitstream.begin.rst new file mode 100644 index 0000000..abc0986 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.write_bitstream.end.rst b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/.write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/ISEWrap.js b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/ISEWrap.js new file mode 100644 index 0000000..898ddd7 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/ISEWrap.sh b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/gen_run.xml b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..22525fb --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/gen_run.xml @@ -0,0 +1,109 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/htr.txt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/htr.txt new file mode 100644 index 0000000..5ade73f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log t160_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/init_design.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/init_design.pb new file mode 100644 index 0000000..da09a89 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/init_design.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/opt_design.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..d0bb51f Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/opt_design.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/place_design.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/place_design.pb new file mode 100644 index 0000000..b48cf54 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/place_design.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/project.wdf b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/project.wdf new file mode 100644 index 0000000..d92e7cd --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/project.wdf @@ -0,0 +1,34 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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0000000..59036ea --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;"; +} else { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log t160_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/runme.bat b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/runme.bat new file mode 100644 index 0000000..73c8b46 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/runme.log b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/runme.log new file mode 100644 index 0000000..66d105b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/runme.log @@ -0,0 +1,519 @@ + +*** Running vivado + with args -log t160_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source t160_top.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Xilinx/xjtag/xjtag_ip/axi_bus_ip'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2018.2/data/ip'. +Command: link_design -top t160_top -part xc7k160tffg676-2 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Project 1-454] Reading design checkpoint 'd:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_uut' +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.2 +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_uut/inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_uut/inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_uut/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57] +INFO: [Timing 38-2] Deriving generated clocks [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57] +get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1215.945 ; gain = 569.516 +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_uut/inst' +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +13 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1215.945 ; gain = 922.664 +INFO: [Common 17-600] The following parameters have non-default value. +tcl.collectionResultDisplayLimit +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.840 . Memory (MB): peak = 1215.945 ; gain = 0.000 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1316a2ad9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1231.195 ; gain = 15.250 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 16c9a1f79 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.068 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 16c9a1f79 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1eb451d36 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 4 cells and removed 180 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1538d74eb + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.171 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1c55edb60 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 127f793b4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.249 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 127f793b4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.258 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 127f793b4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 127f793b4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx +Command: report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 101d1a060 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6fefd6f5 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: d336f18d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: d336f18d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: d336f18d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: d1c75eb9 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 2.2 Physical Synthesis In Placer +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------- +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +----------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.2 Physical Synthesis In Placer | Checksum: ebc621e4 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 16ac457a5 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 16ac457a5 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 8204cabd + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 85bad895 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 8f5e50ba + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 11f83c4ba + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: d1b450fd + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: d1b450fd + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: d1b450fd + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: febca9a6 + +Phase 4.1.1.1 BUFG Insertion +INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. +Phase 4.1.1.1 BUFG Insertion | Checksum: febca9a6 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 +INFO: [Place 30-746] Post Placement Timing Summary WNS=7.646. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: 13cce97ff + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 +Phase 4.1 Post Commit Optimization | Checksum: 13cce97ff + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 13cce97ff + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 13cce97ff + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 17232a056 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17232a056 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 +Ending Placer Task | Checksum: b69e6885 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 +INFO: [Common 17-83] Releasing license: Implementation +51 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 1237.301 ; gain = 6.105 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 1239.848 ; gain = 2.547 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file t160_top_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.073 . Memory (MB): peak = 1242.855 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file t160_top_utilization_placed.rpt -pb t160_top_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 1242.855 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file t160_top_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1242.855 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 352b954c ConstDB: 0 ShapeSum: 8172d339 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 5f8d60c8 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1431.848 ; gain = 188.992 +Post Restoration Checksum: NetGraph: 30a26099 NumContArr: 2eeb002f Constraints: 0 Timing: 0 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: 5f8d60c8 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1431.848 ; gain = 188.992 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: 5f8d60c8 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1436.453 ; gain = 193.598 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: 5f8d60c8 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1436.453 ; gain = 193.598 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: 25c1824e3 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.773 | TNS=0.000 | WHS=-0.121 | THS=-27.989| + +Phase 2 Router Initialization | Checksum: 20704431e + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1b0fffc2a + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 21 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.415 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: a3c24bf6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 +Phase 4 Rip-up And Reroute | Checksum: a3c24bf6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: a3c24bf6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: a3c24bf6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 +Phase 5 Delay and Skew Optimization | Checksum: a3c24bf6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: f70c9c41 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.501 | TNS=0.000 | WHS=0.080 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: f70c9c41 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 +Phase 6 Post Hold Fix | Checksum: f70c9c41 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0492231 % + Global Horizontal Routing Utilization = 0.0481245 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: b67e94a6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: b67e94a6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 135db133c + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=7.501 | TNS=0.000 | WHS=0.080 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: 135db133c + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 1454.324 ; gain = 211.469 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +68 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1454.324 ; gain = 211.469 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1454.324 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx +Command: report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx +Command: report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx +Command: report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +80 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file t160_top_route_status.rpt -pb t160_top_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file t160_top_timing_summary_routed.rpt -pb t160_top_timing_summary_routed.pb -rpx t160_top_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [runtcl-4] Executing : report_incremental_reuse -file t160_top_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file t160_top_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file t160_top_bus_skew_routed.rpt -pb t160_top_bus_skew_routed.pb -rpx t160_top_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force t160_top.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./t160_top.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +98 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1902.570 ; gain = 429.656 +INFO: [Common 17-206] Exiting Vivado at Tue Jun 30 17:35:53 2020... diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/runme.sh b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/runme.sh new file mode 100644 index 0000000..a83b77f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/runme.sh @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin +else + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log t160_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.bit b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.bit new file mode 100644 index 0000000..b8432a4 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.bit differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.hwdef b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.hwdef new file mode 100644 index 0000000..910f7a0 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.hwdef differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.sysdef b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.sysdef new file mode 100644 index 0000000..0565c97 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.sysdef differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.tcl b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.tcl new file mode 100644 index 0000000..fe07943 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.tcl @@ -0,0 +1,184 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {HDL-1065} -limit 10000 + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param tcl.collectionResultDisplayLimit 0 + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7k160tffg676-2 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/wt [current_project] + set_property parent.project_path D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.xpr [current_project] + set_property ip_repo_paths D:/Xilinx/xjtag/xjtag_ip/axi_bus_ip [current_project] + set_property ip_output_repo D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + set_property XPM_LIBRARIES XPM_CDC [current_project] + add_files -quiet D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.dcp + set_msg_config -source 4 -id {BD 41-1661} -limit 0 + set_param project.isImplRun true + add_files D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1.bd + read_ip -quiet D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci + set_param project.isImplRun false + read_xdc D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc + set_param project.isImplRun true + link_design -top t160_top -part xc7k160tffg676-2 + set_param project.isImplRun false + write_hwdef -force -file t160_top.hwdef + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force t160_top_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force t160_top_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file t160_top_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file t160_top_utilization_placed.rpt -pb t160_top_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file t160_top_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force t160_top_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file t160_top_route_status.rpt -pb t160_top_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file t160_top_timing_summary_routed.rpt -pb t160_top_timing_summary_routed.pb -rpx t160_top_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file t160_top_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file t160_top_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file t160_top_bus_skew_routed.rpt -pb t160_top_bus_skew_routed.pb -rpx t160_top_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force t160_top_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_property XPM_LIBRARIES XPM_CDC [current_project] + catch { write_mem_info -force t160_top.mmi } + write_bitstream -force t160_top.bit + catch { write_sysdef -hwdef t160_top.hwdef -bitfile t160_top.bit -meminfo t160_top.mmi -file t160_top.sysdef } + catch {write_debug_probes -quiet -force t160_top} + catch {file copy -force t160_top.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.vdi b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.vdi new file mode 100644 index 0000000..3a8d3d3 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.vdi @@ -0,0 +1,520 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jun 30 17:34:30 2020 +# Process ID: 8920 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1 +# Command line: vivado.exe -log t160_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace +# Log file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.vdi +# Journal file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source t160_top.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Xilinx/xjtag/xjtag_ip/axi_bus_ip'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2018.2/data/ip'. +Command: link_design -top t160_top -part xc7k160tffg676-2 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Project 1-454] Reading design checkpoint 'd:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_uut' +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.2 +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_uut/inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_uut/inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_uut/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57] +INFO: [Timing 38-2] Deriving generated clocks [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57] +get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1215.945 ; gain = 569.516 +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_uut/inst' +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +13 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1215.945 ; gain = 922.664 +INFO: [Common 17-600] The following parameters have non-default value. +tcl.collectionResultDisplayLimit +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.840 . Memory (MB): peak = 1215.945 ; gain = 0.000 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1316a2ad9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1231.195 ; gain = 15.250 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 16c9a1f79 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.068 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 16c9a1f79 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1eb451d36 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 4 cells and removed 180 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1538d74eb + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.171 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1c55edb60 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 127f793b4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.249 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 127f793b4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.258 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 127f793b4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 127f793b4 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1231.195 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx +Command: report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 101d1a060 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 6fefd6f5 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: d336f18d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: d336f18d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: d336f18d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: d1c75eb9 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 2.2 Physical Synthesis In Placer +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------- +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +----------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.2 Physical Synthesis In Placer | Checksum: ebc621e4 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 16ac457a5 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 16ac457a5 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 8204cabd + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 85bad895 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 8f5e50ba + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 11f83c4ba + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: d1b450fd + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: d1b450fd + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: d1b450fd + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.195 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: febca9a6 + +Phase 4.1.1.1 BUFG Insertion +INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. +Phase 4.1.1.1 BUFG Insertion | Checksum: febca9a6 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 +INFO: [Place 30-746] Post Placement Timing Summary WNS=7.646. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: 13cce97ff + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 +Phase 4.1 Post Commit Optimization | Checksum: 13cce97ff + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 13cce97ff + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 13cce97ff + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 17232a056 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17232a056 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 +Ending Placer Task | Checksum: b69e6885 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1237.301 ; gain = 6.105 +INFO: [Common 17-83] Releasing license: Implementation +51 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 1237.301 ; gain = 6.105 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 1239.848 ; gain = 2.547 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file t160_top_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.073 . Memory (MB): peak = 1242.855 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file t160_top_utilization_placed.rpt -pb t160_top_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 1242.855 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file t160_top_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1242.855 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 352b954c ConstDB: 0 ShapeSum: 8172d339 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 5f8d60c8 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1431.848 ; gain = 188.992 +Post Restoration Checksum: NetGraph: 30a26099 NumContArr: 2eeb002f Constraints: 0 Timing: 0 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: 5f8d60c8 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1431.848 ; gain = 188.992 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: 5f8d60c8 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1436.453 ; gain = 193.598 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: 5f8d60c8 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1436.453 ; gain = 193.598 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: 25c1824e3 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.773 | TNS=0.000 | WHS=-0.121 | THS=-27.989| + +Phase 2 Router Initialization | Checksum: 20704431e + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1b0fffc2a + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 21 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.415 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: a3c24bf6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 +Phase 4 Rip-up And Reroute | Checksum: a3c24bf6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: a3c24bf6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: a3c24bf6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 +Phase 5 Delay and Skew Optimization | Checksum: a3c24bf6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: f70c9c41 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.501 | TNS=0.000 | WHS=0.080 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: f70c9c41 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 +Phase 6 Post Hold Fix | Checksum: f70c9c41 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0492231 % + Global Horizontal Routing Utilization = 0.0481245 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: b67e94a6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: b67e94a6 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 135db133c + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=7.501 | TNS=0.000 | WHS=0.080 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: 135db133c + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 1454.324 ; gain = 211.469 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 1454.324 ; gain = 211.469 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +68 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1454.324 ; gain = 211.469 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1454.324 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx +Command: report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx +Command: report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx +Command: report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +80 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file t160_top_route_status.rpt -pb t160_top_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file t160_top_timing_summary_routed.rpt -pb t160_top_timing_summary_routed.pb -rpx t160_top_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [runtcl-4] Executing : report_incremental_reuse -file t160_top_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file t160_top_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file t160_top_bus_skew_routed.rpt -pb t160_top_bus_skew_routed.pb -rpx t160_top_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force t160_top.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./t160_top.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +98 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1902.570 ; gain = 429.656 +INFO: [Common 17-206] Exiting Vivado at Tue Jun 30 17:35:53 2020... diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_bus_skew_routed.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_bus_skew_routed.pb new file mode 100644 index 0000000..3390588 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_bus_skew_routed.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_bus_skew_routed.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_bus_skew_routed.rpt new file mode 100644 index 0000000..7bd6c5e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_bus_skew_routed.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:35:34 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_bus_skew -warn_on_violation -file t160_top_bus_skew_routed.rpt -pb t160_top_bus_skew_routed.pb -rpx t160_top_bus_skew_routed.rpx +| Design : t160_top +| Device : 7k160t-ffg676 +| Speed File : -2 PRODUCTION 1.12 2017-02-17 +--------------------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_bus_skew_routed.rpx b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_bus_skew_routed.rpx new file mode 100644 index 0000000..b9300c6 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_bus_skew_routed.rpx differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_clock_utilization_routed.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_clock_utilization_routed.rpt new file mode 100644 index 0000000..f0572b3 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_clock_utilization_routed.rpt @@ -0,0 +1,248 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:35:34 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_clock_utilization -file t160_top_clock_utilization_routed.rpt +| Design : t160_top +| Device : 7k160t-ffg676 +| Speed File : -2 PRODUCTION 1.12 2017-02-17 +-------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Device Cell Placement Summary for Global Clock g1 +8. Device Cell Placement Summary for Global Clock g2 +9. Clock Region Cell Placement per Global Clock: Region X1Y1 +10. Clock Region Cell Placement per Global Clock: Region X0Y2 +11. Clock Region Cell Placement per Global Clock: Region X0Y3 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 3 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 120 | 0 | 0 | 0 | +| BUFIO | 0 | 32 | 0 | 0 | 0 | +| BUFMR | 0 | 16 | 0 | 0 | 0 | +| BUFR | 0 | 32 | 0 | 0 | 0 | +| MMCM | 1 | 8 | 0 | 0 | 0 | +| PLL | 0 | 8 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+----------------------------+-------------------------------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+----------------------------+-------------------------------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 2 | 681 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_uut/inst/clkout1_buf/O | clk_uut/inst/clk_out1 | +| g1 | src0 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | 1 | 1 | 0 | 5.000 | clkfbout_clk_wiz_0 | clk_uut/inst/clkf_buf/O | clk_uut/inst/clkfbout_buf_clk_wiz_0 | +| g2 | src0 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 0 | 6 | n/a | n/a | BUFG_inst/O | rstn | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+----------------------------+-------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-------------------------------------+---------------------------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-------------------------------------+---------------------------------+ +| src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X1Y1 | X1Y1 | 1 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_uut/inst/mmcm_adv_inst/CLKOUT0 | clk_uut/inst/clk_out1_clk_wiz_0 | +| src0 | g1 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X1Y1 | X1Y1 | 1 | 0 | 5.000 | clkfbout_clk_wiz_0 | clk_uut/inst/mmcm_adv_inst/CLKFBOUT | clk_uut/inst/clkfbout_clk_wiz_0 | +| src0 | g2 | MMCME2_ADV/LOCKED | None | MMCME2_ADV_X1Y1 | X1Y1 | 1 | 4 | | | clk_uut/inst/mmcm_adv_inst/LOCKED | clk_uut/inst/locked | ++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-------------------------------------+---------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y2 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 638 | 2200 | 261 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y3 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 43 | 2200 | 19 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 | +| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y4 | 0 | 0 | +| Y3 | 1 | 0 | +| Y2 | 2 | 0 | +| Y1 | 0 | 1 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+ +| g0 | BUFG/O | n/a | clk_out1_clk_wiz_0 | 10.000 | {0.000 5.000} | 681 | 0 | 0 | 0 | clk_uut/inst/clk_out1 | ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+------+----+ +| | X0 | X1 | ++----+------+----+ +| Y4 | 0 | 0 | +| Y3 | 43 | 0 | +| Y2 | 638 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+------+----+ + + +7. Device Cell Placement Summary for Global Clock g1 +---------------------------------------------------- + ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------+ +| g1 | BUFG/O | n/a | clkfbout_clk_wiz_0 | 5.000 | {0.000 2.500} | 0 | 0 | 1 | 0 | clk_uut/inst/clkfbout_buf_clk_wiz_0 | ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y4 | 0 | 0 | +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 0 | 1 | +| Y0 | 0 | 0 | ++----+----+----+ + + +8. Device Cell Placement Summary for Global Clock g2 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+------+ +| g2 | BUFG/O | n/a | | | | 6 | 0 | 0 | 0 | rstn | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y4 | 0 | 0 | +| Y3 | 0 | 0 | +| Y2 | 6 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +9. Clock Region Cell Placement per Global Clock: Region X1Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------------+ +| g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | clk_uut/inst/clkfbout_buf_clk_wiz_0 | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +10. Clock Region Cell Placement per Global Clock: Region X0Y2 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------+ +| g0 | n/a | BUFG/O | None | 638 | 0 | 638 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_uut/inst/clk_out1 | +| g2 | n/a | BUFG/O | None | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | rstn | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +11. Clock Region Cell Placement per Global Clock: Region X0Y3 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------------+ +| g0 | n/a | BUFG/O | None | 43 | 0 | 43 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_uut/inst/clk_out1 | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y1 [get_cells BUFG_inst] +set_property LOC BUFGCTRL_X0Y2 [get_cells clk_uut/inst/clkf_buf] +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_uut/inst/clkout1_buf] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y71 [get_ports sys_clkn] +set_property LOC IOB_X1Y72 [get_ports sys_clkp] + +# Clock net "rstn" driven by instance "BUFG_inst" located at site "BUFGCTRL_X0Y1" +#startgroup +create_pblock {CLKAG_rstn} +add_cells_to_pblock [get_pblocks {CLKAG_rstn}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="rstn"}]]] +resize_pblock [get_pblocks {CLKAG_rstn}] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2} +#endgroup + +# Clock net "clk_uut/inst/clk_out1" driven by instance "clk_uut/inst/clkout1_buf" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_uut/inst/clk_out1} +add_cells_to_pblock [get_pblocks {CLKAG_clk_uut/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_uut/inst/clk_out1"}]]] +resize_pblock [get_pblocks {CLKAG_clk_uut/inst/clk_out1}] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3} +#endgroup diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_control_sets_placed.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_control_sets_placed.rpt new file mode 100644 index 0000000..5440c0d --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_control_sets_placed.rpt @@ -0,0 +1,87 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:35:07 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_control_sets -verbose -file t160_top_control_sets_placed.rpt +| Design : t160_top +| Device : xc7k160t +------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 20 | +| Unused register locations in slices containing registers | 22 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 4 | 1 | +| 6 | 2 | +| 8 | 3 | +| 16+ | 14 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 334 | 40 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 380 | 49 | +| Yes | No | No | 4 | 1 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 644 | 67 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++------------------------+------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++------------------------+------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+------------------+----------------+ +| clk_uut/inst/clk_out1 | uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/ishift_cnt[5] | | 1 | 4 | +| clk_uut/inst/clk_out1 | uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/_n0207_inv | uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/M_AXI_ARESETN_inv | 1 | 6 | +| clk_uut/inst/clk_out1 | uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/ird_valid_icmd_rd[1]_AND_11_o | uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/M_AXI_ARESETN_inv | 1 | 6 | +| clk_uut/inst/clk_out1 | | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear | 1 | 8 | +| clk_uut/inst/clk_out1 | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2 | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr | 1 | 8 | +| clk_uut/inst/clk_out1 | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0 | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 1 | 8 | +| clk_uut/inst/clk_out1 | uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/dop_clk_r[2]_dop_clk_r[1]_AND_3_o | uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/Mcount_ishift_cnt_val | 2 | 16 | +| clk_uut/inst/clk_out1 | | uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/GND_5_o_init_txn_pulse_OR_42_o | 4 | 22 | +| clk_uut/inst/clk_out1 | uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/_n0293_inv | uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/M_AXI_ARESETN_inv | 4 | 64 | +| clk_uut/inst/clk_out1 | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0] | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 6 | 64 | +| clk_uut/inst/clk_out1 | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 5 | 64 | +| clk_uut/inst/clk_out1 | uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/_n0211_inv | uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/M_AXI_ARESETN_inv | 10 | 64 | +| clk_uut/inst/clk_out1 | uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/_n0216_inv | uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/M_AXI_ARESETN_inv | 6 | 64 | +| clk_uut/inst/clk_out1 | uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/_n0231_inv | uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/M_AXI_ARESETN_inv | 10 | 68 | +| clk_uut/inst/clk_out1 | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Not_Dual.gpio_Data_Out_reg[0][0] | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 8 | 72 | +| clk_uut/inst/clk_out1 | | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0] | 14 | 94 | +| clk_uut/inst/clk_out1 | | uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/M_AXI_ARESETN_inv | 13 | 128 | +| clk_uut/inst/clk_out1 | | uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[0] | 17 | 128 | +| clk_uut/inst/clk_out1 | uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/dop_clk_r[2]_dop_clk_r[1]_AND_3_o | uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/M_AXI_ARESETN_inv | 12 | 140 | +| clk_uut/inst/clk_out1 | | | 40 | 334 | ++------------------------+------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+------------------+----------------+ + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_opted.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_opted.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_opted.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_opted.rpt new file mode 100644 index 0000000..86f91e5 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:35:02 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx +| Design : t160_top +| Device : xc7k160tffg676-2 +| Speed File : -2 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_opted.rpx b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_opted.rpx new file mode 100644 index 0000000..32ed0fe Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_opted.rpx differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_routed.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_routed.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_routed.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_routed.rpt new file mode 100644 index 0000000..06435ce --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:35:29 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx +| Design : t160_top +| Device : xc7k160tffg676-2 +| Speed File : -2 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_routed.rpx b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_routed.rpx new file mode 100644 index 0000000..d208473 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_drc_routed.rpx differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_io_placed.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_io_placed.rpt new file mode 100644 index 0000000..ff5fb27 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_io_placed.rpt @@ -0,0 +1,718 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:35:07 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_io -file t160_top_io_placed.rpt +| Design : t160_top +| Device : xc7k160t +| Speed File : -2 +| Package : ffg676 +| Package Version : FINAL 2012-06-26 +| Package Pin Delay Version : VERS. 2.0 2012-06-26 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 6 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | | MGTXTXN3_116 | Gigabit | | | | | | | | | | | | | | | | +| A4 | | | MGTXTXP3_116 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| A12 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A13 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A17 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A18 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A19 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A20 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| A21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| A22 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| A23 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| A24 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| A25 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| A26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AA2 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA5 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA7 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA8 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA9 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA10 | sys_clkp | High Performance | IO_L14P_T2_SRCC_33 | INPUT | DIFF_SSTL15 | 33 | | | | NONE | | FIXED | | | | NONE | | | | +| AA11 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AA12 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA13 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA14 | | High Performance | IO_L7P_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA15 | | High Performance | IO_L7N_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA17 | | High Performance | IO_L11P_T1_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA18 | | High Performance | IO_L11N_T1_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA19 | | High Performance | IO_L16P_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA20 | | High Performance | IO_L16N_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA21 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| AA22 | | High Range | IO_L13N_T2_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA23 | | High Range | IO_L11P_T1_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA24 | | High Range | IO_L12N_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA25 | | High Range | IO_L7P_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB2 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB4 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB5 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB6 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB8 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AB9 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB10 | sys_clkn | High Performance | IO_L14N_T2_SRCC_33 | INPUT | DIFF_SSTL15 | 33 | | | | NONE | | FIXED | | | | NONE | | | | +| AB11 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB12 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB14 | | High Performance | IO_L10P_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB15 | | High Performance | IO_L10N_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB16 | | High Performance | IO_L12P_T1_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB17 | | High Performance | IO_L14P_T2_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB18 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AB19 | | High Performance | IO_L18P_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB20 | | High Performance | IO_L18N_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB21 | | High Range | IO_L18P_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB22 | | High Range | IO_L17P_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB24 | | High Range | IO_L11N_T1_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB25 | | High Range | IO_L7N_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB26 | | High Range | IO_L9P_T1_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC1 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC2 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC3 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AC6 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC7 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC9 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AC11 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC12 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC13 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC14 | | High Performance | IO_L8P_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC15 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AC16 | | High Performance | IO_L12N_T1_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC17 | | High Performance | IO_L14N_T2_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC18 | | High Performance | IO_L13P_T2_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC19 | | High Performance | IO_L17P_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AC21 | | High Range | IO_L18N_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC22 | | High Range | IO_L17N_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC23 | | High Range | IO_L14P_T2_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC24 | | High Range | IO_L14N_T2_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC25 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| AC26 | | High Range | IO_L9N_T1_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AD3 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD4 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD6 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AD8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD9 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD10 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD11 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AD13 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD14 | | High Performance | IO_L8N_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD15 | | High Performance | IO_L4P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD16 | | High Performance | IO_L6P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AD18 | | High Performance | IO_L13N_T2_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD19 | | High Performance | IO_L17N_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD20 | | High Performance | IO_L15P_T2_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD21 | | High Range | IO_L19P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD22 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| AD23 | | High Range | IO_L16P_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD24 | | High Range | IO_L16N_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD25 | | High Range | IO_L23P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD26 | | High Range | IO_L21P_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE2 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE3 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AE5 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE6 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE7 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE8 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AE10 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE11 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE12 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AE15 | | High Performance | IO_L4N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE16 | | High Performance | IO_L6N_T0_VREF_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE17 | | High Performance | IO_L1P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE18 | | High Performance | IO_L3P_T0_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE19 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AE20 | | High Performance | IO_L15N_T2_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE21 | | High Range | IO_L19N_T3_VREF_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE22 | | High Range | IO_L24P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE23 | | High Range | IO_L22P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AE25 | | High Range | IO_L23N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE26 | | High Range | IO_L21N_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AF2 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF3 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF4 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF5 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF6 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AF7 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF8 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF9 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF10 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AF12 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF13 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF14 | | High Performance | IO_L2P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF15 | | High Performance | IO_L2N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF16 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AF17 | | High Performance | IO_L1N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF18 | | High Performance | IO_L3N_T0_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF19 | | High Performance | IO_L5P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF20 | | High Performance | IO_L5N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AF22 | | High Range | IO_L24N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF23 | | High Range | IO_L22N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF24 | | High Range | IO_L20P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF25 | | High Range | IO_L20N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF26 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| B1 | | | MGTXTXN2_116 | Gigabit | | | | | | | | | | | | | | | | +| B2 | | | MGTXTXP2_116 | Gigabit | | | | | | | | | | | | | | | | +| B3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B5 | | | MGTXRXN3_116 | Gigabit | | | | | | | | | | | | | | | | +| B6 | | | MGTXRXP3_116 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B9 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B11 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B14 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| B15 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| B19 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B20 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| B21 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| B22 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| B23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B24 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| B25 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| B26 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C3 | | | MGTXRXN2_116 | Gigabit | | | | | | | | | | | | | | | | +| C4 | | | MGTXRXP2_116 | Gigabit | | | | | | | | | | | | | | | | +| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C8 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| C9 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C13 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| C14 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| C15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C16 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C19 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| C22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| C23 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| C24 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| C25 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| C26 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| D1 | | | MGTXTXN1_116 | Gigabit | | | | | | | | | | | | | | | | +| D2 | | | MGTXTXP1_116 | Gigabit | | | | | | | | | | | | | | | | +| D3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTREFCLK0N_116 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTREFCLK0P_116 | Gigabit | | | | | | | | | | | | | | | | +| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D8 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| D13 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D19 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| D21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| D22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| D23 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| D24 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| D25 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| D26 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E3 | | | MGTXRXN1_116 | Gigabit | | | | | | | | | | | | | | | | +| E4 | | | MGTXRXP1_116 | Gigabit | | | | | | | | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| E10 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E11 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E12 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| E20 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| E21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| E22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| E23 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| E24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E25 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| E26 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| F1 | | | MGTXTXN0_116 | Gigabit | | | | | | | | | | | | | | | | +| F2 | | | MGTXTXP0_116 | Gigabit | | | | | | | | | | | | | | | | +| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F5 | | | MGTREFCLK1N_116 | Gigabit | | | | | | | | | | | | | | | | +| F6 | | | MGTREFCLK1P_116 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| F9 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F13 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| F17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F18 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F19 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| F21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F22 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| F23 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| F24 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| F25 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| F26 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| G3 | | | MGTXRXN0_116 | Gigabit | | | | | | | | | | | | | | | | +| G4 | | | MGTXRXP0_116 | Gigabit | | | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| G7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| G10 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| G11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| G12 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G14 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| G15 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G16 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G19 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| G20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G21 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| G22 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| G23 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| G24 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| G25 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| G26 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| H1 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| H2 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| H3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | | +| H6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H9 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| H11 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| H12 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H13 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H16 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| H21 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| H22 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| H23 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| H24 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| H25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H26 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J3 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| J4 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| J5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| J7 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| J8 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| J11 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| J14 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| J17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| J19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| J21 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| J22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J23 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| J24 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| J25 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| J26 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| K1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| K2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| K3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | | +| K6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K15 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| K19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K20 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| K21 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| K22 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| K23 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| K24 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| K25 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| K26 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| L1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| L3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| L4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| L5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| L7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| L8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L17 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| L18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| L19 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| L21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L22 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| L23 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| L24 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| L25 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| L26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| M2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| M3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| M4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M5 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | | +| M6 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| M12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| M18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| M19 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| M20 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M21 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M22 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M24 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M25 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| M26 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| N1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| N4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| N5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N6 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | | +| N7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N8 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| N12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N16 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| N20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N21 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| N22 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| N23 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| N24 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| N25 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| N26 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| P1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| P2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P16 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P18 | | High Range | IO_L24N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| P19 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| P20 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| P21 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| P22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| P23 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| P24 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| P25 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| P26 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| R1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| R4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| R5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| R7 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| R12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R16 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| R17 | led[0] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R18 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| R19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| R20 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| R21 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| R22 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| R23 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| R24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R25 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| R26 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| T1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T2 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T5 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| T6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| T7 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | | +| T8 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | | +| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T12 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| T17 | led[1] | High Range | IO_L23N_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T18 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| T19 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| T20 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T22 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T23 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T24 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T25 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T26 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| U1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| U4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U9 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| U12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| U16 | led[2] | High Range | IO_25_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U17 | led[3] | High Range | IO_L23P_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U19 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| U20 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| U21 | | High Range | IO_0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U22 | | High Range | IO_L1P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U23 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| U24 | | High Range | IO_L2P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U25 | | High Range | IO_L2N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U26 | | High Range | IO_L4P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| V1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V6 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V9 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| V11 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V12 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | | +| V13 | | High Performance | IO_0_VRN_32 | User IO | | 32 | | | | | | | | | | | | | | +| V14 | | High Performance | IO_L24P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V16 | | High Performance | IO_L20P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V17 | | High Performance | IO_L20N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V18 | | High Performance | IO_L23P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V19 | | High Performance | IO_L23N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V20 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| V21 | | High Range | IO_L6P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| V22 | | High Range | IO_L1N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| V23 | | High Range | IO_L3P_T0_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| V24 | | High Range | IO_L3N_T0_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| V25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V26 | | High Range | IO_L4N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| W1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W3 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| W8 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | +| W9 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| W10 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| W11 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W13 | | High Performance | IO_25_VRP_32 | User IO | | 32 | | | | | | | | | | | | | | +| W14 | | High Performance | IO_L24N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| W15 | | High Performance | IO_L22P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| W16 | | High Performance | IO_L22N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| W17 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| W18 | | High Performance | IO_L21P_T3_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| W19 | | High Performance | IO_L21N_T3_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L15P_T2_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| W21 | | High Range | IO_L6N_T0_VREF_12 | User IO | | 12 | | | | | | | | | | | | | | +| W22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W23 | | High Range | IO_L8P_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| W24 | | High Range | IO_L8N_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| W25 | | High Range | IO_L5P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| W26 | | High Range | IO_L5N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y3 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| Y5 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y6 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y7 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y8 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y10 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y11 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y12 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y13 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y14 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| Y15 | | High Performance | IO_L9P_T1_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y16 | | High Performance | IO_L9N_T1_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y17 | | High Performance | IO_L19P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y18 | | High Performance | IO_L19N_T3_VREF_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y20 | | High Range | IO_25_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y21 | | High Range | IO_L15N_T2_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y22 | | High Range | IO_L13P_T2_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y23 | | High Range | IO_L12P_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y24 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| Y25 | | High Range | IO_L10P_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y26 | | High Range | IO_L10N_T1_12 | User IO | | 12 | | | | | | | | | | | | | | ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_methodology_drc_routed.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_methodology_drc_routed.pb new file mode 100644 index 0000000..210b56b Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_methodology_drc_routed.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpt new file mode 100644 index 0000000..172689b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpt @@ -0,0 +1,34 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:35:30 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx +| Design : t160_top +| Device : xc7k160tffg676-2 +| Speed File : -2 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpx b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpx new file mode 100644 index 0000000..cfaf740 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpx differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_opt.dcp b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_opt.dcp new file mode 100644 index 0000000..96394ed Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_opt.dcp differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_placed.dcp b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_placed.dcp new file mode 100644 index 0000000..7705dd2 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_placed.dcp differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_power_routed.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_power_routed.rpt new file mode 100644 index 0000000..f14ebb7 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_power_routed.rpt @@ -0,0 +1,164 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:35:32 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx +| Design : t160_top +| Device : xc7k160tffg676-2 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.230 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.116 | +| Device Static (W) | 0.114 | +| Effective TJA (C/W) | 1.9 | +| Max Ambient (C) | 84.6 | +| Junction Temperature (C) | 25.4 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.004 | 5 | --- | --- | +| Slice Logic | <0.001 | 972 | --- | --- | +| LUT as Logic | <0.001 | 257 | 101400 | 0.25 | +| Register | <0.001 | 681 | 202800 | 0.34 | +| CARRY4 | <0.001 | 2 | 25350 | <0.01 | +| BUFG | 0.000 | 1 | 32 | 3.13 | +| Others | 0.000 | 20 | --- | --- | +| Signals | <0.001 | 732 | --- | --- | +| MMCM | 0.107 | 1 | 8 | 12.50 | +| I/O | 0.004 | 6 | 400 | 1.50 | +| Static Power | 0.114 | | | | +| Total | 0.230 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.047 | 0.007 | 0.041 | +| Vccaux | 1.800 | 0.079 | 0.061 | 0.018 | +| Vcco33 | 3.300 | 0.001 | 0.000 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | High | User specified more than 95% of inputs | | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 1.9 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 3.4 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++--------------------+---------------------------------+-----------------+ +| Clock | Domain | Constraint (ns) | ++--------------------+---------------------------------+-----------------+ +| clk_out1_clk_wiz_0 | clk_uut/inst/clk_out1_clk_wiz_0 | 10.0 | +| clkfbout_clk_wiz_0 | clk_uut/inst/clkfbout_clk_wiz_0 | 5.0 | +| sys_clkp | sys_clkp | 5.0 | ++--------------------+---------------------------------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-----------------------------------------+-----------+ +| Name | Power (W) | ++-----------------------------------------+-----------+ +| t160_top | 0.116 | +| clk_uut | 0.112 | +| inst | 0.112 | +| uut | 0.004 | +| design_1_i | 0.004 | +| axi_gpio_0 | 0.002 | +| U0 | 0.002 | +| AXI_LITE_IPIF_I | <0.001 | +| I_SLAVE_ATTACHMENT | <0.001 | +| I_DECODER | <0.001 | +| gpio_core_1 | 0.001 | +| Not_Dual.INPUT_DOUBLE_REGS3 | <0.001 | +| xjtag_axi_0 | 0.002 | +| inst | 0.002 | ++-----------------------------------------+-----------+ + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_power_routed.rpx b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_power_routed.rpx new file mode 100644 index 0000000..0019ce2 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_power_routed.rpx differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_power_summary_routed.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_power_summary_routed.pb new file mode 100644 index 0000000..d5747b3 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_power_summary_routed.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_route_status.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_route_status.pb new file mode 100644 index 0000000..e234774 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_route_status.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_route_status.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_route_status.rpt new file mode 100644 index 0000000..c9a0942 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 1394 : + # of nets not needing routing.......... : 654 : + # of internally routed nets........ : 654 : + # of routable nets..................... : 740 : + # of fully routed nets............. : 740 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_routed.dcp b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_routed.dcp new file mode 100644 index 0000000..02767e6 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_routed.dcp differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_timing_summary_routed.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_timing_summary_routed.pb new file mode 100644 index 0000000..cf1b636 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_timing_summary_routed.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_timing_summary_routed.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_timing_summary_routed.rpt new file mode 100644 index 0000000..bb57c12 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_timing_summary_routed.rpt @@ -0,0 +1,1483 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:35:32 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_timing_summary -max_paths 10 -file t160_top_timing_summary_routed.rpt -pb t160_top_timing_summary_routed.pb -rpx t160_top_timing_summary_routed.rpx -warn_on_violation +| Design : t160_top +| Device : 7k160t-ffg676 +| Speed File : -2 PRODUCTION 1.12 2017-02-17 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 4 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 7.504 0.000 0 1211 0.084 0.000 0 1211 1.100 0.000 0 687 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +sys_clkp {0.000 2.500} 5.000 200.000 + clk_out1_clk_wiz_0 {0.000 5.000} 10.000 100.000 + clkfbout_clk_wiz_0 {0.000 2.500} 5.000 200.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +sys_clkp 1.100 0.000 0 1 + clk_out1_clk_wiz_0 7.504 0.000 0 1211 0.084 0.000 0 1211 4.600 0.000 0 683 + clkfbout_clk_wiz_0 3.592 0.000 0 3 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_clkp + To Clock: sys_clkp + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.100ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_clkp +Waveform(ns): { 0.000 2.500 } +Period(ns): 5.000 +Sources: { sys_clkp } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.071 5.000 3.929 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 5.000 95.000 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 +Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 +High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_out1_clk_wiz_0 + To Clock: clk_out1_clk_wiz_0 + +Setup : 0 Failing Endpoints, Worst Slack 7.504ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.084ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 4.600ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 7.504ns (required time - arrival time) + Source: uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/ishift_cnt_4/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_18/CE + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.085ns (logic 0.388ns (18.612%) route 1.697ns (81.388%)) + Logic Levels: 3 (LUT2=1 LUT6=2) + Clock Path Skew: -0.144ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.643ns = ( 8.357 - 10.000 ) + Source Clock Delay (SCD): -2.198ns + Clock Pessimism Removal (CPR): -0.698ns + Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.112ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.232 -2.198 uut/design_1_i/xjtag_axi_0/inst/m00_axi_aclk + SLICE_X40Y139 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/ishift_cnt_4/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y139 FDRE (Prop_fdre_C_Q) 0.259 -1.939 f uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/ishift_cnt_4/Q + net (fo=4, routed) 0.473 -1.466 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/ishift_cnt[4] + SLICE_X42Y138 LUT2 (Prop_lut2_I0_O) 0.043 -1.423 f uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/chip_r[1]_ishift_cnt[7]_AND_9_o1_SW0/O + net (fo=2, routed) 0.275 -1.148 uut/design_1_i/xjtag_axi_0/inst/N8 + SLICE_X43Y138 LUT6 (Prop_lut6_I5_O) 0.043 -1.105 r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/chip_r[1]_ishift_cnt[7]_AND_9_o1/O + net (fo=3, routed) 0.255 -0.850 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/chip_r[1]_ishift_cnt[7]_AND_9_o1 + SLICE_X42Y138 LUT6 (Prop_lut6_I4_O) 0.043 -0.807 r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/_n0231_inv1/O + net (fo=34, routed) 0.694 -0.113 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/_n0231_inv + SLICE_X39Y150 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_18/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.088 8.357 uut/design_1_i/xjtag_axi_0/inst/m00_axi_aclk + SLICE_X39Y150 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_18/C + clock pessimism -0.698 7.658 + clock uncertainty -0.066 7.592 + SLICE_X39Y150 FDRE (Setup_fdre_C_CE) -0.201 7.391 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_18 + ------------------------------------------------------------------- + required time 7.391 + arrival time 0.113 + ------------------------------------------------------------------- + slack 7.504 + +Slack (MET) : 7.521ns (required time - arrival time) + Source: uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/ip2bus_data_i_D1_reg[17]/D + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.424ns (logic 0.345ns (14.235%) route 2.079ns (85.765%)) + Logic Levels: 2 (LUT5=2) + Clock Path Skew: -0.023ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.627ns = ( 8.373 - 10.000 ) + Source Clock Delay (SCD): -2.197ns + Clock Pessimism Removal (CPR): -0.592ns + Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.112ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.233 -2.197 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_aclk + SLICE_X38Y140 FDRE r uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X38Y140 FDRE (Prop_fdre_C_Q) 0.259 -1.938 f uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]/Q + net (fo=3, routed) 0.531 -1.407 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg + SLICE_X38Y141 LUT5 (Prop_lut5_I2_O) 0.043 -1.364 r uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/ip2bus_data_i_D1[0]_i_2/O + net (fo=32, routed) 1.548 0.184 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/ip2bus_data_i_D1[0]_i_2_n_0 + SLICE_X41Y149 LUT5 (Prop_lut5_I0_O) 0.043 0.227 r uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/ip2bus_data_i_D1[17]_i_1/O + net (fo=1, routed) 0.000 0.227 uut/design_1_i/axi_gpio_0/U0/ip2bus_data[17] + SLICE_X41Y149 FDRE r uut/design_1_i/axi_gpio_0/U0/ip2bus_data_i_D1_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.104 8.373 uut/design_1_i/axi_gpio_0/U0/s_axi_aclk + SLICE_X41Y149 FDRE r uut/design_1_i/axi_gpio_0/U0/ip2bus_data_i_D1_reg[17]/C + clock pessimism -0.592 7.780 + clock uncertainty -0.066 7.714 + SLICE_X41Y149 FDRE (Setup_fdre_C_D) 0.034 7.748 uut/design_1_i/axi_gpio_0/U0/ip2bus_data_i_D1_reg[17] + ------------------------------------------------------------------- + required time 7.748 + arrival time -0.227 + ------------------------------------------------------------------- + slack 7.521 + +Slack (MET) : 7.537ns (required time - arrival time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg[30]/R + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.069ns (logic 0.266ns (12.855%) route 1.803ns (87.145%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.630ns = ( 8.370 - 10.000 ) + Source Clock Delay (SCD): -2.197ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.112ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.233 -2.197 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X37Y141 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y141 FDRE (Prop_fdre_C_Q) 0.223 -1.974 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/Q + net (fo=5, routed) 0.707 -1.267 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GPIO_xferAck_i + SLICE_X37Y141 LUT4 (Prop_lut4_I1_O) 0.043 -1.224 r uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_1/O + net (fo=64, routed) 1.096 -0.128 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/bus2ip_rnw_i_reg + SLICE_X46Y144 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg[30]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.101 8.370 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X46Y144 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg[30]/C + clock pessimism -0.612 7.757 + clock uncertainty -0.066 7.691 + SLICE_X46Y144 FDRE (Setup_fdre_C_R) -0.281 7.410 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg1_reg[30] + ------------------------------------------------------------------- + required time 7.410 + arrival time 0.128 + ------------------------------------------------------------------- + slack 7.537 + +Slack (MET) : 7.537ns (required time - arrival time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg[30]/R + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.069ns (logic 0.266ns (12.855%) route 1.803ns (87.145%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.630ns = ( 8.370 - 10.000 ) + Source Clock Delay (SCD): -2.197ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.112ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.233 -2.197 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X37Y141 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y141 FDRE (Prop_fdre_C_Q) 0.223 -1.974 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/Q + net (fo=5, routed) 0.707 -1.267 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GPIO_xferAck_i + SLICE_X37Y141 LUT4 (Prop_lut4_I1_O) 0.043 -1.224 r uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_1/O + net (fo=64, routed) 1.096 -0.128 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/bus2ip_rnw_i_reg + SLICE_X46Y144 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg[30]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.101 8.370 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X46Y144 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg[30]/C + clock pessimism -0.612 7.757 + clock uncertainty -0.066 7.691 + SLICE_X46Y144 FDRE (Setup_fdre_C_R) -0.281 7.410 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].reg2_reg[30] + ------------------------------------------------------------------- + required time 7.410 + arrival time 0.128 + ------------------------------------------------------------------- + slack 7.537 + +Slack (MET) : 7.537ns (required time - arrival time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg[4]/R + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.069ns (logic 0.266ns (12.855%) route 1.803ns (87.145%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.630ns = ( 8.370 - 10.000 ) + Source Clock Delay (SCD): -2.197ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.112ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.233 -2.197 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X37Y141 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y141 FDRE (Prop_fdre_C_Q) 0.223 -1.974 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/Q + net (fo=5, routed) 0.707 -1.267 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GPIO_xferAck_i + SLICE_X37Y141 LUT4 (Prop_lut4_I1_O) 0.043 -1.224 r uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_1/O + net (fo=64, routed) 1.096 -0.128 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/bus2ip_rnw_i_reg + SLICE_X46Y144 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg[4]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.101 8.370 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X46Y144 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg[4]/C + clock pessimism -0.612 7.757 + clock uncertainty -0.066 7.691 + SLICE_X46Y144 FDRE (Setup_fdre_C_R) -0.281 7.410 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg[4] + ------------------------------------------------------------------- + required time 7.410 + arrival time 0.128 + ------------------------------------------------------------------- + slack 7.537 + +Slack (MET) : 7.537ns (required time - arrival time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg[4]/R + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.069ns (logic 0.266ns (12.855%) route 1.803ns (87.145%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.630ns = ( 8.370 - 10.000 ) + Source Clock Delay (SCD): -2.197ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.112ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.233 -2.197 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X37Y141 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y141 FDRE (Prop_fdre_C_Q) 0.223 -1.974 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/Q + net (fo=5, routed) 0.707 -1.267 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GPIO_xferAck_i + SLICE_X37Y141 LUT4 (Prop_lut4_I1_O) 0.043 -1.224 r uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_1/O + net (fo=64, routed) 1.096 -0.128 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/bus2ip_rnw_i_reg + SLICE_X46Y144 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg[4]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.101 8.370 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X46Y144 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg[4]/C + clock pessimism -0.612 7.757 + clock uncertainty -0.066 7.691 + SLICE_X46Y144 FDRE (Setup_fdre_C_R) -0.281 7.410 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg2_reg[4] + ------------------------------------------------------------------- + required time 7.410 + arrival time 0.128 + ------------------------------------------------------------------- + slack 7.537 + +Slack (MET) : 7.547ns (required time - arrival time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg[29]/R + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.058ns (logic 0.266ns (12.925%) route 1.792ns (87.075%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.048ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.632ns = ( 8.368 - 10.000 ) + Source Clock Delay (SCD): -2.197ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.112ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.233 -2.197 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X37Y141 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y141 FDRE (Prop_fdre_C_Q) 0.223 -1.974 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/Q + net (fo=5, routed) 0.707 -1.267 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GPIO_xferAck_i + SLICE_X37Y141 LUT4 (Prop_lut4_I1_O) 0.043 -1.224 r uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_1/O + net (fo=64, routed) 1.085 -0.139 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/bus2ip_rnw_i_reg + SLICE_X46Y140 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg[29]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.099 8.368 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X46Y140 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg[29]/C + clock pessimism -0.612 7.755 + clock uncertainty -0.066 7.689 + SLICE_X46Y140 FDRE (Setup_fdre_C_R) -0.281 7.408 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg1_reg[29] + ------------------------------------------------------------------- + required time 7.408 + arrival time 0.139 + ------------------------------------------------------------------- + slack 7.547 + +Slack (MET) : 7.547ns (required time - arrival time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg[29]/R + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.058ns (logic 0.266ns (12.925%) route 1.792ns (87.075%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.048ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.632ns = ( 8.368 - 10.000 ) + Source Clock Delay (SCD): -2.197ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.112ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.233 -2.197 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X37Y141 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y141 FDRE (Prop_fdre_C_Q) 0.223 -1.974 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/Q + net (fo=5, routed) 0.707 -1.267 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GPIO_xferAck_i + SLICE_X37Y141 LUT4 (Prop_lut4_I1_O) 0.043 -1.224 r uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_1/O + net (fo=64, routed) 1.085 -0.139 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/bus2ip_rnw_i_reg + SLICE_X46Y140 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg[29]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.099 8.368 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X46Y140 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg[29]/C + clock pessimism -0.612 7.755 + clock uncertainty -0.066 7.689 + SLICE_X46Y140 FDRE (Setup_fdre_C_R) -0.281 7.408 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].reg2_reg[29] + ------------------------------------------------------------------- + required time 7.408 + arrival time 0.139 + ------------------------------------------------------------------- + slack 7.547 + +Slack (MET) : 7.574ns (required time - arrival time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg[5]/R + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.010ns (logic 0.266ns (13.235%) route 1.744ns (86.765%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.630ns = ( 8.370 - 10.000 ) + Source Clock Delay (SCD): -2.197ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.112ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.233 -2.197 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X37Y141 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y141 FDRE (Prop_fdre_C_Q) 0.223 -1.974 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/Q + net (fo=5, routed) 0.707 -1.267 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GPIO_xferAck_i + SLICE_X37Y141 LUT4 (Prop_lut4_I1_O) 0.043 -1.224 r uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_1/O + net (fo=64, routed) 1.037 -0.187 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/bus2ip_rnw_i_reg + SLICE_X45Y145 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg[5]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.101 8.370 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X45Y145 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg[5]/C + clock pessimism -0.612 7.757 + clock uncertainty -0.066 7.691 + SLICE_X45Y145 FDRE (Setup_fdre_C_R) -0.304 7.387 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg1_reg[5] + ------------------------------------------------------------------- + required time 7.387 + arrival time 0.187 + ------------------------------------------------------------------- + slack 7.574 + +Slack (MET) : 7.574ns (required time - arrival time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg[5]/R + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.010ns (logic 0.266ns (13.235%) route 1.744ns (86.765%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.630ns = ( 8.370 - 10.000 ) + Source Clock Delay (SCD): -2.197ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.112ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.233 -2.197 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X37Y141 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y141 FDRE (Prop_fdre_C_Q) 0.223 -1.974 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/iGPIO_xferAck_reg/Q + net (fo=5, routed) 0.707 -1.267 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GPIO_xferAck_i + SLICE_X37Y141 LUT4 (Prop_lut4_I1_O) 0.043 -1.224 r uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].reg1[31]_i_1/O + net (fo=64, routed) 1.037 -0.187 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/bus2ip_rnw_i_reg + SLICE_X45Y145 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg[5]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 1.101 8.370 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X45Y145 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg[5]/C + clock pessimism -0.612 7.757 + clock uncertainty -0.066 7.691 + SLICE_X45Y145 FDRE (Setup_fdre_C_R) -0.304 7.387 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].reg2_reg[5] + ------------------------------------------------------------------- + required time 7.387 + arrival time 0.187 + ------------------------------------------------------------------- + slack 7.574 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.084ns (arrival time - required time) + Source: uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/axi_wdata_2/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_2/D + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.154ns (logic 0.100ns (65.134%) route 0.054ns (34.866%)) + Logic Levels: 0 + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.593ns + Source Clock Delay (SCD): -0.558ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.550 -0.558 uut/design_1_i/xjtag_axi_0/inst/m00_axi_aclk + SLICE_X41Y141 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/axi_wdata_2/C + ------------------------------------------------------------------- ------------------- + SLICE_X41Y141 FDRE (Prop_fdre_C_Q) 0.100 -0.458 r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/axi_wdata_2/Q + net (fo=1, routed) 0.054 -0.405 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/axi_wdata[2] + SLICE_X40Y141 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_2/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.749 -0.593 uut/design_1_i/xjtag_axi_0/inst/m00_axi_aclk + SLICE_X40Y141 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_2/C + clock pessimism 0.045 -0.547 + SLICE_X40Y141 FDRE (Hold_fdre_C_D) 0.059 -0.488 uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_2 + ------------------------------------------------------------------- + required time 0.488 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.085ns (arrival time - required time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[4]/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg[4]/D + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.183ns (logic 0.128ns (70.125%) route 0.055ns (29.875%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.595ns + Source Clock Delay (SCD): -0.559ns + Clock Pessimism Removal (CPR): -0.046ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.549 -0.559 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X47Y144 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y144 FDRE (Prop_fdre_C_Q) 0.100 -0.459 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[4]/Q + net (fo=1, routed) 0.055 -0.405 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/gpio_io_o[27] + SLICE_X46Y144 LUT5 (Prop_lut5_I0_O) 0.028 -0.377 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1[4]_i_1/O + net (fo=1, routed) 0.000 -0.377 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1[4]_i_1_n_0 + SLICE_X46Y144 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.747 -0.595 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk + SLICE_X46Y144 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg[4]/C + clock pessimism 0.046 -0.548 + SLICE_X46Y144 FDRE (Hold_fdre_C_D) 0.087 -0.461 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].reg1_reg[4] + ------------------------------------------------------------------- + required time 0.461 + arrival time -0.377 + ------------------------------------------------------------------- + slack 0.085 + +Slack (MET) : 0.092ns (arrival time - required time) + Source: uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/wdata_16/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/axi_wdata_16/D + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.190ns (logic 0.128ns (67.322%) route 0.062ns (32.678%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.591ns + Source Clock Delay (SCD): -0.556ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.552 -0.556 uut/design_1_i/xjtag_axi_0/inst/m00_axi_aclk + SLICE_X39Y147 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/wdata_16/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y147 FDRE (Prop_fdre_C_Q) 0.100 -0.456 r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/wdata_16/Q + net (fo=3, routed) 0.062 -0.394 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/wdata[16] + SLICE_X38Y147 LUT2 (Prop_lut2_I1_O) 0.028 -0.366 r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_16_xo<0>1/O + net (fo=1, routed) 0.000 -0.366 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT[16] + SLICE_X38Y147 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/axi_wdata_16/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.751 -0.591 uut/design_1_i/xjtag_axi_0/inst/m00_axi_aclk + SLICE_X38Y147 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/axi_wdata_16/C + clock pessimism 0.045 -0.545 + SLICE_X38Y147 FDRE (Hold_fdre_C_D) 0.087 -0.458 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/axi_wdata_16 + ------------------------------------------------------------------- + required time 0.458 + arrival time -0.366 + ------------------------------------------------------------------- + slack 0.092 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/read_data_17/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_19/D + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.370ns (logic 0.171ns (46.196%) route 0.199ns (53.804%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.190ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.600ns + Source Clock Delay (SCD): -0.556ns + Clock Pessimism Removal (CPR): -0.233ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.552 -0.556 uut/design_1_i/xjtag_axi_0/inst/m00_axi_aclk + SLICE_X40Y148 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/read_data_17/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y148 FDRE (Prop_fdre_C_Q) 0.107 -0.449 r uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/read_data_17/Q + net (fo=1, routed) 0.199 -0.250 uut/design_1_i/xjtag_axi_0/inst/xjtag_axi_v1_0_M00_AXI_inst/read_data[17] + SLICE_X40Y150 LUT5 (Prop_lut5_I1_O) 0.064 -0.186 r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/Mmux_oshift[33]_oshift[33]_mux_91_OUT111/O + net (fo=1, routed) 0.000 -0.186 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT[19] + SLICE_X40Y150 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_19/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.742 -0.600 uut/design_1_i/xjtag_axi_0/inst/m00_axi_aclk + SLICE_X40Y150 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_19/C + clock pessimism 0.233 -0.366 + SLICE_X40Y150 FDRE (Hold_fdre_C_D) 0.087 -0.279 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_19 + ------------------------------------------------------------------- + required time 0.279 + arrival time -0.186 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.096ns (arrival time - required time) + Source: uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/icrab_data_13/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_15/D + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.348ns (logic 0.146ns (41.969%) route 0.202ns (58.031%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.192ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.600ns + Source Clock Delay (SCD): -0.558ns + Clock Pessimism Removal (CPR): -0.233ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.550 -0.558 uut/design_1_i/xjtag_axi_0/inst/m00_axi_aclk + SLICE_X42Y146 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/icrab_data_13/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y146 FDRE (Prop_fdre_C_Q) 0.118 -0.440 r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/icrab_data_13/Q + net (fo=2, routed) 0.202 -0.239 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/icrab_data[13] + SLICE_X41Y150 LUT5 (Prop_lut5_I2_O) 0.028 -0.211 r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/Mmux_oshift[33]_oshift[33]_mux_91_OUT71/O + net (fo=1, routed) 0.000 -0.211 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT[15] + SLICE_X41Y150 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_15/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.742 -0.600 uut/design_1_i/xjtag_axi_0/inst/m00_axi_aclk + SLICE_X41Y150 FDRE r uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_15/C + clock pessimism 0.233 -0.366 + SLICE_X41Y150 FDRE (Hold_fdre_C_D) 0.060 -0.306 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/oshift_15 + ------------------------------------------------------------------- + required time 0.306 + arrival time -0.211 + ------------------------------------------------------------------- + slack 0.096 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/D + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.592ns + Source Clock Delay (SCD): -0.557ns + Clock Pessimism Removal (CPR): -0.034ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.551 -0.557 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_axi_aclk + SLICE_X41Y145 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/C + ------------------------------------------------------------------- ------------------- + SLICE_X41Y145 FDRE (Prop_fdre_C_Q) 0.100 -0.457 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/Q + net (fo=1, routed) 0.055 -0.403 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_level_out_bus_d2_11 + SLICE_X41Y145 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.750 -0.592 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_axi_aclk + SLICE_X41Y145 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/C + clock pessimism 0.034 -0.557 + SLICE_X41Y145 FDRE (Hold_fdre_C_D) 0.047 -0.510 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + ------------------------------------------------------------------- + required time 0.510 + arrival time -0.403 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/D + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.595ns + Source Clock Delay (SCD): -0.559ns + Clock Pessimism Removal (CPR): -0.035ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.549 -0.559 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_axi_aclk + SLICE_X47Y143 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y143 FDRE (Prop_fdre_C_Q) 0.100 -0.459 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/Q + net (fo=1, routed) 0.055 -0.405 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_level_out_bus_d2_1 + SLICE_X47Y143 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.747 -0.595 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_axi_aclk + SLICE_X47Y143 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/C + clock pessimism 0.035 -0.559 + SLICE_X47Y143 FDRE (Hold_fdre_C_D) 0.047 -0.512 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + ------------------------------------------------------------------- + required time 0.512 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/D + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.595ns + Source Clock Delay (SCD): -0.559ns + Clock Pessimism Removal (CPR): -0.035ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.549 -0.559 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_axi_aclk + SLICE_X47Y145 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y145 FDRE (Prop_fdre_C_Q) 0.100 -0.459 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/Q + net (fo=1, routed) 0.055 -0.405 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_level_out_bus_d2_24 + SLICE_X47Y145 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.747 -0.595 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_axi_aclk + SLICE_X47Y145 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/C + clock pessimism 0.035 -0.559 + SLICE_X47Y145 FDRE (Hold_fdre_C_D) 0.047 -0.512 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + ------------------------------------------------------------------- + required time 0.512 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/D + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.595ns + Source Clock Delay (SCD): -0.559ns + Clock Pessimism Removal (CPR): -0.035ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.549 -0.559 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_axi_aclk + SLICE_X45Y146 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/C + ------------------------------------------------------------------- ------------------- + SLICE_X45Y146 FDRE (Prop_fdre_C_Q) 0.100 -0.459 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/Q + net (fo=1, routed) 0.055 -0.405 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_level_out_bus_d2_26 + SLICE_X45Y146 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.747 -0.595 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_axi_aclk + SLICE_X45Y146 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/C + clock pessimism 0.035 -0.559 + SLICE_X45Y146 FDRE (Hold_fdre_C_D) 0.047 -0.512 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + ------------------------------------------------------------------- + required time 0.512 + arrival time -0.405 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/D + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.592ns + Source Clock Delay (SCD): -0.557ns + Clock Pessimism Removal (CPR): -0.034ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.551 -0.557 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_axi_aclk + SLICE_X41Y143 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/C + ------------------------------------------------------------------- ------------------- + SLICE_X41Y143 FDRE (Prop_fdre_C_Q) 0.100 -0.457 r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2/Q + net (fo=1, routed) 0.055 -0.403 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_level_out_bus_d2_29 + SLICE_X41Y143 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=681, routed) 0.750 -0.592 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/s_axi_aclk + SLICE_X41Y143 FDRE r uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/C + clock pessimism 0.034 -0.557 + SLICE_X41Y143 FDRE (Hold_fdre_C_D) 0.047 -0.510 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + ------------------------------------------------------------------- + required time 0.510 + arrival time -0.403 + ------------------------------------------------------------------- + slack 0.108 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_out1_clk_wiz_0 +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk_uut/inst/mmcm_adv_inst/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 1.409 10.000 8.592 BUFGCTRL_X0Y0 clk_uut/inst/clkout1_buf/I +Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.071 10.000 8.929 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKOUT0 +Min Period n/a FDRE/C n/a 0.750 10.000 9.250 SLICE_X44Y144 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[27]/C +Min Period n/a FDRE/C n/a 0.750 10.000 9.250 SLICE_X44Y144 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[3]/C +Min Period n/a FDRE/C n/a 0.750 10.000 9.250 SLICE_X44Y144 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[4]/C +Min Period n/a FDRE/C n/a 0.750 10.000 9.250 SLICE_X37Y145 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[5]/C +Min Period n/a FDRE/C n/a 0.750 10.000 9.250 SLICE_X37Y145 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[6]/C +Min Period n/a FDRE/C n/a 0.750 10.000 9.250 SLICE_X37Y145 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[7]/C +Min Period n/a FDRE/C n/a 0.750 10.000 9.250 SLICE_X37Y145 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[8]/C +Min Period n/a FDRE/C n/a 0.750 10.000 9.250 SLICE_X40Y146 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[9]/C +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKOUT0 +Low Pulse Width Fast FDRE/C n/a 0.400 5.000 4.600 SLICE_X48Y144 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3/C +Low Pulse Width Fast FDRE/C n/a 0.400 5.000 4.600 SLICE_X42Y136 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/addr_20/C +Low Pulse Width Fast FDRE/C n/a 0.400 5.000 4.600 SLICE_X42Y136 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/addr_21/C +Low Pulse Width Fast FDRE/C n/a 0.400 5.000 4.600 SLICE_X42Y136 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/addr_22/C +Low Pulse Width Fast FDRE/C n/a 0.400 5.000 4.600 SLICE_X42Y136 uut/design_1_i/xjtag_axi_0/inst/xjtag_bus_uut/addr_23/C +Low Pulse Width Fast FDRE/C n/a 0.400 5.000 4.600 SLICE_X48Y144 uut/design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4/C +Low Pulse Width Fast FDRE/C n/a 0.400 5.000 4.600 SLICE_X44Y144 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[27]/C +Low Pulse Width Fast FDRE/C n/a 0.400 5.000 4.600 SLICE_X44Y144 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[3]/C +Low Pulse Width Fast FDRE/C n/a 0.400 5.000 4.600 SLICE_X44Y144 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[4]/C +Low Pulse Width Slow FDRE/C n/a 0.400 5.000 4.600 SLICE_X37Y145 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[5]/C +High Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 SLICE_X44Y144 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[26]/C +High Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 SLICE_X44Y144 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[27]/C +High Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 SLICE_X37Y145 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[28]/C +High Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 SLICE_X37Y145 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[29]/C +High Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 SLICE_X44Y141 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[2]/C +High Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 SLICE_X44Y141 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[30]/C +High Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 SLICE_X44Y141 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[31]/C +High Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 SLICE_X44Y144 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[3]/C +High Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 SLICE_X44Y144 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[4]/C +High Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 SLICE_X37Y145 uut/design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[5]/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: clkfbout_clk_wiz_0 + To Clock: clkfbout_clk_wiz_0 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.592ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clkfbout_clk_wiz_0 +Waveform(ns): { 0.000 2.500 } +Period(ns): 5.000 +Sources: { clk_uut/inst/mmcm_adv_inst/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 1.409 5.000 3.592 BUFGCTRL_X0Y2 clk_uut/inst/clkf_buf/I +Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.071 5.000 3.929 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKFBOUT +Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.071 5.000 3.929 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKFBIN +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 5.000 95.000 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKFBIN +Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 5.000 208.360 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKFBOUT + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_timing_summary_routed.rpx b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_timing_summary_routed.rpx new file mode 100644 index 0000000..e4c6242 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_timing_summary_routed.rpx differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_utilization_placed.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_utilization_placed.pb new file mode 100644 index 0000000..69fa427 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_utilization_placed.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_utilization_placed.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_utilization_placed.rpt new file mode 100644 index 0000000..25df743 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top_utilization_placed.rpt @@ -0,0 +1,216 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:35:07 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_utilization -file t160_top_utilization_placed.rpt -pb t160_top_utilization_placed.pb +| Design : t160_top +| Device : 7k160tffg676-2 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 257 | 0 | 101400 | 0.25 | +| LUT as Logic | 257 | 0 | 101400 | 0.25 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 681 | 0 | 202800 | 0.34 | +| Register as Flip Flop | 681 | 0 | 202800 | 0.34 | +| Register as Latch | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 33 | Yes | Set | - | +| 648 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 157 | 0 | 25350 | 0.62 | +| SLICEL | 93 | 0 | | | +| SLICEM | 64 | 0 | | | +| LUT as Logic | 257 | 0 | 101400 | 0.25 | +| using O5 output only | 0 | | | | +| using O6 output only | 246 | | | | +| using O5 and O6 | 11 | | | | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 223 | 0 | 101400 | 0.22 | +| fully used LUT-FF pairs | 6 | | | | +| LUT-FF pairs with one unused LUT output | 217 | | | | +| LUT-FF pairs with one unused Flip Flop | 203 | | | | +| Unique Control Sets | 20 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 6 | 6 | 400 | 1.50 | +| IOB Master Pads | 2 | | | | +| IOB Slave Pads | 3 | | | | +| Bonded IPADs | 0 | 0 | 26 | 0.00 | +| Bonded OPADs | 0 | 0 | 16 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 1 | 1 | 384 | 0.26 | +| GTXE2_COMMON | 0 | 0 | 2 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 8 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 400 | 0.00 | +| OLOGIC | 0 | 0 | 400 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 3 | 0 | 32 | 9.38 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 1 | 0 | 8 | 12.50 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 1 | 0 | 4 | 25.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++------------+------+---------------------+ +| Ref Name | Used | Functional Category | ++------------+------+---------------------+ +| FDRE | 648 | Flop & Latch | +| LUT5 | 145 | LUT | +| LUT2 | 61 | LUT | +| FDSE | 33 | Flop & Latch | +| LUT6 | 21 | LUT | +| LUT4 | 20 | LUT | +| LUT3 | 17 | LUT | +| OBUF | 4 | IO | +| LUT1 | 4 | LUT | +| BUFG | 3 | Clock | +| CARRY4 | 2 | CarryLogic | +| MMCME2_ADV | 1 | Clock | +| IBUFDS | 1 | IO | +| BSCANE2 | 1 | Others | ++------------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++-----------+------+ +| Ref Name | Used | ++-----------+------+ +| xjtag_axi | 1 | +| clk_wiz_0 | 1 | ++-----------+------+ + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/usage_statistics_webtalk.html b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/usage_statistics_webtalk.html new file mode 100644 index 0000000..fb145f6 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,864 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedTue Jun 30 17:35:52 2020os_platformWIN64
product_versionVivado v2018.2 (64-bit)project_id73bcbdf34cc64532b09e467c50840731
project_iteration7random_idfb024045cda053fdb075e8f3e6f51813
registration_idfb024045cda053fdb075e8f3e6f51813route_designTRUE
target_devicexc7k160ttarget_familykintex7
target_packageffg676target_speed-2
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i5-6500 CPU @ 3.20GHzcpu_speed3192 MHz
os_nameMicrosoft Windows 7 , 64-bitos_releaseService Pack 1 (build 7601)
system_ram16.000 GBtotal_processors1

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vivado_usage
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gui_handlers
abstractcombinedpanel_remove_selected_elements=1addhdlwrapperdialog_this_option_will_make_copy=2addrepositoryinfodialog_ok=1addresstreetablepanel_address_tree_table=7
addsrcwizard_specify_or_create_constraint_files=1basedialog_apply=2basedialog_cancel=5basedialog_close=1
basedialog_ok=38basedialog_yes=7basereporttab_rerun=8constraintschooserpanel_add_files=1
coretreetablepanel_core_tree_table=11expruntreepanel_exp_run_tree_table=4filesetpanel_file_set_panel_tree=83flownavigatortreepanel_flow_navigator_tree=34
hardwaretreepanel_hardware_tree_table=14ipstatussectionpanel_upgrade_selected=9languagetemplatesdialog_templates_tree=38mainmenumgr_checkpoint=2
mainmenumgr_file=8mainmenumgr_ip=1mainmenumgr_project=4mainmenumgr_reports=2
mainmenumgr_tools=2openfileaction_cancel=1pacommandnames_auto_assign_address=1pacommandnames_auto_connect_ports=5
pacommandnames_auto_connect_target=6pacommandnames_close_project=4pacommandnames_create_top_hdl=2pacommandnames_generate_composite_file=4
pacommandnames_open_target_wizard=1pacommandnames_program_fpga=8pacommandnames_report_ip_status=1pacommandnames_reset_composite_file=1
pacommandnames_save_rsb_design=2pacommandnames_validate_rsb_design=1paviews_code=7paviews_ip_catalog=1
planaheadtab_refresh_ip_catalog=6programdebugtab_open_recently_opened_target=3programfpgadialog_program=8rsbexternalportproppanels_name=4
settingsdialog_project_tree=9settingsprojectiprepositorypage_add_repository=1simpleoutputproductdialog_generate_output_products_immediately=14simpleoutputproductdialog_reset_output_products=1
simpleoutputproductdialog_synthesize_design_globally=1srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1syntheticagettingstartedview_recent_projects=6systembuildermenu_end_connection_mode=2
systembuilderview_add_ip=2systembuilderview_pinning=2systemtab_report_ip_status=1systemtab_upgrade_later=1
taskbanner_close=19tclconsoleview_tcl_console_code_editor=3utilizationhierviewtreetablepanel_table(hierarchy)=2
+ + + + + + + + + + + + + + + + + + + + + + + + +
java_command_handlers
addsources=2autoassignaddress=1autoconnectport=5autoconnecttarget=6
closeproject=4coreview=1createtophdl=2customizecore=1
customizersbblock=4launchopentarget=1launchprogramfpga=8managecompositetargets=5
openhardwaremanager=7openrecenttarget=7reportipstatus=2reportutilization=1
runbitgen=7saversbdesign=1toolssettings=5toolstemplates=1
upgradeip=8validatersbdesign=1
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other_data
guimode=8
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project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=13export_simulation_ies=13
export_simulation_modelsim=13export_simulation_questa=13export_simulation_riviera=13export_simulation_vcs=13
export_simulation_xsim=13implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=3synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilogtarget_simulator=XSimtotalimplruns=2totalsynthesisruns=2
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + + + + + + + + +
post_unisim_transformation
bscane2=1bufg=3carry4=2fdre=766
fdse=33gnd=12ibufds=1lut1=11
lut2=119lut3=17lut4=20lut5=145
lut6=21mmcme2_adv=1obuf=4vcc=9
+
+ + + + + + + + + + + + + + + + + + +
pre_unisim_transformation
bscane2=1bufg=3carry4=2fdre=766
fdse=33gnd=12ibufds=1lut1=11
lut2=119lut3=17lut4=20lut5=145
lut6=21mmcme2_adv=1obuf=4vcc=9
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ip_statistics
+ + + + + + + + + + + + + + + + + + + + +
IP_Integrator/1
bdsource=USERcore_container=NAiptotal=1maxhierdepth=0
numblks=2numhdlrefblks=0numhierblks=0numhlsblks=0
numnonxlnxblks=0numpkgbdblks=0numreposblks=2numsysgenblks=0
synth_mode=Globalx_iplanguage=VERILOGx_iplibrary=BlockDiagramx_ipname=design_1
x_ipvendor=xilinx.comx_ipversion=1.00.a
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
axi_gpio/1
c_all_inputs=0c_all_inputs_2=0c_all_outputs=0c_all_outputs_2=0
c_dout_default=0x00000000c_dout_default_2=0x00000000c_family=kintex7c_gpio2_width=32
c_gpio_width=32c_interrupt_present=0c_is_dual=0c_s_axi_addr_width=9
c_s_axi_data_width=32c_tri_default=0xFFFFFFFFc_tri_default_2=0xFFFFFFFFcore_container=NA
iptotal=1x_ipcorerevision=19x_iplanguage=VERILOGx_iplibrary=ip
x_ipname=axi_gpiox_ipproduct=Vivado 2018.2x_ipsimlanguage=MIXEDx_ipvendor=xilinx.com
x_ipversion=2.0
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
clk_wiz_v6_0_1_0_0/1
clkin1_period=5.000clkin2_period=10.0clock_mgr_type=NAcomponent_name=clk_wiz_0
core_container=NAenable_axi=0feedback_source=FDBK_AUTOfeedback_type=SINGLE
iptotal=1manual_override=falsenum_out_clk=1primitive=MMCM
use_dyn_phase_shift=falseuse_dyn_reconfig=falseuse_inclk_stopped=falseuse_inclk_switchover=false
use_locked=trueuse_max_i_jitter=falseuse_min_o_jitter=falseuse_phase_alignment=true
use_power_down=falseuse_reset=false
+
+ + + + + + + + + + + + + +
xjtag_axi/1
core_container=NAiptotal=1jtag_sel=3x_ipcorerevision=2
x_iplanguage=VERILOGx_iplibrary=userx_ipname=xjtag_axix_ipproduct=Vivado 2018.2
x_ipsimlanguage=MIXEDx_ipvendor=xilinx.comx_ipversion=1.0
+

+ + + + +
report_drc
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command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-internal=default::[not_specified]-internal_only=default::[not_specified]-messages=default::[not_specified]
-name=default::[not_specified]-no_waivers=default::[not_specified]-return_string=default::[not_specified]-ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + +
results
cfgbvs-1=1
+

+ + + +
report_methodology
+ + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-waived=default::[not_specified]
+

+ + + + +
report_power
+ + + + + + + + + + + + + + + +
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-l=default::[not_specified]-name=default::[not_specified]-no_propagation=default::[not_specified]
-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]-vid=default::[not_specified]
-xpe=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")clocks=0.004368confidence_level_clock_activity=High
confidence_level_design_state=Highconfidence_level_device_models=Highconfidence_level_internal_activity=Mediumconfidence_level_io_activity=High
confidence_level_overall=Mediumcustomer=TBDcustomer_class=TBDdevstatic=0.113502
die=xc7k160tffg676-2dsp_output_toggle=12.500000dynamic=0.116034effective_thetaja=1.9
enable_probability=0.990000family=kintex7ff_toggle=12.500000flow_state=routed
heatsink=medium (Medium Profile)i/o=0.004082input_toggle=12.500000junction_temp=25.4 (C)
logic=0.000310mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000mgtvccaux_dynamic_current=0.000000mgtvccaux_static_current=0.000000mgtvccaux_total_current=0.000000
mgtvccaux_voltage=1.800000mmcm=0.106907netlist_net_matched=NAoff-chip_power=0.000000
on-chip_power=0.229536output_enable=1.000000output_load=5.000000output_toggle=12.500000
package=ffg676pct_clock_constrained=3.000000pct_inputs_defined=100platform=nt64
process=typicalram_enable=50.000000ram_write=50.000000read_saif=False
set/reset_probability=0.000000signal_rate=Falsesignals=0.000367simulation_file=None
speedgrade=-2static_prob=Falsetemp_grade=commercialthetajb=4.0 (C/W)
thetasa=3.4 (C/W)toggle_rate=Falseuser_board_temp=25.0 (C)user_effective_thetaja=1.9
user_junc_temp=25.4 (C)user_thetajb=4.0 (C/W)user_thetasa=3.4 (C/W)vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000vccadc_total_current=0.020000vccadc_voltage=1.800000vccaux_dynamic_current=0.060666
vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000
vccaux_static_current=0.018197vccaux_total_current=0.078864vccaux_voltage=1.800000vccbram_dynamic_current=0.000000
vccbram_static_current=0.000919vccbram_total_current=0.000919vccbram_voltage=1.000000vccint_dynamic_current=0.006681
vccint_static_current=0.040528vccint_total_current=0.047208vccint_voltage=1.000000vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000vcco12_total_current=0.000000vcco12_voltage=1.200000vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000vcco135_total_current=0.000000vcco135_voltage=1.350000vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000vcco15_total_current=0.000000vcco15_voltage=1.500000vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000vcco18_total_current=0.000000vcco18_voltage=1.800000vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000vcco25_total_current=0.000000vcco25_voltage=2.500000vcco33_dynamic_current=0.000047
vcco33_static_current=0.001000vcco33_total_current=0.001047vcco33_voltage=3.300000version=2018.2
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=3bufgctrl_util_percentage=9.38
bufhce_available=120bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=32bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=16bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=32bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=8mmcme2_adv_fixed=0mmcme2_adv_used=1mmcme2_adv_util_percentage=12.50
plle2_adv_available=8plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=600dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_i_dci=0
diff_hstl_i_dci_18=0diff_hstl_ii=0diff_hstl_ii_18=0diff_hstl_ii_dci=0
diff_hstl_ii_dci_18=0diff_hstl_ii_t_dci=0diff_hstl_ii_t_dci_18=0diff_hsul_12=0
diff_hsul_12_dci=0diff_mobile_ddr=0diff_sstl12=0diff_sstl12_dci=0
diff_sstl12_t_dci=0diff_sstl135=0diff_sstl135_dci=0diff_sstl135_r=0
diff_sstl135_t_dci=0diff_sstl15=1diff_sstl15_dci=0diff_sstl15_r=0
diff_sstl15_t_dci=0diff_sstl18_i=0diff_sstl18_i_dci=0diff_sstl18_ii=0
diff_sstl18_ii_dci=0diff_sstl18_ii_t_dci=0hslvdci_15=0hslvdci_18=0
hstl_i=0hstl_i_12=0hstl_i_18=0hstl_i_dci=0
hstl_i_dci_18=0hstl_ii=0hstl_ii_18=0hstl_ii_dci=0
hstl_ii_dci_18=0hstl_ii_t_dci=0hstl_ii_t_dci_18=0hsul_12=0
hsul_12_dci=0lvcmos12=0lvcmos15=0lvcmos18=0
lvcmos25=0lvcmos33=1lvdci_15=0lvdci_18=0
lvdci_dv2_15=0lvdci_dv2_18=0lvds=0lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl12=0sstl12_dci=0
sstl12_t_dci=0sstl135=0sstl135_dci=0sstl135_r=0
sstl135_t_dci=0sstl15=0sstl15_dci=0sstl15_r=0
sstl15_t_dci=0sstl18_i=0sstl18_i_dci=0sstl18_ii=0
sstl18_ii_dci=0sstl18_ii_t_dci=0tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=325block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=650ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=325ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
primitives
bscane2_functional_category=Othersbscane2_used=1bufg_functional_category=Clockbufg_used=3
carry4_functional_category=CarryLogiccarry4_used=2fdre_functional_category=Flop & Latchfdre_used=648
fdse_functional_category=Flop & Latchfdse_used=33ibufds_functional_category=IOibufds_used=1
lut1_functional_category=LUTlut1_used=4lut2_functional_category=LUTlut2_used=61
lut3_functional_category=LUTlut3_used=17lut4_functional_category=LUTlut4_used=20
lut5_functional_category=LUTlut5_used=145lut6_functional_category=LUTlut6_used=21
mmcme2_adv_functional_category=Clockmmcme2_adv_used=1obuf_functional_category=IOobuf_used=4
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=50700f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=25350f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=101400lut_as_logic_fixed=0lut_as_logic_used=257lut_as_logic_util_percentage=0.25
lut_as_memory_available=35000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=202800register_as_flip_flop_fixed=0register_as_flip_flop_used=681register_as_flip_flop_util_percentage=0.34
register_as_latch_available=202800register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=101400slice_luts_fixed=0slice_luts_used=257slice_luts_util_percentage=0.25
slice_registers_available=202800slice_registers_fixed=0slice_registers_used=681slice_registers_util_percentage=0.34
fully_used_lut_ff_pairs_fixed=0.34fully_used_lut_ff_pairs_used=6lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0
lut_as_logic_available=101400lut_as_logic_fixed=0lut_as_logic_used=257lut_as_logic_util_percentage=0.25
lut_as_memory_available=35000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0lut_as_shift_register_used=0lut_ff_pairs_with_one_unused_flip_flop_fixed=0lut_ff_pairs_with_one_unused_flip_flop_used=203
lut_ff_pairs_with_one_unused_lut_output_fixed=203lut_ff_pairs_with_one_unused_lut_output_used=217lut_flip_flop_pairs_available=101400lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=223lut_flip_flop_pairs_util_percentage=0.22slice_available=25350slice_fixed=0
slice_used=157slice_util_percentage=0.62slicel_fixed=0slicel_used=93
slicem_fixed=0slicem_used=64unique_control_sets_used=20using_o5_and_o6_fixed=20
using_o5_and_o6_used=11using_o5_output_only_fixed=11using_o5_output_only_used=0using_o6_output_only_fixed=0
using_o6_output_only_used=246
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=1bscane2_util_percentage=25.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + +
router
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
actual_expansions=1127107bogomips=0bram18=0bram36=0
bufg=0bufr=0congestion_level=0ctrls=20
dsp=0effort=2estimated_expansions=442884ff=681
global_clocks=3high_fanout_nets=1iob=6lut=262
movable_instances=980nets=1411pins=4933pll=0
router_runtime=0.000000router_timing_driven=1threads=2timing_constraints_exist=1
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7k160tffg676-2
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=t160_top-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:28shls_ip=0memory_gain=546.352MBmemory_peak=838.070MB
+

+ + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/usage_statistics_webtalk.xml b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..1207faa --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,787 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + +
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+
+
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+
+ + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
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+ + + + + + + + + + + + + + + + + + + + + + + + +
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
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+
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+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/vivado.jou b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/vivado.jou new file mode 100644 index 0000000..5bc87c2 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jun 30 17:34:30 2020 +# Process ID: 8920 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1 +# Command line: vivado.exe -log t160_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace +# Log file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/t160_top.vdi +# Journal file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source t160_top.tcl -notrace diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/vivado.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/vivado.pb new file mode 100644 index 0000000..5d59412 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/vivado.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/write_bitstream.pb b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..cf055e8 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/impl_1/write_bitstream.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.Vivado_Synthesis.queue.rst b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.Xil/t160_top_propImpl.xdc b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.Xil/t160_top_propImpl.xdc new file mode 100644 index 0000000..c7199f0 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.Xil/t160_top_propImpl.xdc @@ -0,0 +1,11 @@ +set_property SRC_FILE_INFO {cfile:D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc rfile:../../../../src/t160_top.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R17 [get_ports {led[0]}] +set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN T17 [get_ports {led[1]}] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U16 [get_ports {led[2]}] +set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U17 [get_ports {led[3]}] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN AA10 [get_ports sys_clkp] diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.ngc2edfcache/xjtag_axi_ngc_2e71882e.edif b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.ngc2edfcache/xjtag_axi_ngc_2e71882e.edif new file mode 100644 index 0000000..d9546bc --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.ngc2edfcache/xjtag_axi_ngc_2e71882e.edif @@ -0,0 +1,8841 @@ +(edif xjtag_axi + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2020 6 30 17 34 22) + (program "Xilinx ngc2edif" (version "P_INT.20180321")) + (author "Xilinx. Inc ") + (comment "This EDIF netlist is to be used within supported synthesis tools") + (comment "for determining resource/timing estimates of the design component") + (comment "represented by this netlist.") + (comment "Command line: -mdp2sp -w -secure xjtag_axi.ngc xjtag_axi.edif "))) + (external UNISIMS + (edifLevel 0) + (technology (numberDefinition)) + (cell GND + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell VCC + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port P + (direction OUTPUT) + ) + ) + ) + ) + (cell FDR + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDRE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell BSCAN_SPARTAN6 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port TDO + (direction INPUT) + ) + (port CAPTURE + (direction OUTPUT) + ) + (port DRCK + (direction OUTPUT) + ) + (port RESET + (direction OUTPUT) + ) + (port RUNTEST + (direction OUTPUT) + ) + (port SEL + (direction OUTPUT) + ) + (port SHIFT + (direction OUTPUT) + ) + (port TCK + (direction OUTPUT) + ) + (port TDI + (direction OUTPUT) + ) + (port TMS + (direction OUTPUT) + ) + (port UPDATE + (direction OUTPUT) + ) + ) + ) + ) + (cell XORCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port LI + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell FDE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT5 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT6 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port I5 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT1 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell FD + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell INV + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + ) + + (library xjtag_axi_lib + (edifLevel 0) + (technology (numberDefinition)) + (cell xjtag_axi + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port m00_axi_aclk + (direction INPUT) + ) + (port m00_axi_aresetn + (direction INPUT) + ) + (port m00_axi_awready + (direction INPUT) + ) + (port m00_axi_wready + (direction INPUT) + ) + (port m00_axi_bvalid + (direction INPUT) + ) + (port m00_axi_arready + (direction INPUT) + ) + (port m00_axi_rvalid + (direction INPUT) + ) + (port m00_axi_awvalid + (direction OUTPUT) + ) + (port m00_axi_wvalid + (direction OUTPUT) + ) + (port m00_axi_bready + (direction OUTPUT) + ) + (port m00_axi_arvalid + (direction OUTPUT) + ) + (port m00_axi_rready + (direction OUTPUT) + ) + (port (array (rename m00_axi_bresp "m00_axi_bresp<1:0>") 2) + (direction INPUT)) + (port (array (rename m00_axi_rdata "m00_axi_rdata<31:0>") 32) + (direction INPUT)) + (port (array (rename m00_axi_rresp "m00_axi_rresp<1:0>") 2) + (direction INPUT)) + (port (array (rename m00_axi_awaddr "m00_axi_awaddr<31:0>") 32) + (direction OUTPUT)) + (port (array (rename m00_axi_awprot "m00_axi_awprot<2:0>") 3) + (direction OUTPUT)) + (port (array (rename m00_axi_wdata "m00_axi_wdata<31:0>") 32) + (direction OUTPUT)) + (port (array (rename m00_axi_wstrb "m00_axi_wstrb<3:0>") 4) + (direction OUTPUT)) + (port (array (rename m00_axi_araddr "m00_axi_araddr<31:0>") 32) + (direction OUTPUT)) + (port (array (rename m00_axi_arprot "m00_axi_arprot<2:0>") 3) + (direction OUTPUT)) + (designator "xc7k70t-2-fbg676") + (property TYPE (string "xjtag_axi") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:m00_axi_bresp<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:INPUT:m00_axi_rdata<31:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:m00_axi_rresp<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:OUTPUT:m00_axi_awaddr<31:0>") (owner "Xilinx")) + (property BUS_INFO (string "3:OUTPUT:m00_axi_awprot<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:OUTPUT:m00_axi_wdata<31:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:m00_axi_wstrb<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:OUTPUT:m00_axi_araddr<31:0>") (owner "Xilinx")) + (property BUS_INFO (string "3:OUTPUT:m00_axi_arprot<2:0>") (owner "Xilinx")) + (property SHREG_MIN_SIZE (string "2") (owner "Xilinx")) + (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 0) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "xjtag_axi_xjtag_axi") (owner "Xilinx")) + ) + (contents + (instance XST_GND + (viewRef view_1 (cellRef GND (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance XST_VCC + (viewRef view_1 (cellRef VCC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd1_renamed_0 "xjtag_axi_v1_0_M00_AXI_inst/mst_exec_state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd2_renamed_1 "xjtag_axi_v1_0_M00_AXI_inst/mst_exec_state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff2_renamed_2 "xjtag_axi_v1_0_M00_AXI_inst/init_txn_ff2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff_renamed_3 "xjtag_axi_v1_0_M00_AXI_inst/init_txn_ff") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_finish_renamed_4 "xjtag_axi_v1_0_M00_AXI_inst/finish") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_iiread_req_renamed_5 "xjtag_axi_v1_0_M00_AXI_inst/iiread_req") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_write_req_d1_renamed_6 "xjtag_axi_v1_0_M00_AXI_inst/write_req_d1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_init_txn_pulse_renamed_7 "xjtag_axi_v1_0_M00_AXI_inst/init_txn_pulse") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_iread_req_renamed_8 "xjtag_axi_v1_0_M00_AXI_inst/iread_req") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_write_req_d0_renamed_9 "xjtag_axi_v1_0_M00_AXI_inst/write_req_d0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_31 "xjtag_axi_v1_0_M00_AXI_inst/read_data_31") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_30 "xjtag_axi_v1_0_M00_AXI_inst/read_data_30") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_29 "xjtag_axi_v1_0_M00_AXI_inst/read_data_29") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_28 "xjtag_axi_v1_0_M00_AXI_inst/read_data_28") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_27 "xjtag_axi_v1_0_M00_AXI_inst/read_data_27") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_26 "xjtag_axi_v1_0_M00_AXI_inst/read_data_26") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_25 "xjtag_axi_v1_0_M00_AXI_inst/read_data_25") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_24 "xjtag_axi_v1_0_M00_AXI_inst/read_data_24") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_23 "xjtag_axi_v1_0_M00_AXI_inst/read_data_23") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_22 "xjtag_axi_v1_0_M00_AXI_inst/read_data_22") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_21 "xjtag_axi_v1_0_M00_AXI_inst/read_data_21") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_20 "xjtag_axi_v1_0_M00_AXI_inst/read_data_20") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_19 "xjtag_axi_v1_0_M00_AXI_inst/read_data_19") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_18 "xjtag_axi_v1_0_M00_AXI_inst/read_data_18") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_17 "xjtag_axi_v1_0_M00_AXI_inst/read_data_17") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_16 "xjtag_axi_v1_0_M00_AXI_inst/read_data_16") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_15 "xjtag_axi_v1_0_M00_AXI_inst/read_data_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_14 "xjtag_axi_v1_0_M00_AXI_inst/read_data_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_13 "xjtag_axi_v1_0_M00_AXI_inst/read_data_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_12 "xjtag_axi_v1_0_M00_AXI_inst/read_data_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_11 "xjtag_axi_v1_0_M00_AXI_inst/read_data_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_10 "xjtag_axi_v1_0_M00_AXI_inst/read_data_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_9 "xjtag_axi_v1_0_M00_AXI_inst/read_data_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_8 "xjtag_axi_v1_0_M00_AXI_inst/read_data_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_7 "xjtag_axi_v1_0_M00_AXI_inst/read_data_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_6 "xjtag_axi_v1_0_M00_AXI_inst/read_data_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_5 "xjtag_axi_v1_0_M00_AXI_inst/read_data_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_4 "xjtag_axi_v1_0_M00_AXI_inst/read_data_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_3 "xjtag_axi_v1_0_M00_AXI_inst/read_data_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_2 "xjtag_axi_v1_0_M00_AXI_inst/read_data_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_1 "xjtag_axi_v1_0_M00_AXI_inst/read_data_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_0 "xjtag_axi_v1_0_M00_AXI_inst/read_data_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_31 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_31") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_30 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_30") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_29 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_29") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_28 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_28") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_27 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_27") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_26 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_26") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_25 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_25") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_24 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_24") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_23 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_23") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_22 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_22") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_21 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_21") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_20 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_20") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_19 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_19") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_18 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_18") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_17 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_17") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_16 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_16") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_15 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_15") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_14 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_14") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_13 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_13") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_12 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_12") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_11 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_11") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_10 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_10") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_9 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_9") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_8 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_8") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_7 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_7") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_6 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_6") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_5 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_5") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_4 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_4") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_3 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_3") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_2 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_1 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_0 "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata_0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_31 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_31") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_30 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_30") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_29 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_29") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_28 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_28") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_27 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_27") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_26 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_26") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_25 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_25") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_24 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_24") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_23 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_23") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_22 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_22") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_21 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_21") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_20 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_20") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_19 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_19") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_18 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_18") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_17 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_17") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_16 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_16") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_15 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_15") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_14 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_14") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_13 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_13") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_12 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_12") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_11 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_11") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_10 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_10") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_9 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_9") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_8 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_8") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_7 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_7") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_6 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_6") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_5 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_5") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_4 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_4") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_3 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_3") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_2 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_1 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_0 "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr_0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_31 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_31") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_30 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_30") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_29 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_29") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_28 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_28") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_27 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_27") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_26 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_26") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_25 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_25") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_24 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_24") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_23 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_23") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_22 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_22") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_21 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_21") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_20 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_20") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_19 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_19") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_18 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_18") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_17 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_17") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_16 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_16") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_15 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_15") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_14 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_14") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_13 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_13") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_12 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_12") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_11 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_11") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_10 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_10") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_9 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_9") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_8 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_8") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_7 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_7") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_6 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_6") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_5 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_5") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_4 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_4") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_3 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_3") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_2 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_1 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_0 "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr_0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_bscan_xjtag_uut_BSCAN_SPARTAN6_inst "xjtag_bus_uut/bscan_xjtag_uut/BSCAN_SPARTAN6_inst") + (viewRef view_1 (cellRef BSCAN_SPARTAN6 (libraryRef UNISIMS))) + (property JTAG_CHAIN (integer 3) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_xor_7__ "xjtag_bus_uut/Mcount_ishift_cnt_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_xor_6__ "xjtag_bus_uut/Mcount_ishift_cnt_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_6__ "xjtag_bus_uut/Mcount_ishift_cnt_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_xor_5__ "xjtag_bus_uut/Mcount_ishift_cnt_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_5__ "xjtag_bus_uut/Mcount_ishift_cnt_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_xor_4__ "xjtag_bus_uut/Mcount_ishift_cnt_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_4__ "xjtag_bus_uut/Mcount_ishift_cnt_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_xor_3__ "xjtag_bus_uut/Mcount_ishift_cnt_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_3__ "xjtag_bus_uut/Mcount_ishift_cnt_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_xor_2__ "xjtag_bus_uut/Mcount_ishift_cnt_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_2__ "xjtag_bus_uut/Mcount_ishift_cnt_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_xor_1__ "xjtag_bus_uut/Mcount_ishift_cnt_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_1__ "xjtag_bus_uut/Mcount_ishift_cnt_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_xor_0__ "xjtag_bus_uut/Mcount_ishift_cnt_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_0__ "xjtag_bus_uut/Mcount_ishift_cnt_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ishift_cnt_0 "xjtag_bus_uut/ishift_cnt_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ishift_cnt_7 "xjtag_bus_uut/ishift_cnt_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ishift_cnt_6 "xjtag_bus_uut/ishift_cnt_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ishift_cnt_5 "xjtag_bus_uut/ishift_cnt_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ishift_cnt_4 "xjtag_bus_uut/ishift_cnt_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ishift_cnt_3 "xjtag_bus_uut/ishift_cnt_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ishift_cnt_2 "xjtag_bus_uut/ishift_cnt_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ishift_cnt_1 "xjtag_bus_uut/ishift_cnt_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_chip_r_2 "xjtag_bus_uut/chip_r_2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_chip_r_1 "xjtag_bus_uut/chip_r_1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_chip_r_0 "xjtag_bus_uut/chip_r_0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_dop_clk_r_3 "xjtag_bus_uut/dop_clk_r_3") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_dop_clk_r_2 "xjtag_bus_uut/dop_clk_r_2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_dop_clk_r_1 "xjtag_bus_uut/dop_clk_r_1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_dop_clk_r_0 "xjtag_bus_uut/dop_clk_r_0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_dop1949_r_1 "xjtag_bus_uut/dop1949_r_1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_dop1949_r_0 "xjtag_bus_uut/dop1949_r_0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_33 "xjtag_bus_uut/oshift_33") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_32 "xjtag_bus_uut/oshift_32") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_31 "xjtag_bus_uut/oshift_31") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_30 "xjtag_bus_uut/oshift_30") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_29 "xjtag_bus_uut/oshift_29") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_28 "xjtag_bus_uut/oshift_28") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_27 "xjtag_bus_uut/oshift_27") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_26 "xjtag_bus_uut/oshift_26") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_25 "xjtag_bus_uut/oshift_25") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_24 "xjtag_bus_uut/oshift_24") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_23 "xjtag_bus_uut/oshift_23") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_22 "xjtag_bus_uut/oshift_22") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_21 "xjtag_bus_uut/oshift_21") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_20 "xjtag_bus_uut/oshift_20") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_19 "xjtag_bus_uut/oshift_19") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_18 "xjtag_bus_uut/oshift_18") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_17 "xjtag_bus_uut/oshift_17") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_16 "xjtag_bus_uut/oshift_16") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_15 "xjtag_bus_uut/oshift_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_14 "xjtag_bus_uut/oshift_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_13 "xjtag_bus_uut/oshift_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_12 "xjtag_bus_uut/oshift_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_11 "xjtag_bus_uut/oshift_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_10 "xjtag_bus_uut/oshift_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_9 "xjtag_bus_uut/oshift_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_8 "xjtag_bus_uut/oshift_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_7 "xjtag_bus_uut/oshift_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_6 "xjtag_bus_uut/oshift_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_5 "xjtag_bus_uut/oshift_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_4 "xjtag_bus_uut/oshift_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_3 "xjtag_bus_uut/oshift_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_2 "xjtag_bus_uut/oshift_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_1 "xjtag_bus_uut/oshift_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_oshift_0 "xjtag_bus_uut/oshift_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_31 "xjtag_bus_uut/axi_waddr_31") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_30 "xjtag_bus_uut/axi_waddr_30") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_29 "xjtag_bus_uut/axi_waddr_29") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_28 "xjtag_bus_uut/axi_waddr_28") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_27 "xjtag_bus_uut/axi_waddr_27") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_26 "xjtag_bus_uut/axi_waddr_26") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_25 "xjtag_bus_uut/axi_waddr_25") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_24 "xjtag_bus_uut/axi_waddr_24") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_23 "xjtag_bus_uut/axi_waddr_23") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_22 "xjtag_bus_uut/axi_waddr_22") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_21 "xjtag_bus_uut/axi_waddr_21") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_20 "xjtag_bus_uut/axi_waddr_20") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_19 "xjtag_bus_uut/axi_waddr_19") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_18 "xjtag_bus_uut/axi_waddr_18") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_17 "xjtag_bus_uut/axi_waddr_17") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_16 "xjtag_bus_uut/axi_waddr_16") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_15 "xjtag_bus_uut/axi_waddr_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_14 "xjtag_bus_uut/axi_waddr_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_13 "xjtag_bus_uut/axi_waddr_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_12 "xjtag_bus_uut/axi_waddr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_11 "xjtag_bus_uut/axi_waddr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_10 "xjtag_bus_uut/axi_waddr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_9 "xjtag_bus_uut/axi_waddr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_8 "xjtag_bus_uut/axi_waddr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_7 "xjtag_bus_uut/axi_waddr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_6 "xjtag_bus_uut/axi_waddr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_5 "xjtag_bus_uut/axi_waddr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_4 "xjtag_bus_uut/axi_waddr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_3 "xjtag_bus_uut/axi_waddr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_2 "xjtag_bus_uut/axi_waddr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_1 "xjtag_bus_uut/axi_waddr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_waddr_0 "xjtag_bus_uut/axi_waddr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_31 "xjtag_bus_uut/axi_raddr_31") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_30 "xjtag_bus_uut/axi_raddr_30") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_29 "xjtag_bus_uut/axi_raddr_29") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_28 "xjtag_bus_uut/axi_raddr_28") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_27 "xjtag_bus_uut/axi_raddr_27") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_26 "xjtag_bus_uut/axi_raddr_26") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_25 "xjtag_bus_uut/axi_raddr_25") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_24 "xjtag_bus_uut/axi_raddr_24") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_23 "xjtag_bus_uut/axi_raddr_23") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_22 "xjtag_bus_uut/axi_raddr_22") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_21 "xjtag_bus_uut/axi_raddr_21") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_20 "xjtag_bus_uut/axi_raddr_20") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_19 "xjtag_bus_uut/axi_raddr_19") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_18 "xjtag_bus_uut/axi_raddr_18") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_17 "xjtag_bus_uut/axi_raddr_17") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_16 "xjtag_bus_uut/axi_raddr_16") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_15 "xjtag_bus_uut/axi_raddr_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_14 "xjtag_bus_uut/axi_raddr_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_13 "xjtag_bus_uut/axi_raddr_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_12 "xjtag_bus_uut/axi_raddr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_11 "xjtag_bus_uut/axi_raddr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_10 "xjtag_bus_uut/axi_raddr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_9 "xjtag_bus_uut/axi_raddr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_8 "xjtag_bus_uut/axi_raddr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_7 "xjtag_bus_uut/axi_raddr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_6 "xjtag_bus_uut/axi_raddr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_5 "xjtag_bus_uut/axi_raddr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_4 "xjtag_bus_uut/axi_raddr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_3 "xjtag_bus_uut/axi_raddr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_2 "xjtag_bus_uut/axi_raddr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_1 "xjtag_bus_uut/axi_raddr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_raddr_0 "xjtag_bus_uut/axi_raddr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_31 "xjtag_bus_uut/axi_wdata_31") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_30 "xjtag_bus_uut/axi_wdata_30") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_29 "xjtag_bus_uut/axi_wdata_29") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_28 "xjtag_bus_uut/axi_wdata_28") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_27 "xjtag_bus_uut/axi_wdata_27") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_26 "xjtag_bus_uut/axi_wdata_26") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_25 "xjtag_bus_uut/axi_wdata_25") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_24 "xjtag_bus_uut/axi_wdata_24") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_23 "xjtag_bus_uut/axi_wdata_23") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_22 "xjtag_bus_uut/axi_wdata_22") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_21 "xjtag_bus_uut/axi_wdata_21") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_20 "xjtag_bus_uut/axi_wdata_20") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_19 "xjtag_bus_uut/axi_wdata_19") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_18 "xjtag_bus_uut/axi_wdata_18") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_17 "xjtag_bus_uut/axi_wdata_17") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_16 "xjtag_bus_uut/axi_wdata_16") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_15 "xjtag_bus_uut/axi_wdata_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_14 "xjtag_bus_uut/axi_wdata_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_13 "xjtag_bus_uut/axi_wdata_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_12 "xjtag_bus_uut/axi_wdata_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_11 "xjtag_bus_uut/axi_wdata_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_10 "xjtag_bus_uut/axi_wdata_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_9 "xjtag_bus_uut/axi_wdata_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_8 "xjtag_bus_uut/axi_wdata_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_7 "xjtag_bus_uut/axi_wdata_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_6 "xjtag_bus_uut/axi_wdata_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_5 "xjtag_bus_uut/axi_wdata_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_4 "xjtag_bus_uut/axi_wdata_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_3 "xjtag_bus_uut/axi_wdata_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_2 "xjtag_bus_uut/axi_wdata_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_1 "xjtag_bus_uut/axi_wdata_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wdata_0 "xjtag_bus_uut/axi_wdata_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wmask_3 "xjtag_bus_uut/axi_wmask_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wmask_2 "xjtag_bus_uut/axi_wmask_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wmask_1 "xjtag_bus_uut/axi_wmask_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wmask_0 "xjtag_bus_uut/axi_wmask_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_31 "xjtag_bus_uut/addr_31") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_30 "xjtag_bus_uut/addr_30") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_29 "xjtag_bus_uut/addr_29") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_28 "xjtag_bus_uut/addr_28") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_27 "xjtag_bus_uut/addr_27") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_26 "xjtag_bus_uut/addr_26") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_25 "xjtag_bus_uut/addr_25") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_24 "xjtag_bus_uut/addr_24") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_23 "xjtag_bus_uut/addr_23") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_22 "xjtag_bus_uut/addr_22") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_21 "xjtag_bus_uut/addr_21") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_20 "xjtag_bus_uut/addr_20") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_19 "xjtag_bus_uut/addr_19") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_18 "xjtag_bus_uut/addr_18") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_17 "xjtag_bus_uut/addr_17") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_16 "xjtag_bus_uut/addr_16") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_15 "xjtag_bus_uut/addr_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_14 "xjtag_bus_uut/addr_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_13 "xjtag_bus_uut/addr_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_12 "xjtag_bus_uut/addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_11 "xjtag_bus_uut/addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_10 "xjtag_bus_uut/addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_9 "xjtag_bus_uut/addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_8 "xjtag_bus_uut/addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_7 "xjtag_bus_uut/addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_6 "xjtag_bus_uut/addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_5 "xjtag_bus_uut/addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_4 "xjtag_bus_uut/addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_3 "xjtag_bus_uut/addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_2 "xjtag_bus_uut/addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_1 "xjtag_bus_uut/addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_addr_0 "xjtag_bus_uut/addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_31 "xjtag_bus_uut/icrab_data_31") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_30 "xjtag_bus_uut/icrab_data_30") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_29 "xjtag_bus_uut/icrab_data_29") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_28 "xjtag_bus_uut/icrab_data_28") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_27 "xjtag_bus_uut/icrab_data_27") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_26 "xjtag_bus_uut/icrab_data_26") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_25 "xjtag_bus_uut/icrab_data_25") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_24 "xjtag_bus_uut/icrab_data_24") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_23 "xjtag_bus_uut/icrab_data_23") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_22 "xjtag_bus_uut/icrab_data_22") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_21 "xjtag_bus_uut/icrab_data_21") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_20 "xjtag_bus_uut/icrab_data_20") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_19 "xjtag_bus_uut/icrab_data_19") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_18 "xjtag_bus_uut/icrab_data_18") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_17 "xjtag_bus_uut/icrab_data_17") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_16 "xjtag_bus_uut/icrab_data_16") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_15 "xjtag_bus_uut/icrab_data_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_14 "xjtag_bus_uut/icrab_data_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_13 "xjtag_bus_uut/icrab_data_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_12 "xjtag_bus_uut/icrab_data_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_11 "xjtag_bus_uut/icrab_data_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_10 "xjtag_bus_uut/icrab_data_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_9 "xjtag_bus_uut/icrab_data_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_8 "xjtag_bus_uut/icrab_data_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_7 "xjtag_bus_uut/icrab_data_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_6 "xjtag_bus_uut/icrab_data_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_5 "xjtag_bus_uut/icrab_data_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_4 "xjtag_bus_uut/icrab_data_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_3 "xjtag_bus_uut/icrab_data_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_2 "xjtag_bus_uut/icrab_data_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_1 "xjtag_bus_uut/icrab_data_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icrab_data_0 "xjtag_bus_uut/icrab_data_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_cmd_7 "xjtag_bus_uut/cmd_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_cmd_6 "xjtag_bus_uut/cmd_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_cmd_5 "xjtag_bus_uut/cmd_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_cmd_4 "xjtag_bus_uut/cmd_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_cmd_3 "xjtag_bus_uut/cmd_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_cmd_2 "xjtag_bus_uut/cmd_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_cmd_1 "xjtag_bus_uut/cmd_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_cmd_0 "xjtag_bus_uut/cmd_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icmd_rd_1 "xjtag_bus_uut/icmd_rd_1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_icmd_rd_0 "xjtag_bus_uut/icmd_rd_0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_31 "xjtag_bus_uut/wdata_31") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_30 "xjtag_bus_uut/wdata_30") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_29 "xjtag_bus_uut/wdata_29") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_28 "xjtag_bus_uut/wdata_28") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_27 "xjtag_bus_uut/wdata_27") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_26 "xjtag_bus_uut/wdata_26") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_25 "xjtag_bus_uut/wdata_25") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_24 "xjtag_bus_uut/wdata_24") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_23 "xjtag_bus_uut/wdata_23") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_22 "xjtag_bus_uut/wdata_22") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_21 "xjtag_bus_uut/wdata_21") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_20 "xjtag_bus_uut/wdata_20") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_19 "xjtag_bus_uut/wdata_19") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_18 "xjtag_bus_uut/wdata_18") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_17 "xjtag_bus_uut/wdata_17") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_16 "xjtag_bus_uut/wdata_16") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_15 "xjtag_bus_uut/wdata_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_14 "xjtag_bus_uut/wdata_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_13 "xjtag_bus_uut/wdata_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_12 "xjtag_bus_uut/wdata_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_11 "xjtag_bus_uut/wdata_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_10 "xjtag_bus_uut/wdata_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_9 "xjtag_bus_uut/wdata_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_8 "xjtag_bus_uut/wdata_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_7 "xjtag_bus_uut/wdata_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_6 "xjtag_bus_uut/wdata_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_5 "xjtag_bus_uut/wdata_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_4 "xjtag_bus_uut/wdata_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_3 "xjtag_bus_uut/wdata_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_2 "xjtag_bus_uut/wdata_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_wdata_1 "xjtag_bus_uut/wdata_1") + (viewRef view_1 (cellRef FDRE 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"xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_2_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___44___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_2_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_3_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_3_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___43___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_3_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_4_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_4_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___42___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_4_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_5_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_5_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___41___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_5_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_6_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_6_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___40___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_6_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_7_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_7_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___39___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_7_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_8_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_8_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___38___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_8_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_9_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_9_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___37___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_9_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_10_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_10_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___36___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_10_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_11_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_11_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___35___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_11_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_12_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_12_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___34___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_12_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_13_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_13_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___33___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_13_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_14_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_14_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___32___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_14_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_15_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_15_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___31___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_15_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_16_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_16_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___30___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_16_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_17_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_17_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___29___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_17_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_18_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_18_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___28___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_18_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_19_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_19_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___27___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_19_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_20_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_20_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___26___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_20_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_21_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_21_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___25___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_21_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_22_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_22_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___24___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_22_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_23_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_23_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___23___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_23_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_24_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_24_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___22___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_24_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_25_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_25_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___21___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_25_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_26_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_26_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___20___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_26_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_27_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_27_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___19___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_27_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_28_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_28_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___18___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_28_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_29_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_29_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___17___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_29_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_30_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_30_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___16___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_30_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_31_xo_0_1 "xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_31_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___15___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_31_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_0_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_0_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_1_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_1_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_2_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_2_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_3_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_3_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_4_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_4_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_5_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_5_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_6_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_6_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_7_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_7_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_8_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_8_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_9_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_9_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_10_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_10_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_11_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_11_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_12_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_12_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_13_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_13_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_14_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_14_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_15_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_15_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_16_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_16_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_17_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_17_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_18_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_18_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_19_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_19_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_20_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_20_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_21_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_21_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_22_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_22_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_23_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_23_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_24_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_24_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_25_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_25_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_26_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_26_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_27_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_27_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_28_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_28_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_29_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_29_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_30_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_30_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_31_xo_0_1 "xjtag_bus_uut/Mxor_wdata[31]_icrab_data[31]_xor_42_OUT_31_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_0_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_0_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___14___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_0_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_1_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_1_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___13___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_1_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_2_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_2_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___44___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_2_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_3_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_3_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___43___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_3_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_4_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_4_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___42___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_4_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_5_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_5_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___41___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_5_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_6_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_6_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___40___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_6_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_7_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_7_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___39___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_7_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_8_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_8_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___38___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_8_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_9_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_9_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___37___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_9_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_10_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_10_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___36___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_10_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_11_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_11_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___35___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_11_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_12_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_12_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___34___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_12_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_13_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_13_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___33___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_13_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_14_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_14_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___32___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_14_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_15_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_15_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___31___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_15_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_16_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_16_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___30___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_16_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_17_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_17_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___29___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_17_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_18_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_18_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___28___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_18_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_19_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_19_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___27___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_19_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_20_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_20_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___26___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_20_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_21_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_21_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___25___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_21_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_22_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_22_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___24___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_22_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_23_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_23_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___23___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_23_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_24_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_24_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___22___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_24_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_25_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_25_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___21___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_25_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_26_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_26_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___20___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_26_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_27_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_27_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___19___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_27_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_28_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_28_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___18___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_28_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_29_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_29_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___17___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_29_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_30_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_30_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___16___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_30_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_31_xo_0_1 "xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_72_OUT_31_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___15___xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_39_OUT_31_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_bscan_xjtag_uut_DOP19491 "xjtag_bus_uut/bscan_xjtag_uut/DOP19491") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___46___xjtag_bus_uut/bscan_xjtag_uut/DOP19491") (owner "Xilinx")) + (property INIT (string "8") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_bscan_xjtag_uut_CLK1 "xjtag_bus_uut/bscan_xjtag_uut/CLK1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___46___xjtag_bus_uut/bscan_xjtag_uut/DOP19491") (owner "Xilinx")) + (property INIT (string "8") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_bscan_xjtag_uut_Mmux_CS11 "xjtag_bus_uut/bscan_xjtag_uut/Mmux_CS11") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___47___xjtag_bus_uut/bscan_xjtag_uut/Mmux_CS11") (owner "Xilinx")) + (property INIT (string "B") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut__n0207_inv1 "xjtag_bus_uut/_n0207_inv1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___3___xjtag_bus_uut/_n0207_inv1") (owner "Xilinx")) + (property INIT (string "20") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut__n0216_inv1 "xjtag_bus_uut/_n0216_inv1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___2___xjtag_bus_uut/_n0211_inv1") (owner "Xilinx")) + (property INIT (string "10") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ishift_data_71__PWR_2_o_equal_69_o_31_1 "xjtag_bus_uut/ishift_data[71]_PWR_2_o_equal_69_o<31>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___8___xjtag_bus_uut/ishift_data[71]_PWR_2_o_equal_69_o<31>1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_dop_clk_r_2__dop_clk_r_1__AND_3_o1 "xjtag_bus_uut/dop_clk_r[2]_dop_clk_r[1]_AND_3_o1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___4___xjtag_bus_uut/dop_clk_r[2]_dop_clk_r[1]_AND_3_o1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ird_valid_icmd_rd_1__AND_11_o1 "xjtag_bus_uut/ird_valid_icmd_rd[1]_AND_11_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___47___xjtag_bus_uut/bscan_xjtag_uut/Mmux_CS11") (owner "Xilinx")) + (property INIT (string "20") (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst__n0284_SW0 "xjtag_axi_v1_0_M00_AXI_inst/_n0284_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___12___xjtag_axi_v1_0_M00_AXI_inst/_n0284_SW0") (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst__n0284_renamed_10 "xjtag_axi_v1_0_M00_AXI_inst/_n0284") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000002") (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst__n0276_SW0 "xjtag_axi_v1_0_M00_AXI_inst/_n0276_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___1___xjtag_axi_v1_0_M00_AXI_inst/_n0276_SW0") (owner "Xilinx")) + (property INIT (string "FFFE") (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst__n0276_renamed_11 "xjtag_axi_v1_0_M00_AXI_inst/_n0276") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000002") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_SW0 "xjtag_bus_uut/dop_clk_r[2]_GND_2_o_AND_15_o_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00011111") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_renamed_12 "xjtag_bus_uut/dop_clk_r[2]_GND_2_o_AND_15_o") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2220222022222220") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_SW0 "xjtag_bus_uut/chip_r[1]_ishift_cnt[7]_AND_9_o1_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_renamed_13 "xjtag_bus_uut/chip_r[1]_ishift_cnt[7]_AND_9_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000008") (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_arvalid_renamed_14 "xjtag_axi_v1_0_M00_AXI_inst/axi_arvalid") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wvalid_renamed_15 "xjtag_axi_v1_0_M00_AXI_inst/axi_wvalid") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awvalid_renamed_16 "xjtag_axi_v1_0_M00_AXI_inst/axi_awvalid") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_issued_renamed_17 "xjtag_axi_v1_0_M00_AXI_inst/read_issued") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_write_issued_renamed_18 "xjtag_axi_v1_0_M00_AXI_inst/write_issued") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_start_single_write_renamed_19 "xjtag_axi_v1_0_M00_AXI_inst/start_single_write") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_start_single_read_renamed_20 "xjtag_axi_v1_0_M00_AXI_inst/start_single_read") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_rready_renamed_21 "xjtag_axi_v1_0_M00_AXI_inst/axi_rready") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_axi_bready_renamed_22 "xjtag_axi_v1_0_M00_AXI_inst/axi_bready") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_ifinish_renamed_23 "xjtag_axi_v1_0_M00_AXI_inst/ifinish") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_iwr_rd_renamed_24 "xjtag_axi_v1_0_M00_AXI_inst/iwr_rd") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_reads_done_renamed_25 "xjtag_axi_v1_0_M00_AXI_inst/reads_done") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_last_read_renamed_26 "xjtag_axi_v1_0_M00_AXI_inst/last_read") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_writes_done_renamed_27 "xjtag_axi_v1_0_M00_AXI_inst/writes_done") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_last_write_renamed_28 "xjtag_axi_v1_0_M00_AXI_inst/last_write") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_6__rt_renamed_29 "xjtag_bus_uut/Mcount_ishift_cnt_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_5__rt_renamed_30 "xjtag_bus_uut/Mcount_ishift_cnt_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_4__rt_renamed_31 "xjtag_bus_uut/Mcount_ishift_cnt_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_3__rt_renamed_32 "xjtag_bus_uut/Mcount_ishift_cnt_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_2__rt_renamed_33 "xjtag_bus_uut/Mcount_ishift_cnt_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_1__rt_renamed_34 "xjtag_bus_uut/Mcount_ishift_cnt_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_Mcount_ishift_cnt_xor_7__rt_renamed_35 "xjtag_bus_uut/Mcount_ishift_cnt_xor<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_write_index_0_renamed_36 "xjtag_axi_v1_0_M00_AXI_inst/write_index_0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_axi_v1_0_M00_AXI_inst_read_index_0_renamed_37 "xjtag_axi_v1_0_M00_AXI_inst/read_index_0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_iwr_valid_renamed_38 "xjtag_bus_uut/iwr_valid") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ird_valid_renamed_39 "xjtag_bus_uut/ird_valid") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_rvalid_renamed_40 "xjtag_bus_uut/axi_rvalid") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_axi_wvalid_renamed_41 "xjtag_bus_uut/axi_wvalid") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o1_SW0 "xjtag_bus_uut/dop_clk_r[2]_ishift_cnt[7]_AND_13_o1_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut__n0231_inv1 "xjtag_bus_uut/_n0231_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FBFFFFFF00040000") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_ird_valid_rstpot_renamed_42 "xjtag_bus_uut/ird_valid_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000020000000000") (owner "Xilinx")) + ) + (instance (rename xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_SW1 "xjtag_bus_uut/chip_r[1]_ishift_cnt[7]_AND_9_o1_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB 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) + (net (rename m00_axi_rdata_20_ "m00_axi_rdata<20>") + (joined + (portRef (member m00_axi_rdata 11)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_20)) + ) + ) + (net (rename m00_axi_rdata_19_ "m00_axi_rdata<19>") + (joined + (portRef (member m00_axi_rdata 12)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_19)) + ) + ) + (net (rename m00_axi_rdata_18_ "m00_axi_rdata<18>") + (joined + (portRef (member m00_axi_rdata 13)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_18)) + ) + ) + (net (rename m00_axi_rdata_17_ "m00_axi_rdata<17>") + (joined + (portRef (member m00_axi_rdata 14)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_17)) + ) + ) + (net (rename m00_axi_rdata_16_ "m00_axi_rdata<16>") + (joined + (portRef (member m00_axi_rdata 15)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_16)) + ) + ) + (net (rename m00_axi_rdata_15_ "m00_axi_rdata<15>") + (joined + (portRef (member m00_axi_rdata 16)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_15)) + ) + ) + (net (rename m00_axi_rdata_14_ "m00_axi_rdata<14>") + (joined + (portRef (member m00_axi_rdata 17)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_14)) + ) + ) + (net (rename m00_axi_rdata_13_ "m00_axi_rdata<13>") + (joined + (portRef (member m00_axi_rdata 18)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_13)) + ) + ) + (net (rename m00_axi_rdata_12_ "m00_axi_rdata<12>") + (joined + (portRef (member m00_axi_rdata 19)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_12)) + ) + ) + (net (rename m00_axi_rdata_11_ "m00_axi_rdata<11>") + (joined + (portRef (member m00_axi_rdata 20)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_11)) + ) + ) + (net (rename m00_axi_rdata_10_ "m00_axi_rdata<10>") + (joined + (portRef (member m00_axi_rdata 21)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_10)) + ) + ) + (net (rename m00_axi_rdata_9_ "m00_axi_rdata<9>") + (joined + (portRef (member m00_axi_rdata 22)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_9)) + ) + ) + (net (rename m00_axi_rdata_8_ "m00_axi_rdata<8>") + (joined + (portRef (member m00_axi_rdata 23)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_8)) + ) + ) + (net (rename m00_axi_rdata_7_ "m00_axi_rdata<7>") + (joined + (portRef (member m00_axi_rdata 24)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_7)) + ) + ) + (net (rename m00_axi_rdata_6_ "m00_axi_rdata<6>") + (joined + (portRef (member m00_axi_rdata 25)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_6)) + ) + ) + (net (rename m00_axi_rdata_5_ "m00_axi_rdata<5>") + (joined + (portRef (member m00_axi_rdata 26)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_5)) + ) + ) + (net (rename m00_axi_rdata_4_ "m00_axi_rdata<4>") + (joined + (portRef (member m00_axi_rdata 27)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_4)) + ) + ) + (net (rename m00_axi_rdata_3_ "m00_axi_rdata<3>") + (joined + (portRef (member m00_axi_rdata 28)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_3)) + ) + ) + (net (rename m00_axi_rdata_2_ "m00_axi_rdata<2>") + (joined + (portRef (member m00_axi_rdata 29)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_2)) + ) + ) + (net (rename m00_axi_rdata_1_ "m00_axi_rdata<1>") + (joined + (portRef (member m00_axi_rdata 30)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_1)) + ) + ) + (net (rename m00_axi_rdata_0_ "m00_axi_rdata<0>") + (joined + (portRef (member m00_axi_rdata 31)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_0)) + ) + ) + (net m00_axi_aclk + (joined + (portRef m00_axi_aclk) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_0)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_1)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_2)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_3)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_4)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_5)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_6)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_7)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_8)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_9)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_10)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_11)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_12)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_13)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_14)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_15)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_16)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_17)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_18)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_19)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_20)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_21)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_22)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_23)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_24)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_25)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_26)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_27)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_28)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_29)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_30)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_31)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_0)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_1)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_2)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_3)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_4)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_5)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_6)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_7)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_8)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_9)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_10)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_11)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_12)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_13)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_14)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_15)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_16)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_17)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_18)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_19)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_20)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_21)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_22)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_23)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_24)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_25)) + (portRef C (instanceRef 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(instanceRef xjtag_bus_uut_wdata_4)) + (portRef C (instanceRef xjtag_bus_uut_wdata_5)) + (portRef C (instanceRef xjtag_bus_uut_wdata_6)) + (portRef C (instanceRef xjtag_bus_uut_wdata_7)) + (portRef C (instanceRef xjtag_bus_uut_wdata_8)) + (portRef C (instanceRef xjtag_bus_uut_wdata_9)) + (portRef C (instanceRef xjtag_bus_uut_wdata_10)) + (portRef C (instanceRef xjtag_bus_uut_wdata_11)) + (portRef C (instanceRef xjtag_bus_uut_wdata_12)) + (portRef C (instanceRef xjtag_bus_uut_wdata_13)) + (portRef C (instanceRef xjtag_bus_uut_wdata_14)) + (portRef C (instanceRef xjtag_bus_uut_wdata_15)) + (portRef C (instanceRef xjtag_bus_uut_wdata_16)) + (portRef C (instanceRef xjtag_bus_uut_wdata_17)) + (portRef C (instanceRef xjtag_bus_uut_wdata_18)) + (portRef C (instanceRef xjtag_bus_uut_wdata_19)) + (portRef C (instanceRef xjtag_bus_uut_wdata_20)) + (portRef C (instanceRef xjtag_bus_uut_wdata_21)) + (portRef C (instanceRef xjtag_bus_uut_wdata_22)) + (portRef C (instanceRef xjtag_bus_uut_wdata_23)) + (portRef C (instanceRef xjtag_bus_uut_wdata_24)) + (portRef C (instanceRef xjtag_bus_uut_wdata_25)) + (portRef C (instanceRef xjtag_bus_uut_wdata_26)) + (portRef C (instanceRef xjtag_bus_uut_wdata_27)) + (portRef C (instanceRef xjtag_bus_uut_wdata_28)) + (portRef C (instanceRef xjtag_bus_uut_wdata_29)) + (portRef C (instanceRef xjtag_bus_uut_wdata_30)) + (portRef C (instanceRef xjtag_bus_uut_wdata_31)) + (portRef C (instanceRef xjtag_bus_uut_icmd_rd_0)) + (portRef C (instanceRef xjtag_bus_uut_icmd_rd_1)) + (portRef C (instanceRef xjtag_bus_uut_cmd_0)) + (portRef C (instanceRef xjtag_bus_uut_cmd_1)) + (portRef C (instanceRef xjtag_bus_uut_cmd_2)) + (portRef C (instanceRef xjtag_bus_uut_cmd_3)) + (portRef C (instanceRef xjtag_bus_uut_cmd_4)) + (portRef C (instanceRef xjtag_bus_uut_cmd_5)) + (portRef C (instanceRef xjtag_bus_uut_cmd_6)) + (portRef C (instanceRef xjtag_bus_uut_cmd_7)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_0)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_1)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_2)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_3)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_4)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_5)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_6)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_7)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_8)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_9)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_10)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_11)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_12)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_13)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_14)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_15)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_16)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_17)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_18)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_19)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_20)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_21)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_22)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_23)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_24)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_25)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_26)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_27)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_28)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_29)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_30)) + (portRef C (instanceRef xjtag_bus_uut_icrab_data_31)) + (portRef C (instanceRef xjtag_bus_uut_addr_0)) + (portRef C (instanceRef xjtag_bus_uut_addr_1)) + (portRef C (instanceRef xjtag_bus_uut_addr_2)) + (portRef C (instanceRef xjtag_bus_uut_addr_3)) + (portRef C (instanceRef xjtag_bus_uut_addr_4)) + (portRef C (instanceRef xjtag_bus_uut_addr_5)) + (portRef C (instanceRef xjtag_bus_uut_addr_6)) + (portRef C (instanceRef xjtag_bus_uut_addr_7)) + (portRef C (instanceRef xjtag_bus_uut_addr_8)) + (portRef C (instanceRef xjtag_bus_uut_addr_9)) + (portRef C (instanceRef xjtag_bus_uut_addr_10)) + (portRef C (instanceRef xjtag_bus_uut_addr_11)) + (portRef C (instanceRef xjtag_bus_uut_addr_12)) + (portRef C (instanceRef xjtag_bus_uut_addr_13)) + (portRef C (instanceRef xjtag_bus_uut_addr_14)) + (portRef C (instanceRef xjtag_bus_uut_addr_15)) + (portRef C (instanceRef xjtag_bus_uut_addr_16)) + (portRef C (instanceRef xjtag_bus_uut_addr_17)) + (portRef C (instanceRef xjtag_bus_uut_addr_18)) + (portRef C (instanceRef xjtag_bus_uut_addr_19)) + (portRef C (instanceRef xjtag_bus_uut_addr_20)) + (portRef C (instanceRef xjtag_bus_uut_addr_21)) + (portRef C (instanceRef xjtag_bus_uut_addr_22)) + (portRef C (instanceRef xjtag_bus_uut_addr_23)) + (portRef C (instanceRef xjtag_bus_uut_addr_24)) + (portRef C (instanceRef xjtag_bus_uut_addr_25)) + (portRef C (instanceRef xjtag_bus_uut_addr_26)) + (portRef C (instanceRef xjtag_bus_uut_addr_27)) + (portRef C (instanceRef xjtag_bus_uut_addr_28)) + (portRef C (instanceRef xjtag_bus_uut_addr_29)) + (portRef C (instanceRef xjtag_bus_uut_addr_30)) + (portRef C (instanceRef xjtag_bus_uut_addr_31)) + (portRef C (instanceRef xjtag_bus_uut_axi_wmask_0)) + (portRef C (instanceRef xjtag_bus_uut_axi_wmask_1)) + (portRef C (instanceRef xjtag_bus_uut_axi_wmask_2)) + (portRef C (instanceRef xjtag_bus_uut_axi_wmask_3)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_0)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_1)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_2)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_3)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_4)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_5)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_6)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_7)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_8)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_9)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_10)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_11)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_12)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_13)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_14)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_15)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_16)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_17)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_18)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_19)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_20)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_21)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_22)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_23)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_24)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_25)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_26)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_27)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_28)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_29)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_30)) + (portRef C (instanceRef xjtag_bus_uut_axi_wdata_31)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_0)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_1)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_2)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_3)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_4)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_5)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_6)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_7)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_8)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_9)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_10)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_11)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_12)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_13)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_14)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_15)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_16)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_17)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_18)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_19)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_20)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_21)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_22)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_23)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_24)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_25)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_26)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_27)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_28)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_29)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_30)) + (portRef C (instanceRef xjtag_bus_uut_axi_raddr_31)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_0)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_1)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_2)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_3)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_4)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_5)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_6)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_7)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_8)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_9)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_10)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_11)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_12)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_13)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_14)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_15)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_16)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_17)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_18)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_19)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_20)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_21)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_22)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_23)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_24)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_25)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_26)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_27)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_28)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_29)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_30)) + (portRef C (instanceRef xjtag_bus_uut_axi_waddr_31)) + (portRef C (instanceRef xjtag_bus_uut_oshift_0)) + (portRef C (instanceRef xjtag_bus_uut_oshift_1)) + (portRef C (instanceRef xjtag_bus_uut_oshift_2)) + (portRef C (instanceRef xjtag_bus_uut_oshift_3)) + (portRef C (instanceRef xjtag_bus_uut_oshift_4)) + (portRef C (instanceRef xjtag_bus_uut_oshift_5)) + (portRef C (instanceRef xjtag_bus_uut_oshift_6)) + (portRef C (instanceRef xjtag_bus_uut_oshift_7)) + (portRef C (instanceRef xjtag_bus_uut_oshift_8)) + (portRef C (instanceRef xjtag_bus_uut_oshift_9)) + (portRef C (instanceRef xjtag_bus_uut_oshift_10)) + (portRef C (instanceRef xjtag_bus_uut_oshift_11)) + (portRef C (instanceRef xjtag_bus_uut_oshift_12)) + (portRef C (instanceRef xjtag_bus_uut_oshift_13)) + (portRef C (instanceRef xjtag_bus_uut_oshift_14)) + (portRef C (instanceRef xjtag_bus_uut_oshift_15)) + (portRef C (instanceRef xjtag_bus_uut_oshift_16)) + (portRef C (instanceRef xjtag_bus_uut_oshift_17)) + (portRef C (instanceRef xjtag_bus_uut_oshift_18)) + (portRef C (instanceRef xjtag_bus_uut_oshift_19)) + (portRef C (instanceRef xjtag_bus_uut_oshift_20)) + (portRef C (instanceRef xjtag_bus_uut_oshift_21)) + (portRef C (instanceRef xjtag_bus_uut_oshift_22)) + (portRef C (instanceRef xjtag_bus_uut_oshift_23)) + (portRef C (instanceRef xjtag_bus_uut_oshift_24)) + (portRef C (instanceRef xjtag_bus_uut_oshift_25)) + (portRef C (instanceRef xjtag_bus_uut_oshift_26)) + (portRef C (instanceRef xjtag_bus_uut_oshift_27)) + (portRef C (instanceRef xjtag_bus_uut_oshift_28)) + (portRef C (instanceRef xjtag_bus_uut_oshift_29)) + (portRef C (instanceRef xjtag_bus_uut_oshift_30)) + (portRef C (instanceRef xjtag_bus_uut_oshift_31)) + (portRef C (instanceRef xjtag_bus_uut_oshift_32)) + (portRef C (instanceRef xjtag_bus_uut_oshift_33)) + (portRef C (instanceRef xjtag_bus_uut_dop1949_r_0)) + (portRef C (instanceRef xjtag_bus_uut_dop1949_r_1)) + (portRef C (instanceRef xjtag_bus_uut_dop_clk_r_0)) + (portRef C (instanceRef xjtag_bus_uut_dop_clk_r_1)) + (portRef C (instanceRef xjtag_bus_uut_dop_clk_r_2)) + (portRef C (instanceRef xjtag_bus_uut_dop_clk_r_3)) + (portRef C (instanceRef xjtag_bus_uut_chip_r_0)) + (portRef C (instanceRef xjtag_bus_uut_chip_r_1)) + (portRef C (instanceRef xjtag_bus_uut_chip_r_2)) + (portRef C (instanceRef xjtag_bus_uut_ishift_cnt_1)) + (portRef C (instanceRef xjtag_bus_uut_ishift_cnt_2)) + (portRef C (instanceRef xjtag_bus_uut_ishift_cnt_3)) + (portRef C (instanceRef xjtag_bus_uut_ishift_cnt_4)) + (portRef C (instanceRef xjtag_bus_uut_ishift_cnt_5)) + (portRef C (instanceRef xjtag_bus_uut_ishift_cnt_6)) + (portRef C (instanceRef xjtag_bus_uut_ishift_cnt_7)) + (portRef C (instanceRef xjtag_bus_uut_ishift_cnt_0)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_arvalid_renamed_14)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wvalid_renamed_15)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awvalid_renamed_16)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_issued_renamed_17)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_issued_renamed_18)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_write_renamed_19)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_read_renamed_20)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_rready_renamed_21)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_bready_renamed_22)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_ifinish_renamed_23)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iwr_rd_renamed_24)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_reads_done_renamed_25)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_read_renamed_26)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_writes_done_renamed_27)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_write_renamed_28)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_index_0_renamed_36)) + (portRef C (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_index_0_renamed_37)) + (portRef C (instanceRef xjtag_bus_uut_iwr_valid_renamed_38)) + (portRef C (instanceRef xjtag_bus_uut_ird_valid_renamed_39)) + (portRef C (instanceRef xjtag_bus_uut_axi_rvalid_renamed_40)) + (portRef C (instanceRef xjtag_bus_uut_axi_wvalid_renamed_41)) + (portRef C (instanceRef xjtag_bus_uut_dop1950_r_0_renamed_44)) + ) + ) + (net m00_axi_aresetn + (joined + (portRef m00_axi_aresetn) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_GND_5_o_init_txn_pulse_OR_42_o1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_val1)) + (portRef I0 (instanceRef xjtag_bus_uut__n0200_inv1_rstpot_renamed_43)) + (portRef I2 (instanceRef xjtag_bus_uut_iwr_valid_rstpot_renamed_53)) + (portRef I0 (instanceRef xjtag_bus_uut_axi_rvalid_rstpot_renamed_54)) + (portRef I1 (instanceRef xjtag_bus_uut_axi_wvalid_rstpot_renamed_63)) + (portRef I (instanceRef xjtag_axi_v1_0_M00_AXI_inst_M_AXI_ARESETN_inv1_INV_0)) + ) + ) + (net m00_axi_awready + (joined + (portRef m00_axi_awready) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awvalid_glue_set_renamed_58)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_write_glue_set_renamed_62)) + ) + ) + (net m00_axi_wready + (joined + (portRef m00_axi_wready) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wvalid_glue_set_renamed_57)) + ) + ) + (net m00_axi_bvalid + (joined + (portRef m00_axi_bvalid) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_M_AXI_BVALID_axi_bready_AND_22_o1)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_SW0)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_writes_done_glue_set_renamed_61)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0293_inv1)) + ) + ) + (net m00_axi_arready + (joined + (portRef m00_axi_arready) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_read_glue_set_renamed_60)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_ifinish_glue_set_renamed_65)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_arvalid_glue_set_renamed_66)) + ) + ) + (net m00_axi_rvalid + (joined + (portRef m00_axi_rvalid) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_M_AXI_RVALID_axi_rready_AND_30_o1)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0284_SW0)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_reads_done_glue_set_renamed_59)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_ifinish_glue_set_renamed_65)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0293_inv1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_31_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<31>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_31)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT271)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_30_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<30>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_30)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT261)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_29_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<29>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_29)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT251)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_28_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<28>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_28)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT241)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_27_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<27>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_27)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT221)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_26_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<26>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_26)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT211)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_25_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<25>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_25)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT201)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_24_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<24>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_24)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT191)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_23_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<23>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_23)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT181)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_22_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<22>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_22)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT171)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_21_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<21>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_21)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT161)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_20_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<20>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_20)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT151)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_19_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<19>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_19)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT141)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_18_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<18>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_18)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT131)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_17_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<17>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_17)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT111)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_16_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<16>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_16)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT101)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_15_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<15>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_15)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT91)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_14_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<14>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_14)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT81)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_13_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<13>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_13)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT71)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_12_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<12>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_12)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT61)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_11_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<11>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_11)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT51)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_10_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<10>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_10)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT41)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_9_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<9>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_9)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT35)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_8_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<8>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_8)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT210)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_7_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<7>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_7)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT341)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_6_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<6>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_6)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT331)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_5_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<5>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_5)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT321)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_4_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<4>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_4)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT311)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_3_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<3>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_3)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT301)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_2_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<2>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_2)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT291)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_1_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<1>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT281)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_data_0_ "xjtag_axi_v1_0_M00_AXI_inst/read_data<0>") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_0)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT231)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_31_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<31>") + (joined + (portRef (member m00_axi_awaddr 0)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_31)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_30_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<30>") + (joined + (portRef (member m00_axi_awaddr 1)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_30)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_29_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<29>") + (joined + (portRef (member m00_axi_awaddr 2)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_29)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_28_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<28>") + (joined + (portRef (member m00_axi_awaddr 3)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_28)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_27_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<27>") + (joined + (portRef (member m00_axi_awaddr 4)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_27)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_26_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<26>") + (joined + (portRef (member m00_axi_awaddr 5)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_26)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_25_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<25>") + (joined + (portRef (member m00_axi_awaddr 6)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_25)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_24_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<24>") + (joined + (portRef (member m00_axi_awaddr 7)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_24)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_23_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<23>") + (joined + (portRef (member m00_axi_awaddr 8)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_23)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_22_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<22>") + (joined + (portRef (member m00_axi_awaddr 9)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_22)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_21_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<21>") + (joined + (portRef (member m00_axi_awaddr 10)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_21)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_20_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<20>") + (joined + (portRef (member m00_axi_awaddr 11)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_20)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_19_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<19>") + (joined + (portRef (member m00_axi_awaddr 12)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_19)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_18_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<18>") + (joined + (portRef (member m00_axi_awaddr 13)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_18)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_17_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<17>") + (joined + (portRef (member m00_axi_awaddr 14)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_17)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_16_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<16>") + (joined + (portRef (member m00_axi_awaddr 15)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_16)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_15_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<15>") + (joined + (portRef (member m00_axi_awaddr 16)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_15)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_14_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<14>") + (joined + (portRef (member m00_axi_awaddr 17)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_14)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_13_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<13>") + (joined + (portRef (member m00_axi_awaddr 18)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_13)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_12_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<12>") + (joined + (portRef (member m00_axi_awaddr 19)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_12)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_11_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<11>") + (joined + (portRef (member m00_axi_awaddr 20)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_11)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_10_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<10>") + (joined + (portRef (member m00_axi_awaddr 21)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_10)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_9_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<9>") + (joined + (portRef (member m00_axi_awaddr 22)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_9)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_8_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<8>") + (joined + (portRef (member m00_axi_awaddr 23)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_8)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_7_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<7>") + (joined + (portRef (member m00_axi_awaddr 24)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_7)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_6_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<6>") + (joined + (portRef (member m00_axi_awaddr 25)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_6)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_5_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<5>") + (joined + (portRef (member m00_axi_awaddr 26)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_5)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_4_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<4>") + (joined + (portRef (member m00_axi_awaddr 27)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_4)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_3_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<3>") + (joined + (portRef (member m00_axi_awaddr 28)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_3)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_2_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<2>") + (joined + (portRef (member m00_axi_awaddr 29)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_2)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_1_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<1>") + (joined + (portRef (member m00_axi_awaddr 30)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_0_ "xjtag_axi_v1_0_M00_AXI_inst/axi_awaddr<0>") + (joined + (portRef (member m00_axi_awaddr 31)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_0)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_31_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<31>") + (joined + (portRef (member m00_axi_wdata 0)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_31)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_30_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<30>") + (joined + (portRef (member m00_axi_wdata 1)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_30)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_29_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<29>") + (joined + (portRef (member m00_axi_wdata 2)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_29)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_28_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<28>") + (joined + (portRef (member m00_axi_wdata 3)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_28)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_27_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<27>") + (joined + (portRef (member m00_axi_wdata 4)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_27)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_26_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<26>") + (joined + (portRef (member m00_axi_wdata 5)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_26)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_25_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<25>") + (joined + (portRef (member m00_axi_wdata 6)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_25)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_24_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<24>") + (joined + (portRef (member m00_axi_wdata 7)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_24)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_23_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<23>") + (joined + (portRef (member m00_axi_wdata 8)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_23)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_22_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<22>") + (joined + (portRef (member m00_axi_wdata 9)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_22)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_21_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<21>") + (joined + (portRef (member m00_axi_wdata 10)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_21)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_20_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<20>") + (joined + (portRef (member m00_axi_wdata 11)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_20)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_19_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<19>") + (joined + (portRef (member m00_axi_wdata 12)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_19)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_18_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<18>") + (joined + (portRef (member m00_axi_wdata 13)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_18)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_17_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<17>") + (joined + (portRef (member m00_axi_wdata 14)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_17)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_16_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<16>") + (joined + (portRef (member m00_axi_wdata 15)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_16)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_15_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<15>") + (joined + (portRef (member m00_axi_wdata 16)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_15)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_14_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<14>") + (joined + (portRef (member m00_axi_wdata 17)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_14)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_13_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<13>") + (joined + (portRef (member m00_axi_wdata 18)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_13)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_12_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<12>") + (joined + (portRef (member m00_axi_wdata 19)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_12)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_11_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<11>") + (joined + (portRef (member m00_axi_wdata 20)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_11)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_10_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<10>") + (joined + (portRef (member m00_axi_wdata 21)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_10)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_9_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<9>") + (joined + (portRef (member m00_axi_wdata 22)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_9)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_8_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<8>") + (joined + (portRef (member m00_axi_wdata 23)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_8)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_7_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<7>") + (joined + (portRef (member m00_axi_wdata 24)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_7)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_6_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<6>") + (joined + (portRef (member m00_axi_wdata 25)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_6)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_5_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<5>") + (joined + (portRef (member m00_axi_wdata 26)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_5)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_4_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<4>") + (joined + (portRef (member m00_axi_wdata 27)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_4)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_3_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<3>") + (joined + (portRef (member m00_axi_wdata 28)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_3)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_2_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<2>") + (joined + (portRef (member m00_axi_wdata 29)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_2)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_1_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<1>") + (joined + (portRef (member m00_axi_wdata 30)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_0_ "xjtag_axi_v1_0_M00_AXI_inst/axi_wdata<0>") + (joined + (portRef (member m00_axi_wdata 31)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_0)) + ) + ) + (net (rename xjtag_bus_uut_axi_wmask_3_ "xjtag_bus_uut/axi_wmask<3>") + (joined + (portRef (member m00_axi_wstrb 0)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wmask_3)) + ) + ) + (net (rename xjtag_bus_uut_axi_wmask_2_ "xjtag_bus_uut/axi_wmask<2>") + (joined + (portRef (member m00_axi_wstrb 1)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wmask_2)) + ) + ) + (net (rename xjtag_bus_uut_axi_wmask_1_ "xjtag_bus_uut/axi_wmask<1>") + (joined + (portRef (member m00_axi_wstrb 2)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wmask_1)) + ) + ) + (net (rename xjtag_bus_uut_axi_wmask_0_ "xjtag_bus_uut/axi_wmask<0>") + (joined + (portRef (member m00_axi_wstrb 3)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wmask_0)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_31_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<31>") + (joined + (portRef (member m00_axi_araddr 0)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_31)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_30_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<30>") + (joined + (portRef (member m00_axi_araddr 1)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_30)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_29_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<29>") + (joined + (portRef (member m00_axi_araddr 2)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_29)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_28_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<28>") + (joined + (portRef (member m00_axi_araddr 3)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_28)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_27_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<27>") + (joined + (portRef (member m00_axi_araddr 4)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_27)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_26_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<26>") + (joined + (portRef (member m00_axi_araddr 5)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_26)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_25_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<25>") + (joined + (portRef (member m00_axi_araddr 6)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_25)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_24_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<24>") + (joined + (portRef (member m00_axi_araddr 7)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_24)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_23_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<23>") + (joined + (portRef (member m00_axi_araddr 8)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_23)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_22_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<22>") + (joined + (portRef (member m00_axi_araddr 9)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_22)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_21_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<21>") + (joined + (portRef (member m00_axi_araddr 10)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_21)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_20_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<20>") + (joined + (portRef (member m00_axi_araddr 11)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_20)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_19_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<19>") + (joined + (portRef (member m00_axi_araddr 12)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_19)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_18_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<18>") + (joined + (portRef (member m00_axi_araddr 13)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_18)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_17_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<17>") + (joined + (portRef (member m00_axi_araddr 14)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_17)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_16_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<16>") + (joined + (portRef (member m00_axi_araddr 15)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_16)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_15_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<15>") + (joined + (portRef (member m00_axi_araddr 16)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_15)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_14_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<14>") + (joined + (portRef (member m00_axi_araddr 17)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_14)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_13_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<13>") + (joined + (portRef (member m00_axi_araddr 18)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_13)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_12_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<12>") + (joined + (portRef (member m00_axi_araddr 19)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_12)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_11_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<11>") + (joined + (portRef (member m00_axi_araddr 20)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_11)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_10_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<10>") + (joined + (portRef (member m00_axi_araddr 21)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_10)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_9_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<9>") + (joined + (portRef (member m00_axi_araddr 22)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_9)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_8_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<8>") + (joined + (portRef (member m00_axi_araddr 23)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_8)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_7_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<7>") + (joined + (portRef (member m00_axi_araddr 24)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_7)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_6_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<6>") + (joined + (portRef (member m00_axi_araddr 25)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_6)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_5_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<5>") + (joined + (portRef (member m00_axi_araddr 26)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_5)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_4_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<4>") + (joined + (portRef (member m00_axi_araddr 27)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_4)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_3_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<3>") + (joined + (portRef (member m00_axi_araddr 28)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_3)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_2_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<2>") + (joined + (portRef (member m00_axi_araddr 29)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_2)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_1_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<1>") + (joined + (portRef (member m00_axi_araddr 30)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_0_ "xjtag_axi_v1_0_M00_AXI_inst/axi_araddr<0>") + (joined + (portRef (member m00_axi_araddr 31)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_0)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_finish "xjtag_axi_v1_0_M00_AXI_inst/finish") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_finish_renamed_4)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT110)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT121)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awvalid "xjtag_axi_v1_0_M00_AXI_inst/axi_awvalid") + (joined + (portRef m00_axi_awvalid) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_SW0)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awvalid_renamed_16)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awvalid_glue_set_renamed_58)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wvalid "xjtag_axi_v1_0_M00_AXI_inst/axi_wvalid") + (joined + (portRef m00_axi_wvalid) + (portRef I4 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_renamed_11)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wvalid_renamed_15)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wvalid_glue_set_renamed_57)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_bready "xjtag_axi_v1_0_M00_AXI_inst/axi_bready") + (joined + (portRef m00_axi_bready) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_M_AXI_BVALID_axi_bready_AND_22_o1)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_bready_renamed_22)) + (portRef I4 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_issued_glue_set_renamed_50)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_write_glue_set_renamed_51)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_writes_done_glue_set_renamed_61)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0293_inv1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_arvalid "xjtag_axi_v1_0_M00_AXI_inst/axi_arvalid") + (joined + (portRef m00_axi_arvalid) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0284_SW0)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_arvalid_renamed_14)) + (portRef I4 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_ifinish_glue_set_renamed_65)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_arvalid_glue_set_renamed_66)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_rready "xjtag_axi_v1_0_M00_AXI_inst/axi_rready") + (joined + (portRef m00_axi_rready) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_M_AXI_RVALID_axi_rready_AND_30_o1)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_rready_renamed_21)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_issued_glue_set_renamed_49)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_read_glue_set_renamed_52)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_reads_done_glue_set_renamed_59)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_ifinish_glue_set_renamed_65)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0293_inv1)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_31_ "xjtag_bus_uut/axi_waddr<31>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_31)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_31)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_30_ "xjtag_bus_uut/axi_waddr<30>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_30)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_30)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_29_ "xjtag_bus_uut/axi_waddr<29>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_29)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_29)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_28_ "xjtag_bus_uut/axi_waddr<28>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_28)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_28)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_27_ "xjtag_bus_uut/axi_waddr<27>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_27)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_27)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_26_ "xjtag_bus_uut/axi_waddr<26>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_26)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_26)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_25_ "xjtag_bus_uut/axi_waddr<25>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_25)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_25)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_24_ "xjtag_bus_uut/axi_waddr<24>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_24)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_24)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_23_ "xjtag_bus_uut/axi_waddr<23>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_23)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_23)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_22_ "xjtag_bus_uut/axi_waddr<22>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_22)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_22)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_21_ "xjtag_bus_uut/axi_waddr<21>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_21)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_21)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_20_ "xjtag_bus_uut/axi_waddr<20>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_20)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_20)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_19_ "xjtag_bus_uut/axi_waddr<19>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_19)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_19)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_18_ "xjtag_bus_uut/axi_waddr<18>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_18)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_18)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_17_ "xjtag_bus_uut/axi_waddr<17>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_17)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_17)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_16_ "xjtag_bus_uut/axi_waddr<16>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_16)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_16)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_15_ "xjtag_bus_uut/axi_waddr<15>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_15)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_15)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_14_ "xjtag_bus_uut/axi_waddr<14>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_14)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_14)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_13_ "xjtag_bus_uut/axi_waddr<13>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_13)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_13)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_12_ "xjtag_bus_uut/axi_waddr<12>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_12)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_12)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_11_ "xjtag_bus_uut/axi_waddr<11>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_11)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_11)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_10_ "xjtag_bus_uut/axi_waddr<10>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_10)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_10)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_9_ "xjtag_bus_uut/axi_waddr<9>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_9)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_9)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_8_ "xjtag_bus_uut/axi_waddr<8>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_8)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_8)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_7_ "xjtag_bus_uut/axi_waddr<7>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_7)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_7)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_6_ "xjtag_bus_uut/axi_waddr<6>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_6)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_6)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_5_ "xjtag_bus_uut/axi_waddr<5>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_5)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_5)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_4_ "xjtag_bus_uut/axi_waddr<4>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_4)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_4)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_3_ "xjtag_bus_uut/axi_waddr<3>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_3)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_3)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_2_ "xjtag_bus_uut/axi_waddr<2>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_2)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_2)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_1_ "xjtag_bus_uut/axi_waddr<1>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_1)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_1)) + ) + ) + (net (rename xjtag_bus_uut_axi_waddr_0_ "xjtag_bus_uut/axi_waddr<0>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_0)) + (portRef Q (instanceRef xjtag_bus_uut_axi_waddr_0)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_31_ "xjtag_bus_uut/axi_wdata<31>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_31)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_31)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_30_ "xjtag_bus_uut/axi_wdata<30>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_30)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_30)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_29_ "xjtag_bus_uut/axi_wdata<29>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_29)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_29)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_28_ "xjtag_bus_uut/axi_wdata<28>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_28)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_28)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_27_ "xjtag_bus_uut/axi_wdata<27>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_27)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_27)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_26_ "xjtag_bus_uut/axi_wdata<26>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_26)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_26)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_25_ "xjtag_bus_uut/axi_wdata<25>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_25)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_25)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_24_ "xjtag_bus_uut/axi_wdata<24>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_24)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_24)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_23_ "xjtag_bus_uut/axi_wdata<23>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_23)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_23)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_22_ "xjtag_bus_uut/axi_wdata<22>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_22)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_22)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_21_ "xjtag_bus_uut/axi_wdata<21>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_21)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_21)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_20_ "xjtag_bus_uut/axi_wdata<20>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_20)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_20)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_19_ "xjtag_bus_uut/axi_wdata<19>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_19)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_19)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_18_ "xjtag_bus_uut/axi_wdata<18>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_18)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_18)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_17_ "xjtag_bus_uut/axi_wdata<17>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_17)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_17)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_16_ "xjtag_bus_uut/axi_wdata<16>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_16)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_16)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_15_ "xjtag_bus_uut/axi_wdata<15>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_15)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_15)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_14_ "xjtag_bus_uut/axi_wdata<14>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_14)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_14)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_13_ "xjtag_bus_uut/axi_wdata<13>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_13)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_13)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_12_ "xjtag_bus_uut/axi_wdata<12>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_12)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_12)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_11_ "xjtag_bus_uut/axi_wdata<11>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_11)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_11)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_10_ "xjtag_bus_uut/axi_wdata<10>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_10)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_10)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_9_ "xjtag_bus_uut/axi_wdata<9>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_9)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_9)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_8_ "xjtag_bus_uut/axi_wdata<8>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_8)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_8)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_7_ "xjtag_bus_uut/axi_wdata<7>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_7)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_7)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_6_ "xjtag_bus_uut/axi_wdata<6>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_6)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_6)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_5_ "xjtag_bus_uut/axi_wdata<5>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_5)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_5)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_4_ "xjtag_bus_uut/axi_wdata<4>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_4)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_4)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_3_ "xjtag_bus_uut/axi_wdata<3>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_3)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_3)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_2_ "xjtag_bus_uut/axi_wdata<2>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_2)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_2)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_1_ "xjtag_bus_uut/axi_wdata<1>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_1)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_1)) + ) + ) + (net (rename xjtag_bus_uut_axi_wdata_0_ "xjtag_bus_uut/axi_wdata<0>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_0)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wdata_0)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_31_ "xjtag_bus_uut/axi_raddr<31>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_31)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_31)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_30_ "xjtag_bus_uut/axi_raddr<30>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_30)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_30)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_29_ "xjtag_bus_uut/axi_raddr<29>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_29)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_29)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_28_ "xjtag_bus_uut/axi_raddr<28>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_28)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_28)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_27_ "xjtag_bus_uut/axi_raddr<27>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_27)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_27)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_26_ "xjtag_bus_uut/axi_raddr<26>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_26)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_26)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_25_ "xjtag_bus_uut/axi_raddr<25>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_25)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_25)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_24_ "xjtag_bus_uut/axi_raddr<24>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_24)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_24)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_23_ "xjtag_bus_uut/axi_raddr<23>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_23)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_23)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_22_ "xjtag_bus_uut/axi_raddr<22>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_22)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_22)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_21_ "xjtag_bus_uut/axi_raddr<21>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_21)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_21)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_20_ "xjtag_bus_uut/axi_raddr<20>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_20)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_20)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_19_ "xjtag_bus_uut/axi_raddr<19>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_19)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_19)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_18_ "xjtag_bus_uut/axi_raddr<18>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_18)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_18)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_17_ "xjtag_bus_uut/axi_raddr<17>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_17)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_17)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_16_ "xjtag_bus_uut/axi_raddr<16>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_16)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_16)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_15_ "xjtag_bus_uut/axi_raddr<15>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_15)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_15)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_14_ "xjtag_bus_uut/axi_raddr<14>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_14)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_14)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_13_ "xjtag_bus_uut/axi_raddr<13>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_13)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_13)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_12_ "xjtag_bus_uut/axi_raddr<12>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_12)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_12)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_11_ "xjtag_bus_uut/axi_raddr<11>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_11)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_11)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_10_ "xjtag_bus_uut/axi_raddr<10>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_10)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_10)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_9_ "xjtag_bus_uut/axi_raddr<9>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_9)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_9)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_8_ "xjtag_bus_uut/axi_raddr<8>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_8)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_8)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_7_ "xjtag_bus_uut/axi_raddr<7>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_7)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_7)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_6_ "xjtag_bus_uut/axi_raddr<6>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_6)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_6)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_5_ "xjtag_bus_uut/axi_raddr<5>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_5)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_5)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_4_ "xjtag_bus_uut/axi_raddr<4>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_4)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_4)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_3_ "xjtag_bus_uut/axi_raddr<3>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_3)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_3)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_2_ "xjtag_bus_uut/axi_raddr<2>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_2)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_2)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_1_ "xjtag_bus_uut/axi_raddr<1>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_1)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_1)) + ) + ) + (net (rename xjtag_bus_uut_axi_raddr_0_ "xjtag_bus_uut/axi_raddr<0>") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_0)) + (portRef Q (instanceRef xjtag_bus_uut_axi_raddr_0)) + ) + ) + (net (rename xjtag_bus_uut_axi_wvalid "xjtag_bus_uut/axi_wvalid") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_req_d0_renamed_9)) + (portRef Q (instanceRef xjtag_bus_uut_axi_wvalid_renamed_41)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iwr_rd_glue_set_renamed_64)) + ) + ) + (net (rename xjtag_bus_uut_axi_rvalid "xjtag_bus_uut/axi_rvalid") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iread_req_renamed_8)) + (portRef Q (instanceRef xjtag_bus_uut_axi_rvalid_renamed_40)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iwr_rd_glue_set_renamed_64)) + ) + ) + (net (rename m00_axi_arprot_0_ "m00_axi_arprot<0>") + (joined + (portRef P (instanceRef XST_VCC)) + (portRef (member m00_axi_arprot 2)) + (portRef DI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_0__)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd1_In "xjtag_axi_v1_0_M00_AXI_inst/mst_exec_state_FSM_FFd1-In") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd1_renamed_0)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd1_In1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd2_In "xjtag_axi_v1_0_M00_AXI_inst/mst_exec_state_FSM_FFd2-In") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd2_renamed_1)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd2_In1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst__n0293_inv "xjtag_axi_v1_0_M00_AXI_inst/_n0293_inv") + (joined + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_0)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_1)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_2)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_3)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_4)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_5)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_6)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_7)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_8)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_9)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_10)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_11)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_12)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_13)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_14)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_15)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_16)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_17)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_18)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_19)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_20)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_21)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_22)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_23)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_24)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_25)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_26)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_27)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_28)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_29)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_30)) + (portRef CE (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_31)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0293_inv1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_M_AXI_ARESETN_inv "xjtag_axi_v1_0_M00_AXI_inst/M_AXI_ARESETN_inv") + (joined + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_0)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_1)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_2)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_3)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_4)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_5)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_6)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_7)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_8)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_9)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_10)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_11)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_12)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_13)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_14)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_15)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_16)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_17)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_18)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_19)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_20)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_21)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_22)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_23)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_24)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_25)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_26)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_27)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_28)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_29)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_30)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_araddr_31)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_0)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_1)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_2)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_3)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_4)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_5)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_6)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_7)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_8)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_9)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_10)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_11)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_12)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_13)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_14)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_15)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_16)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_17)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_18)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_19)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_20)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_21)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_22)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_23)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_24)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_25)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_26)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_27)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_28)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_29)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_30)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awaddr_31)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_req_d1_renamed_6)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iiread_req_renamed_5)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_finish_renamed_4)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff_renamed_3)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff2_renamed_2)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_0)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_1)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_2)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_3)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_4)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_5)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_6)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_7)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_8)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_9)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_10)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_11)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_12)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_13)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_14)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_15)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_16)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_17)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_18)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_19)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_20)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_21)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_22)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_23)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_24)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_25)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_26)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_27)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_28)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_29)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_30)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wdata_31)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_0)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_1)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_2)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_3)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_4)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_5)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_6)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_data_7)) 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(portRef R (instanceRef xjtag_bus_uut_axi_waddr_15)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_16)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_17)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_18)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_19)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_20)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_21)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_22)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_23)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_24)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_25)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_26)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_27)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_28)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_29)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_30)) + (portRef R (instanceRef xjtag_bus_uut_axi_waddr_31)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_0)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_1)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_2)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_3)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_4)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_5)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_6)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_7)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_8)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_9)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_10)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_11)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_12)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_13)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_14)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_15)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_16)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_17)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_18)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_19)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_20)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_21)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_22)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_23)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_24)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_25)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_26)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_27)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_28)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_29)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_30)) + (portRef R (instanceRef xjtag_bus_uut_axi_raddr_31)) + (portRef R (instanceRef xjtag_bus_uut_dop1950_r_0_renamed_44)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_M_AXI_ARESETN_inv1_INV_0)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff2_iiread_req_OR_41_o "xjtag_axi_v1_0_M00_AXI_inst/init_txn_ff2_iiread_req_OR_41_o") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_pulse_renamed_7)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff2_iiread_req_OR_41_o1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst__n0284 "xjtag_axi_v1_0_M00_AXI_inst/_n0284") + (joined + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0284_renamed_10)) + (portRef I5 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_issued_glue_set_renamed_49)) + (portRef I5 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_read_glue_set_renamed_52)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst__n0276 "xjtag_axi_v1_0_M00_AXI_inst/_n0276") + (joined + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_renamed_11)) + (portRef I5 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_issued_glue_set_renamed_50)) + (portRef I5 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_write_glue_set_renamed_51)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_GND_5_o_init_txn_pulse_OR_42_o "xjtag_axi_v1_0_M00_AXI_inst/GND_5_o_init_txn_pulse_OR_42_o") + (joined + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_GND_5_o_init_txn_pulse_OR_42_o1)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_arvalid_renamed_14)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wvalid_renamed_15)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awvalid_renamed_16)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_rready_renamed_21)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_bready_renamed_22)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_reads_done_renamed_25)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_read_renamed_26)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_writes_done_renamed_27)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_write_renamed_28)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_index_0_renamed_36)) + (portRef R (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_index_0_renamed_37)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_issued "xjtag_axi_v1_0_M00_AXI_inst/read_issued") + (joined + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0284_renamed_10)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_issued_renamed_17)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_issued_glue_set_renamed_49)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_start_single_read "xjtag_axi_v1_0_M00_AXI_inst/start_single_read") + (joined + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0284_renamed_10)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_read_renamed_20)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_read_glue_set_renamed_52)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_index_0_rstpot_renamed_56)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_arvalid_glue_set_renamed_66)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_write_issued "xjtag_axi_v1_0_M00_AXI_inst/write_issued") + (joined + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_renamed_11)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_issued_renamed_18)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_issued_glue_set_renamed_50)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_start_single_write "xjtag_axi_v1_0_M00_AXI_inst/start_single_write") + (joined + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_renamed_11)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_write_renamed_19)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_write_glue_set_renamed_51)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_index_0_rstpot_renamed_55)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wvalid_glue_set_renamed_57)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awvalid_glue_set_renamed_58)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_ifinish "xjtag_axi_v1_0_M00_AXI_inst/ifinish") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_finish_renamed_4)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_ifinish_renamed_23)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_ifinish_glue_set_renamed_65)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_iwr_rd "xjtag_axi_v1_0_M00_AXI_inst/iwr_rd") + (joined + (portRef I4 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd1_In1)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd2_In1)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iwr_rd_renamed_24)) + (portRef I4 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iwr_rd_glue_set_renamed_64)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_index_0 "xjtag_axi_v1_0_M00_AXI_inst/read_index_0") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_index_0_renamed_37)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_index_0_rstpot_renamed_56)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_read_glue_set_renamed_60)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_write_index_0 "xjtag_axi_v1_0_M00_AXI_inst/write_index_0") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_index_0_renamed_36)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_index_0_rstpot_renamed_55)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_write_glue_set_renamed_62)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd2 "xjtag_axi_v1_0_M00_AXI_inst/mst_exec_state_FSM_FFd2") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd2_renamed_1)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd1_In1)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd2_In1)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0284_renamed_10)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_renamed_11)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_issued_glue_set_renamed_49)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_issued_glue_set_renamed_50)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_write_glue_set_renamed_51)) + (portRef I4 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_read_glue_set_renamed_52)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd1 "xjtag_axi_v1_0_M00_AXI_inst/mst_exec_state_FSM_FFd1") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd1_renamed_0)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd1_In1)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd2_In1)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0284_renamed_10)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_renamed_11)) + (portRef I4 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_issued_glue_set_renamed_49)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_issued_glue_set_renamed_50)) + (portRef I4 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_write_glue_set_renamed_51)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_read_glue_set_renamed_52)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_reads_done "xjtag_axi_v1_0_M00_AXI_inst/reads_done") + (joined + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd1_In1)) + (portRef I4 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0284_renamed_10)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_reads_done_renamed_25)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_issued_glue_set_renamed_49)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_read_glue_set_renamed_52)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_reads_done_glue_set_renamed_59)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_last_read "xjtag_axi_v1_0_M00_AXI_inst/last_read") + (joined + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0284_SW0)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_read_renamed_26)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_reads_done_glue_set_renamed_59)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_read_glue_set_renamed_60)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_writes_done "xjtag_axi_v1_0_M00_AXI_inst/writes_done") + (joined + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd2_In1)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_SW0)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_writes_done_renamed_27)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_issued_glue_set_renamed_50)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_write_glue_set_renamed_51)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_writes_done_glue_set_renamed_61)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_last_write "xjtag_axi_v1_0_M00_AXI_inst/last_write") + (joined + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_SW0)) + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_write_renamed_28)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_writes_done_glue_set_renamed_61)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_write_glue_set_renamed_62)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_init_txn_pulse "xjtag_axi_v1_0_M00_AXI_inst/init_txn_pulse") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_pulse_renamed_7)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd1_In1)) + (portRef I4 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_mst_exec_state_FSM_FFd2_In1)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_GND_5_o_init_txn_pulse_OR_42_o1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_iiread_req "xjtag_axi_v1_0_M00_AXI_inst/iiread_req") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iiread_req_renamed_5)) + (portRef I2 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff2_iiread_req_OR_41_o1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff2 "xjtag_axi_v1_0_M00_AXI_inst/init_txn_ff2") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff2_renamed_2)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff2_iiread_req_OR_41_o1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff "xjtag_axi_v1_0_M00_AXI_inst/init_txn_ff") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff_renamed_3)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff2_renamed_2)) + (portRef I1 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff2_iiread_req_OR_41_o1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_write_req_d1 "xjtag_axi_v1_0_M00_AXI_inst/write_req_d1") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_req_d1_renamed_6)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff_renamed_3)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_iread_req "xjtag_axi_v1_0_M00_AXI_inst/iread_req") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iread_req_renamed_8)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iiread_req_renamed_5)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_init_txn_ff2_iiread_req_OR_41_o1)) + (portRef I3 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iwr_rd_glue_set_renamed_64)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_write_req_d0 "xjtag_axi_v1_0_M00_AXI_inst/write_req_d0") + (joined + (portRef Q (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_req_d0_renamed_9)) + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_req_d1_renamed_6)) + (portRef I0 (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iwr_rd_glue_set_renamed_64)) + ) + ) + (net (rename xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1 "xjtag_bus_uut/chip_r[1]_ishift_cnt[7]_AND_9_o1") + (joined + (portRef O (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_renamed_13)) + (portRef I4 (instanceRef xjtag_bus_uut__n0231_inv1)) + (portRef I5 (instanceRef xjtag_bus_uut_ird_valid_rstpot_renamed_42)) + (portRef I4 (instanceRef xjtag_bus_uut_dop1950_r_0_rstpot_renamed_45)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_6_ "xjtag_bus_uut/Mcount_ishift_cnt_cy<6>") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_6__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_7__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_5_ "xjtag_bus_uut/Mcount_ishift_cnt_cy<5>") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_5__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_6__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_6__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_4_ "xjtag_bus_uut/Mcount_ishift_cnt_cy<4>") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_4__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_5__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_5__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_3_ "xjtag_bus_uut/Mcount_ishift_cnt_cy<3>") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_3__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_4__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_4__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_2_ "xjtag_bus_uut/Mcount_ishift_cnt_cy<2>") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_2__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_3__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_3__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_1_ "xjtag_bus_uut/Mcount_ishift_cnt_cy<1>") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_1__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_2__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_2__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_0_ "xjtag_bus_uut/Mcount_ishift_cnt_cy<0>") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_0__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_1__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_1__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_lut_0_ "xjtag_bus_uut/Mcount_ishift_cnt_lut<0>") + (joined + (portRef S (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_0__)) + (portRef LI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_0__)) + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_lut_0__INV_0)) + ) + ) + (net (rename xjtag_bus_uut_Result_7_ "xjtag_bus_uut/Result<7>") + (joined + (portRef D (instanceRef xjtag_bus_uut_ishift_cnt_7)) + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_7__)) + ) + ) + (net (rename xjtag_bus_uut_Result_6_ "xjtag_bus_uut/Result<6>") + (joined + (portRef D (instanceRef xjtag_bus_uut_ishift_cnt_6)) + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_6__)) + ) + ) + (net (rename xjtag_bus_uut_Result_5_ "xjtag_bus_uut/Result<5>") + (joined + (portRef D (instanceRef xjtag_bus_uut_ishift_cnt_5)) + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_5__)) + ) + ) + (net (rename xjtag_bus_uut_Result_4_ "xjtag_bus_uut/Result<4>") + (joined + (portRef D (instanceRef xjtag_bus_uut_ishift_cnt_4)) + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_4__)) + ) + ) + (net (rename xjtag_bus_uut_Result_3_ "xjtag_bus_uut/Result<3>") + (joined + (portRef D (instanceRef xjtag_bus_uut_ishift_cnt_3)) + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_3__)) + ) + ) + (net (rename xjtag_bus_uut_Result_2_ "xjtag_bus_uut/Result<2>") + (joined + (portRef D (instanceRef xjtag_bus_uut_ishift_cnt_2)) + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_2__)) + ) + ) + (net (rename xjtag_bus_uut_Result_1_ "xjtag_bus_uut/Result<1>") + (joined + (portRef D (instanceRef xjtag_bus_uut_ishift_cnt_1)) + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_1__)) + ) + ) + (net (rename xjtag_bus_uut_Result_0_ "xjtag_bus_uut/Result<0>") + (joined + (portRef D (instanceRef xjtag_bus_uut_ishift_cnt_0)) + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_0__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_val "xjtag_bus_uut/Mcount_ishift_cnt_val") + (joined + (portRef R (instanceRef xjtag_bus_uut_ishift_cnt_0)) + (portRef R (instanceRef xjtag_bus_uut_ishift_cnt_7)) + (portRef R (instanceRef xjtag_bus_uut_ishift_cnt_6)) + (portRef R (instanceRef xjtag_bus_uut_ishift_cnt_5)) + (portRef R (instanceRef xjtag_bus_uut_ishift_cnt_4)) + (portRef R (instanceRef xjtag_bus_uut_ishift_cnt_3)) + (portRef R (instanceRef xjtag_bus_uut_ishift_cnt_2)) + (portRef R (instanceRef xjtag_bus_uut_ishift_cnt_1)) + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_val1)) + (portRef I4 (instanceRef xjtag_bus_uut_ird_valid_rstpot_renamed_42)) + ) + ) + (net (rename xjtag_bus_uut_bscan_xjtag_uut_RUNTEST "xjtag_bus_uut/bscan_xjtag_uut/RUNTEST") + (joined + (portRef RUNTEST (instanceRef xjtag_bus_uut_bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef I0 (instanceRef xjtag_bus_uut_bscan_xjtag_uut_Mmux_CS11)) + ) + ) + (net (rename xjtag_bus_uut_bscan_xjtag_uut_SEL "xjtag_bus_uut/bscan_xjtag_uut/SEL") + (joined + (portRef SEL (instanceRef xjtag_bus_uut_bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef I1 (instanceRef xjtag_bus_uut_bscan_xjtag_uut_Mmux_CS11)) + ) + ) + (net (rename xjtag_bus_uut_bscan_xjtag_uut_SHIFT "xjtag_bus_uut/bscan_xjtag_uut/SHIFT") + (joined + (portRef SHIFT (instanceRef xjtag_bus_uut_bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef I1 (instanceRef xjtag_bus_uut_bscan_xjtag_uut_DOP19491)) + (portRef I0 (instanceRef xjtag_bus_uut_bscan_xjtag_uut_CLK1)) + ) + ) + (net (rename xjtag_bus_uut_bscan_xjtag_uut_TCK "xjtag_bus_uut/bscan_xjtag_uut/TCK") + (joined + (portRef TCK (instanceRef xjtag_bus_uut_bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef I1 (instanceRef xjtag_bus_uut_bscan_xjtag_uut_CLK1)) + ) + ) + (net (rename xjtag_bus_uut_bscan_xjtag_uut_TDI "xjtag_bus_uut/bscan_xjtag_uut/TDI") + (joined + (portRef TDI (instanceRef xjtag_bus_uut_bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef I0 (instanceRef xjtag_bus_uut_bscan_xjtag_uut_DOP19491)) + ) + ) + (net (rename xjtag_bus_uut__n0231_inv "xjtag_bus_uut/_n0231_inv") + (joined + (portRef CE (instanceRef xjtag_bus_uut_oshift_0)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_1)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_2)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_3)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_4)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_5)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_6)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_7)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_8)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_9)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_10)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_11)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_12)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_13)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_14)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_15)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_16)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_17)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_18)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_19)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_20)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_21)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_22)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_23)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_24)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_25)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_26)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_27)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_28)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_29)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_30)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_31)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_32)) + (portRef CE (instanceRef xjtag_bus_uut_oshift_33)) + (portRef O (instanceRef xjtag_bus_uut__n0231_inv1)) + ) + ) + (net (rename xjtag_bus_uut__n0207_inv "xjtag_bus_uut/_n0207_inv") + (joined + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_0)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_1)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_2)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_3)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_4)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_5)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_6)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_7)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_8)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_9)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_10)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_11)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_12)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_13)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_14)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_15)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_16)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_17)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_18)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_19)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_20)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_21)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_22)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_23)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_24)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_25)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_26)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_27)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_28)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_29)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_30)) + (portRef CE (instanceRef xjtag_bus_uut_axi_waddr_31)) + (portRef O (instanceRef xjtag_bus_uut__n0207_inv1)) + ) + ) + (net (rename xjtag_bus_uut__n0211_inv "xjtag_bus_uut/_n0211_inv") + (joined + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_0)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_1)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_2)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_3)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_4)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_5)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_6)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_7)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_8)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_9)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_10)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_11)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_12)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_13)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_14)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_15)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_16)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_17)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_18)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_19)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_20)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_21)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_22)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_23)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_24)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_25)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_26)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_27)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_28)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_29)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_30)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wdata_31)) + (portRef O (instanceRef xjtag_bus_uut__n0211_inv1)) + ) + ) + (net (rename xjtag_bus_uut__n0216_inv "xjtag_bus_uut/_n0216_inv") + (joined + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_0)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_1)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_2)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_3)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_4)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_5)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_6)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_7)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_8)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_9)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_10)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_11)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_12)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_13)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_14)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_15)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_16)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_17)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_18)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_19)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_20)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_21)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_22)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_23)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_24)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_25)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_26)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_27)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_28)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_29)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_30)) + (portRef CE (instanceRef xjtag_bus_uut_icrab_data_31)) + (portRef O (instanceRef xjtag_bus_uut__n0216_inv1)) + ) + ) + (net (rename xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o "xjtag_bus_uut/dop_clk_r[2]_ishift_cnt[7]_AND_13_o") + (joined + (portRef O (instanceRef xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT110)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT121)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT210)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT35)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT41)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT51)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT61)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT71)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT81)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT91)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT101)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT111)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT131)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT141)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT151)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT161)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT171)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT181)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT191)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT201)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT211)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT221)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT241)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT251)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT261)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT271)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT281)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT291)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT301)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT311)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT321)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT331)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT341)) + (portRef I4 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT231)) + ) + ) + (net (rename xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o "xjtag_bus_uut/dop_clk_r[2]_GND_2_o_AND_15_o") + (joined + (portRef O (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_renamed_12)) + (portRef I5 (instanceRef xjtag_bus_uut__n0231_inv1)) + (portRef I5 (instanceRef xjtag_bus_uut_dop1950_r_0_rstpot_renamed_45)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_0_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<0>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_0)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_0_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_1_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<1>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_1)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_1_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_2_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<2>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_2)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_2_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_3_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<3>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_3)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_3_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_4_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<4>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_4)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_4_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_5_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<5>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_5)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_5_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_6_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<6>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_6)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_6_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_7_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<7>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_7)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_7_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_8_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<8>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_8)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_8_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_9_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<9>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_9)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_9_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_10_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<10>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_10)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_10_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_11_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<11>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_11)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_11_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_12_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<12>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_12)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_12_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_13_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<13>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_13)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_13_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_14_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<14>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_14)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_14_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_15_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<15>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_15)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_15_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_16_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<16>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_16)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_16_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_17_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<17>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_17)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_17_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_18_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<18>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_18)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_18_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_19_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<19>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_19)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_19_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_20_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<20>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_20)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_20_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_21_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<21>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_21)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_21_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_22_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<22>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_22)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_22_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_23_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<23>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_23)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_23_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_24_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<24>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_24)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_24_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_25_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<25>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_25)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_25_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_26_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<26>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_26)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_26_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_27_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<27>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_27)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_27_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_28_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<28>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_28)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_28_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_29_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<29>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_29)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_29_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_30_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<30>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_30)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_30_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_69__icrab_data_31__xor_72_OUT_31_ "xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_72_OUT<31>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_raddr_31)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_31_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_data_71__PWR_2_o_equal_69_o "xjtag_bus_uut/ishift_data[71]_PWR_2_o_equal_69_o") + (joined + (portRef O (instanceRef xjtag_bus_uut_ishift_data_71__PWR_2_o_equal_69_o_31_1)) + (portRef I0 (instanceRef xjtag_bus_uut_ird_valid_rstpot_renamed_42)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_0_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<0>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_0)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_0_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_1_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<1>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_1)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_1_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_2_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<2>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_2)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_2_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_3_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<3>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_3)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_3_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_4_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<4>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_4)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_4_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_5_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<5>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_5)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_5_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_6_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<6>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_6)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_6_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_7_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<7>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_7)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_7_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_8_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<8>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_8)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_8_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_9_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<9>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_9)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_9_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_10_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<10>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_10)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_10_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_11_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<11>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_11)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_11_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_12_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<12>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_12)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_12_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_13_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<13>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_13)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_13_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_14_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<14>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_14)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_14_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_15_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<15>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_15)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_15_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_16_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<16>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_16)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_16_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_17_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<17>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_17)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_17_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_18_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<18>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_18)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_18_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_19_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<19>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_19)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_19_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_20_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<20>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_20)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_20_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_21_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<21>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_21)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_21_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_22_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<22>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_22)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_22_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_23_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<23>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_23)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_23_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_24_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<24>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_24)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_24_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_25_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<25>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_25)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_25_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_26_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<26>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_26)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_26_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_27_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<27>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_27)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_27_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_28_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<28>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_28)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_28_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_29_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<29>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_29)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_29_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_30_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<30>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_30)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_30_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31__icrab_data_31__xor_42_OUT_31_ "xjtag_bus_uut/wdata[31]_icrab_data[31]_xor_42_OUT<31>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wdata_31)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_31_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_0_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<0>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_0)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_0_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_1_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<1>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_1)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_1_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_2_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<2>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_2)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_2_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_3_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<3>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_3)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_3_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_4_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<4>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_4)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_4_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_5_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<5>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_5)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_5_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_6_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<6>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_6)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_6_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_7_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<7>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_7)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_7_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_8_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<8>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_8)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_8_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_9_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<9>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_9)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_9_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_10_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<10>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_10)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_10_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_11_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<11>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_11)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_11_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_12_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<12>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_12)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_12_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_13_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<13>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_13)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_13_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_14_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<14>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_14)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_14_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_15_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<15>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_15)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_15_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_16_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<16>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_16)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_16_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_17_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<17>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_17)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_17_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_18_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<18>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_18)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_18_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_19_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<19>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_19)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_19_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_20_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<20>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_20)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_20_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_21_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<21>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_21)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_21_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_22_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<22>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_22)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_22_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_23_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<23>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_23)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_23_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_24_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<24>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_24)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_24_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_25_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<25>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_25)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_25_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_26_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<26>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_26)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_26_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_27_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<27>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_27)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_27_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_28_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<28>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_28)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_28_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_29_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<29>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_29)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_29_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_30_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<30>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_30)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_30_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31__icrab_data_31__xor_39_OUT_31_ "xjtag_bus_uut/addr[31]_icrab_data[31]_xor_39_OUT<31>") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_waddr_31)) + (portRef O (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_31_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_dop_clk_r_2__dop_clk_r_1__AND_3_o "xjtag_bus_uut/dop_clk_r[2]_dop_clk_r[1]_AND_3_o") + (joined + (portRef CE (instanceRef xjtag_bus_uut_wdata_0)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_1)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_2)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_3)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_4)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_5)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_6)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_7)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_8)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_9)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_10)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_11)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_12)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_13)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_14)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_15)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_16)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_17)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_18)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_19)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_20)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_21)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_22)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_23)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_24)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_25)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_26)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_27)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_28)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_29)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_30)) + (portRef CE (instanceRef xjtag_bus_uut_wdata_31)) + (portRef CE (instanceRef xjtag_bus_uut_cmd_0)) + (portRef CE (instanceRef xjtag_bus_uut_cmd_1)) + (portRef CE (instanceRef xjtag_bus_uut_cmd_2)) + (portRef CE (instanceRef xjtag_bus_uut_cmd_3)) + (portRef CE (instanceRef xjtag_bus_uut_cmd_4)) + (portRef CE (instanceRef xjtag_bus_uut_cmd_5)) + (portRef CE (instanceRef xjtag_bus_uut_cmd_6)) + (portRef CE (instanceRef xjtag_bus_uut_cmd_7)) + (portRef CE (instanceRef xjtag_bus_uut_addr_0)) + (portRef CE (instanceRef xjtag_bus_uut_addr_1)) + (portRef CE (instanceRef xjtag_bus_uut_addr_2)) + (portRef CE (instanceRef xjtag_bus_uut_addr_3)) + (portRef CE (instanceRef xjtag_bus_uut_addr_4)) + (portRef CE (instanceRef xjtag_bus_uut_addr_5)) + (portRef CE (instanceRef xjtag_bus_uut_addr_6)) + (portRef CE (instanceRef xjtag_bus_uut_addr_7)) + (portRef CE (instanceRef xjtag_bus_uut_addr_8)) + (portRef CE (instanceRef xjtag_bus_uut_addr_9)) + (portRef CE (instanceRef xjtag_bus_uut_addr_10)) + (portRef CE (instanceRef xjtag_bus_uut_addr_11)) + (portRef CE (instanceRef xjtag_bus_uut_addr_12)) + (portRef CE (instanceRef xjtag_bus_uut_addr_13)) + (portRef CE (instanceRef xjtag_bus_uut_addr_14)) + (portRef CE (instanceRef xjtag_bus_uut_addr_15)) + (portRef CE (instanceRef xjtag_bus_uut_addr_16)) + (portRef CE (instanceRef xjtag_bus_uut_addr_17)) + (portRef CE (instanceRef xjtag_bus_uut_addr_18)) + (portRef CE (instanceRef xjtag_bus_uut_addr_19)) + (portRef CE (instanceRef xjtag_bus_uut_addr_20)) + (portRef CE (instanceRef xjtag_bus_uut_addr_21)) + (portRef CE (instanceRef xjtag_bus_uut_addr_22)) + (portRef CE (instanceRef xjtag_bus_uut_addr_23)) + (portRef CE (instanceRef xjtag_bus_uut_addr_24)) + (portRef CE (instanceRef xjtag_bus_uut_addr_25)) + (portRef CE (instanceRef xjtag_bus_uut_addr_26)) + (portRef CE (instanceRef xjtag_bus_uut_addr_27)) + (portRef CE (instanceRef xjtag_bus_uut_addr_28)) + (portRef CE (instanceRef xjtag_bus_uut_addr_29)) + (portRef CE (instanceRef xjtag_bus_uut_addr_30)) + (portRef CE (instanceRef xjtag_bus_uut_addr_31)) + (portRef CE (instanceRef xjtag_bus_uut_ishift_cnt_1)) + (portRef CE (instanceRef xjtag_bus_uut_ishift_cnt_2)) + (portRef CE (instanceRef xjtag_bus_uut_ishift_cnt_3)) + (portRef CE (instanceRef xjtag_bus_uut_ishift_cnt_4)) + (portRef CE (instanceRef xjtag_bus_uut_ishift_cnt_5)) + (portRef CE (instanceRef xjtag_bus_uut_ishift_cnt_6)) + (portRef CE (instanceRef xjtag_bus_uut_ishift_cnt_7)) + (portRef CE (instanceRef xjtag_bus_uut_ishift_cnt_0)) + (portRef O (instanceRef xjtag_bus_uut_dop_clk_r_2__dop_clk_r_1__AND_3_o1)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_0_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<0>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_0)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT110)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_1_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<1>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_1)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT121)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_2_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<2>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_2)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT231)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_3_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<3>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_3)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT281)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_4_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<4>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_4)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT291)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_5_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<5>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_5)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT301)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_6_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<6>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_6)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT311)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_7_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<7>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_7)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT321)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_8_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<8>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_8)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT331)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_9_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<9>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_9)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT341)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_10_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<10>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_10)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT210)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_11_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<11>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_11)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT35)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_12_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<12>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_12)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT41)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_13_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<13>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_13)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT51)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_14_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<14>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_14)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT61)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_15_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<15>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_15)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT71)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_16_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<16>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_16)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT81)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_17_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<17>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_17)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT91)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_18_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<18>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_18)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT101)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_19_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<19>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_19)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT111)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_20_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<20>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_20)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT131)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_21_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<21>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_21)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT141)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_22_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<22>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_22)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT151)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_23_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<23>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_23)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT161)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_24_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<24>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_24)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT171)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_25_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<25>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_25)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT181)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_26_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<26>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_26)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT191)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_27_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<27>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_27)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT201)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_28_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<28>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_28)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT211)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_29_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<29>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_29)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT221)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_30_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<30>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_30)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT241)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_31_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<31>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_31)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT251)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_32_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<32>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_32)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT261)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33__oshift_33__mux_91_OUT_33_ "xjtag_bus_uut/oshift[33]_oshift[33]_mux_91_OUT<33>") + (joined + (portRef D (instanceRef xjtag_bus_uut_oshift_33)) + (portRef O (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT271)) + ) + ) + (net (rename xjtag_bus_uut_dop1949 "xjtag_bus_uut/dop1949") + (joined + (portRef D (instanceRef xjtag_bus_uut_dop1949_r_0)) + (portRef O (instanceRef xjtag_bus_uut_bscan_xjtag_uut_DOP19491)) + ) + ) + (net (rename xjtag_bus_uut_dop_clk "xjtag_bus_uut/dop_clk") + (joined + (portRef D (instanceRef xjtag_bus_uut_dop_clk_r_0)) + (portRef O (instanceRef xjtag_bus_uut_bscan_xjtag_uut_CLK1)) + ) + ) + (net (rename xjtag_bus_uut_chip "xjtag_bus_uut/chip") + (joined + (portRef D (instanceRef xjtag_bus_uut_chip_r_0)) + (portRef O (instanceRef xjtag_bus_uut_bscan_xjtag_uut_Mmux_CS11)) + ) + ) + (net (rename xjtag_bus_uut_ird_valid_icmd_rd_1__AND_11_o "xjtag_bus_uut/ird_valid_icmd_rd[1]_AND_11_o") + (joined + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_0)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_1)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_2)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_3)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_4)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_5)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_6)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_7)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_8)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_9)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_10)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_11)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_12)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_13)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_14)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_15)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_16)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_17)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_18)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_19)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_20)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_21)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_22)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_23)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_24)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_25)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_26)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_27)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_28)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_29)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_30)) + (portRef CE (instanceRef xjtag_bus_uut_axi_raddr_31)) + (portRef O (instanceRef xjtag_bus_uut_ird_valid_icmd_rd_1__AND_11_o1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_cnt_0_ "xjtag_bus_uut/ishift_cnt<0>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_ishift_cnt_0)) + (portRef I3 (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_SW0)) + (portRef I2 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_renamed_13)) + (portRef I1 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_rstpot_renamed_48)) + (portRef I (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_lut_0__INV_0)) + (portRef I0 (instanceRef xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_cnt_1_ "xjtag_bus_uut/ishift_cnt<1>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_ishift_cnt_1)) + (portRef I2 (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_SW0)) + (portRef I0 (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_1__rt_renamed_34)) + (portRef I2 (instanceRef xjtag_bus_uut__n0231_inv1)) + (portRef I3 (instanceRef xjtag_bus_uut_ird_valid_rstpot_renamed_42)) + (portRef I3 (instanceRef xjtag_bus_uut__n0200_inv1_rstpot_renamed_43)) + (portRef I0 (instanceRef xjtag_bus_uut_dop1950_r_0_rstpot_SW0)) + (portRef I2 (instanceRef xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_cnt_2_ "xjtag_bus_uut/ishift_cnt<2>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_ishift_cnt_2)) + (portRef I4 (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_SW0)) + (portRef I0 (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_2__rt_renamed_33)) + (portRef I1 (instanceRef xjtag_bus_uut_ird_valid_rstpot_renamed_42)) + (portRef I4 (instanceRef xjtag_bus_uut__n0200_inv1_rstpot_renamed_43)) + (portRef I1 (instanceRef xjtag_bus_uut__n0231_inv1)) + (portRef I3 (instanceRef xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + (portRef I2 (instanceRef xjtag_bus_uut_dop1950_r_0_rstpot_renamed_45)) + ) + ) + (net (rename xjtag_bus_uut_ishift_cnt_3_ "xjtag_bus_uut/ishift_cnt<3>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_ishift_cnt_3)) + (portRef I0 (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_SW0)) + (portRef I4 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_renamed_13)) + (portRef I0 (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_3__rt_renamed_32)) + (portRef I3 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_rstpot_renamed_48)) + (portRef I1 (instanceRef xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_cnt_4_ "xjtag_bus_uut/ishift_cnt<4>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_ishift_cnt_4)) + (portRef I1 (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_SW0)) + (portRef I0 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_SW0)) + (portRef I0 (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_4__rt_renamed_31)) + (portRef I4 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_rstpot_renamed_48)) + ) + ) + (net (rename xjtag_bus_uut_ishift_cnt_5_ "xjtag_bus_uut/ishift_cnt<5>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_ishift_cnt_5)) + (portRef I4 (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_renamed_12)) + (portRef I0 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_renamed_13)) + (portRef I0 (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_5__rt_renamed_30)) + (portRef I0 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_SW1)) + (portRef CE (instanceRef xjtag_bus_uut_icmd_rd_0)) + (portRef CE (instanceRef xjtag_bus_uut_icmd_rd_1)) + ) + ) + (net (rename xjtag_bus_uut_ishift_cnt_6_ "xjtag_bus_uut/ishift_cnt<6>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_ishift_cnt_6)) + (portRef I2 (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_renamed_12)) + (portRef I1 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_SW0)) + (portRef I0 (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_6__rt_renamed_29)) + (portRef I5 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_rstpot_renamed_48)) + ) + ) + (net (rename xjtag_bus_uut_ishift_cnt_7_ "xjtag_bus_uut/ishift_cnt<7>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_ishift_cnt_7)) + (portRef I3 (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_renamed_12)) + (portRef I3 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_renamed_13)) + (portRef I0 (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_7__rt_renamed_35)) + (portRef I2 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_SW1)) + (portRef I2 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_rstpot_renamed_48)) + ) + ) + (net (rename xjtag_bus_uut_oshift_1_ "xjtag_bus_uut/oshift<1>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT110)) + ) + ) + (net (rename xjtag_bus_uut_oshift_2_ "xjtag_bus_uut/oshift<2>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_2)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT121)) + ) + ) + (net (rename xjtag_bus_uut_oshift_3_ "xjtag_bus_uut/oshift<3>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_3)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT231)) + ) + ) + (net (rename xjtag_bus_uut_oshift_4_ "xjtag_bus_uut/oshift<4>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_4)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT281)) + ) + ) + (net (rename xjtag_bus_uut_oshift_5_ "xjtag_bus_uut/oshift<5>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_5)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT291)) + ) + ) + (net (rename xjtag_bus_uut_oshift_6_ "xjtag_bus_uut/oshift<6>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_6)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT301)) + ) + ) + (net (rename xjtag_bus_uut_oshift_7_ "xjtag_bus_uut/oshift<7>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_7)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT311)) + ) + ) + (net (rename xjtag_bus_uut_oshift_8_ "xjtag_bus_uut/oshift<8>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_8)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT321)) + ) + ) + (net (rename xjtag_bus_uut_oshift_9_ "xjtag_bus_uut/oshift<9>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_9)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT331)) + ) + ) + (net (rename xjtag_bus_uut_oshift_10_ "xjtag_bus_uut/oshift<10>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_10)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT341)) + ) + ) + (net (rename xjtag_bus_uut_oshift_11_ "xjtag_bus_uut/oshift<11>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_11)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT210)) + ) + ) + (net (rename xjtag_bus_uut_oshift_12_ "xjtag_bus_uut/oshift<12>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_12)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT35)) + ) + ) + (net (rename xjtag_bus_uut_oshift_13_ "xjtag_bus_uut/oshift<13>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_13)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT41)) + ) + ) + (net (rename xjtag_bus_uut_oshift_14_ "xjtag_bus_uut/oshift<14>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_14)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT51)) + ) + ) + (net (rename xjtag_bus_uut_oshift_15_ "xjtag_bus_uut/oshift<15>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_15)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT61)) + ) + ) + (net (rename xjtag_bus_uut_oshift_16_ "xjtag_bus_uut/oshift<16>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_16)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT71)) + ) + ) + (net (rename xjtag_bus_uut_oshift_17_ "xjtag_bus_uut/oshift<17>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_17)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT81)) + ) + ) + (net (rename xjtag_bus_uut_oshift_18_ "xjtag_bus_uut/oshift<18>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_18)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT91)) + ) + ) + (net (rename xjtag_bus_uut_oshift_19_ "xjtag_bus_uut/oshift<19>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_19)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT101)) + ) + ) + (net (rename xjtag_bus_uut_oshift_20_ "xjtag_bus_uut/oshift<20>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_20)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT111)) + ) + ) + (net (rename xjtag_bus_uut_oshift_21_ "xjtag_bus_uut/oshift<21>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_21)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT131)) + ) + ) + (net (rename xjtag_bus_uut_oshift_22_ "xjtag_bus_uut/oshift<22>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_22)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT141)) + ) + ) + (net (rename xjtag_bus_uut_oshift_23_ "xjtag_bus_uut/oshift<23>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_23)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT151)) + ) + ) + (net (rename xjtag_bus_uut_oshift_24_ "xjtag_bus_uut/oshift<24>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_24)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT161)) + ) + ) + (net (rename xjtag_bus_uut_oshift_25_ "xjtag_bus_uut/oshift<25>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_25)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT171)) + ) + ) + (net (rename xjtag_bus_uut_oshift_26_ "xjtag_bus_uut/oshift<26>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_26)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT181)) + ) + ) + (net (rename xjtag_bus_uut_oshift_27_ "xjtag_bus_uut/oshift<27>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_27)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT191)) + ) + ) + (net (rename xjtag_bus_uut_oshift_28_ "xjtag_bus_uut/oshift<28>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_28)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT201)) + ) + ) + (net (rename xjtag_bus_uut_oshift_29_ "xjtag_bus_uut/oshift<29>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_29)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT211)) + ) + ) + (net (rename xjtag_bus_uut_oshift_30_ "xjtag_bus_uut/oshift<30>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_30)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT221)) + ) + ) + (net (rename xjtag_bus_uut_oshift_31_ "xjtag_bus_uut/oshift<31>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_31)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT241)) + ) + ) + (net (rename xjtag_bus_uut_oshift_32_ "xjtag_bus_uut/oshift<32>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_32)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT251)) + ) + ) + (net (rename xjtag_bus_uut_oshift_33_ "xjtag_bus_uut/oshift<33>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_33)) + (portRef I0 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT261)) + ) + ) + (net (rename xjtag_bus_uut_oshift_0_ "xjtag_bus_uut/oshift<0>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_oshift_0)) + (portRef I1 (instanceRef xjtag_bus_uut_dop1950_r_0_rstpot_renamed_45)) + ) + ) + (net (rename xjtag_bus_uut_dop1950_r_0 "xjtag_bus_uut/dop1950_r_0") + (joined + (portRef TDO (instanceRef xjtag_bus_uut_bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef Q (instanceRef xjtag_bus_uut_dop1950_r_0_renamed_44)) + (portRef I0 (instanceRef xjtag_bus_uut_dop1950_r_0_rstpot_renamed_45)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_0_ "xjtag_bus_uut/icrab_data<0>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_0)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_0_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_0_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_0_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT231)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_1_ "xjtag_bus_uut/icrab_data<1>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_1_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_1_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_1_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT281)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_2_ "xjtag_bus_uut/icrab_data<2>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_2)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_2_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_2_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_2_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT291)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_3_ "xjtag_bus_uut/icrab_data<3>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_3)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_3_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_3_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_3_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT301)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_4_ "xjtag_bus_uut/icrab_data<4>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_4)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_4_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_4_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_4_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT311)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_5_ "xjtag_bus_uut/icrab_data<5>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_5)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_5_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_5_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_5_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT321)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_6_ "xjtag_bus_uut/icrab_data<6>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_6)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_6_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_6_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_6_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT331)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_7_ "xjtag_bus_uut/icrab_data<7>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_7)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_7_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_7_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_7_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT341)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_8_ "xjtag_bus_uut/icrab_data<8>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_8)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_8_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_8_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_8_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT210)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_9_ "xjtag_bus_uut/icrab_data<9>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_9)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_9_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_9_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_9_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT35)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_10_ "xjtag_bus_uut/icrab_data<10>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_10)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_10_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_10_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_10_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT41)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_11_ "xjtag_bus_uut/icrab_data<11>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_11)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_11_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_11_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_11_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT51)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_12_ "xjtag_bus_uut/icrab_data<12>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_12)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_12_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_12_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_12_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT61)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_13_ "xjtag_bus_uut/icrab_data<13>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_13)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_13_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_13_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_13_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT71)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_14_ "xjtag_bus_uut/icrab_data<14>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_14)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_14_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_14_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_14_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT81)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_15_ "xjtag_bus_uut/icrab_data<15>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_15)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_15_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_15_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_15_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT91)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_16_ "xjtag_bus_uut/icrab_data<16>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_16)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_16_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_16_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_16_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT101)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_17_ "xjtag_bus_uut/icrab_data<17>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_17)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_17_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_17_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_17_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT111)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_18_ "xjtag_bus_uut/icrab_data<18>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_18)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_18_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_18_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_18_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT131)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_19_ "xjtag_bus_uut/icrab_data<19>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_19)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_19_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_19_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_19_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT141)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_20_ "xjtag_bus_uut/icrab_data<20>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_20)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_20_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_20_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_20_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT151)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_21_ "xjtag_bus_uut/icrab_data<21>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_21)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_21_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_21_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_21_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT161)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_22_ "xjtag_bus_uut/icrab_data<22>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_22)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_22_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_22_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_22_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT171)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_23_ "xjtag_bus_uut/icrab_data<23>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_23)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_23_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_23_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_23_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT181)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_24_ "xjtag_bus_uut/icrab_data<24>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_24)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_24_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_24_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_24_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT191)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_25_ "xjtag_bus_uut/icrab_data<25>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_25)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_25_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_25_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_25_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT201)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_26_ "xjtag_bus_uut/icrab_data<26>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_26)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_26_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_26_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_26_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT211)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_27_ "xjtag_bus_uut/icrab_data<27>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_27)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_27_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_27_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_27_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT221)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_28_ "xjtag_bus_uut/icrab_data<28>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_28)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_28_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_28_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_28_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT241)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_29_ "xjtag_bus_uut/icrab_data<29>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_29)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_29_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_29_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_29_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT251)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_30_ "xjtag_bus_uut/icrab_data<30>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_30)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_30_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_30_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_30_xo_0_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT261)) + ) + ) + (net (rename xjtag_bus_uut_icrab_data_31_ "xjtag_bus_uut/icrab_data<31>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icrab_data_31)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_31_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_31_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_31_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT271)) + ) + ) + (net (rename xjtag_bus_uut_wdata_1_ "xjtag_bus_uut/wdata<1>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_0)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_1)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_1_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_3_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_2_ "xjtag_bus_uut/wdata<2>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_1)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_2)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_2)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_2_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_4_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_3_ "xjtag_bus_uut/wdata<3>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_2)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_3)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_3)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_3_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_5_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_4_ "xjtag_bus_uut/wdata<4>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_3)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_4)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_4)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_4_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_6_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_5_ "xjtag_bus_uut/wdata<5>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_4)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_5)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_5)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_5_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_7_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_6_ "xjtag_bus_uut/wdata<6>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_5)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_6)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_6)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_6_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_8_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_7_ "xjtag_bus_uut/wdata<7>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_6)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_7)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_7)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_7_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_9_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_8_ "xjtag_bus_uut/wdata<8>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_7)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_8)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_8)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_8_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_10_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_9_ "xjtag_bus_uut/wdata<9>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_8)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_9)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_9)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_9_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_11_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_10_ "xjtag_bus_uut/wdata<10>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_9)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_10)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_10)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_10_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_12_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_11_ "xjtag_bus_uut/wdata<11>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_10)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_11)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_11)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_11_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_13_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_12_ "xjtag_bus_uut/wdata<12>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_11)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_12)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_12)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_12_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_14_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_13_ "xjtag_bus_uut/wdata<13>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_12)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_13)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_13)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_13_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_15_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_14_ "xjtag_bus_uut/wdata<14>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_13)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_14)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_14)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_14_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_16_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_15_ "xjtag_bus_uut/wdata<15>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_14)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_15)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_15)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_15_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_17_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_16_ "xjtag_bus_uut/wdata<16>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_15)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_16)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_16)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_16_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_18_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_17_ "xjtag_bus_uut/wdata<17>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_16)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_17)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_17)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_17_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_19_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_18_ "xjtag_bus_uut/wdata<18>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_17)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_18)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_18)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_18_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_20_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_19_ "xjtag_bus_uut/wdata<19>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_18)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_19)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_19)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_19_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_21_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_20_ "xjtag_bus_uut/wdata<20>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_19)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_20)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_20)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_20_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_22_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_21_ "xjtag_bus_uut/wdata<21>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_20)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_21)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_21)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_21_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_23_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_22_ "xjtag_bus_uut/wdata<22>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_21)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_22)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_22)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_22_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_24_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_23_ "xjtag_bus_uut/wdata<23>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_22)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_23)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_23)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_23_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_25_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_24_ "xjtag_bus_uut/wdata<24>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_23)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_24)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_24)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_24_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_26_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_25_ "xjtag_bus_uut/wdata<25>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_24)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_25)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_25)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_25_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_27_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_26_ "xjtag_bus_uut/wdata<26>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_25)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_26)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_26)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_26_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_28_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_27_ "xjtag_bus_uut/wdata<27>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_26)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_27)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_27)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_27_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_29_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_28_ "xjtag_bus_uut/wdata<28>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_27)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_28)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_28)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_28_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_30_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_29_ "xjtag_bus_uut/wdata<29>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_28)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_29)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_29)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_29_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_31_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_wdata_30_ "xjtag_bus_uut/wdata<30>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_29)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_30)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_30)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_30_xo_0_1)) + (portRef I0 (instanceRef xjtag_bus_uut_ishift_data_71__PWR_2_o_equal_69_o_31_1)) + (portRef I3 (instanceRef xjtag_bus_uut_icmd_rd_0_dpot1_renamed_46)) + (portRef I2 (instanceRef xjtag_bus_uut_axi_rvalid_rstpot_renamed_54)) + ) + ) + (net (rename xjtag_bus_uut_wdata_31_ "xjtag_bus_uut/wdata<31>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_30)) + (portRef Q (instanceRef xjtag_bus_uut_wdata_31)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_31)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_31_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_ishift_data_71__PWR_2_o_equal_69_o_31_1)) + (portRef I3 (instanceRef xjtag_bus_uut_icmd_rd_1_dpot1_renamed_47)) + (portRef I3 (instanceRef xjtag_bus_uut_axi_rvalid_rstpot_renamed_54)) + ) + ) + (net (rename xjtag_bus_uut_wdata_0_ "xjtag_bus_uut/wdata<0>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_wdata_0)) + (portRef D (instanceRef xjtag_bus_uut_cmd_7)) + (portRef D (instanceRef xjtag_bus_uut_icrab_data_0)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_wdata_31__icrab_data_31__xor_42_OUT_0_xo_0_1)) + (portRef I1 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_2_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_cmd_1_ "xjtag_bus_uut/cmd<1>") + (joined + (portRef D (instanceRef xjtag_bus_uut_cmd_0)) + (portRef Q (instanceRef xjtag_bus_uut_cmd_1)) + (portRef I2 (instanceRef xjtag_bus_uut__n0211_inv1)) + (portRef I1 (instanceRef xjtag_bus_uut__n0207_inv1)) + (portRef I0 (instanceRef xjtag_bus_uut__n0216_inv1)) + (portRef I3 (instanceRef xjtag_bus_uut_iwr_valid_rstpot_renamed_53)) + (portRef I2 (instanceRef xjtag_bus_uut_axi_wvalid_rstpot_renamed_63)) + ) + ) + (net (rename xjtag_bus_uut_cmd_2_ "xjtag_bus_uut/cmd<2>") + (joined + (portRef D (instanceRef xjtag_bus_uut_cmd_1)) + (portRef Q (instanceRef xjtag_bus_uut_cmd_2)) + ) + ) + (net (rename xjtag_bus_uut_cmd_3_ "xjtag_bus_uut/cmd<3>") + (joined + (portRef D (instanceRef xjtag_bus_uut_cmd_2)) + (portRef Q (instanceRef xjtag_bus_uut_cmd_3)) + ) + ) + (net (rename xjtag_bus_uut_cmd_0_ "xjtag_bus_uut/cmd<0>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_cmd_0)) + (portRef D (instanceRef xjtag_bus_uut_addr_31)) + (portRef I1 (instanceRef xjtag_bus_uut__n0211_inv1)) + (portRef I2 (instanceRef xjtag_bus_uut__n0207_inv1)) + (portRef I1 (instanceRef xjtag_bus_uut__n0216_inv1)) + (portRef I0 (instanceRef xjtag_bus_uut_axi_wvalid_rstpot_renamed_63)) + ) + ) + (net (rename xjtag_bus_uut_cmd_4_ "xjtag_bus_uut/cmd<4>") + (joined + (portRef D (instanceRef xjtag_bus_uut_cmd_3)) + (portRef Q (instanceRef xjtag_bus_uut_cmd_4)) + (portRef D (instanceRef xjtag_bus_uut_axi_wmask_0)) + ) + ) + (net (rename xjtag_bus_uut_cmd_5_ "xjtag_bus_uut/cmd<5>") + (joined + (portRef D (instanceRef xjtag_bus_uut_cmd_4)) + (portRef Q (instanceRef xjtag_bus_uut_cmd_5)) + (portRef D (instanceRef xjtag_bus_uut_axi_wmask_1)) + ) + ) + (net (rename xjtag_bus_uut_cmd_6_ "xjtag_bus_uut/cmd<6>") + (joined + (portRef D (instanceRef xjtag_bus_uut_cmd_5)) + (portRef Q (instanceRef xjtag_bus_uut_cmd_6)) + (portRef D (instanceRef xjtag_bus_uut_axi_wmask_2)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_0_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_cmd_7_ "xjtag_bus_uut/cmd<7>") + (joined + (portRef D (instanceRef xjtag_bus_uut_cmd_6)) + (portRef Q (instanceRef xjtag_bus_uut_cmd_7)) + (portRef D (instanceRef xjtag_bus_uut_axi_wmask_3)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_ishift_data_69__icrab_data_31__xor_72_OUT_1_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_0_ "xjtag_bus_uut/addr<0>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_addr_0)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_0_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_1_ "xjtag_bus_uut/addr<1>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_0)) + (portRef Q (instanceRef xjtag_bus_uut_addr_1)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_1_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_2_ "xjtag_bus_uut/addr<2>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_1)) + (portRef Q (instanceRef xjtag_bus_uut_addr_2)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_2_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_3_ "xjtag_bus_uut/addr<3>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_2)) + (portRef Q (instanceRef xjtag_bus_uut_addr_3)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_3_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_4_ "xjtag_bus_uut/addr<4>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_3)) + (portRef Q (instanceRef xjtag_bus_uut_addr_4)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_4_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_5_ "xjtag_bus_uut/addr<5>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_4)) + (portRef Q (instanceRef xjtag_bus_uut_addr_5)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_5_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_6_ "xjtag_bus_uut/addr<6>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_5)) + (portRef Q (instanceRef xjtag_bus_uut_addr_6)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_6_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_7_ "xjtag_bus_uut/addr<7>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_6)) + (portRef Q (instanceRef xjtag_bus_uut_addr_7)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_7_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_8_ "xjtag_bus_uut/addr<8>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_7)) + (portRef Q (instanceRef xjtag_bus_uut_addr_8)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_8_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_9_ "xjtag_bus_uut/addr<9>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_8)) + (portRef Q (instanceRef xjtag_bus_uut_addr_9)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_9_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_10_ "xjtag_bus_uut/addr<10>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_9)) + (portRef Q (instanceRef xjtag_bus_uut_addr_10)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_10_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_11_ "xjtag_bus_uut/addr<11>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_10)) + (portRef Q (instanceRef xjtag_bus_uut_addr_11)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_11_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_12_ "xjtag_bus_uut/addr<12>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_11)) + (portRef Q (instanceRef xjtag_bus_uut_addr_12)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_12_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_13_ "xjtag_bus_uut/addr<13>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_12)) + (portRef Q (instanceRef xjtag_bus_uut_addr_13)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_13_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_14_ "xjtag_bus_uut/addr<14>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_13)) + (portRef Q (instanceRef xjtag_bus_uut_addr_14)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_14_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_15_ "xjtag_bus_uut/addr<15>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_14)) + (portRef Q (instanceRef xjtag_bus_uut_addr_15)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_15_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_16_ "xjtag_bus_uut/addr<16>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_15)) + (portRef Q (instanceRef xjtag_bus_uut_addr_16)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_16_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_17_ "xjtag_bus_uut/addr<17>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_16)) + (portRef Q (instanceRef xjtag_bus_uut_addr_17)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_17_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_18_ "xjtag_bus_uut/addr<18>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_17)) + (portRef Q (instanceRef xjtag_bus_uut_addr_18)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_18_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_19_ "xjtag_bus_uut/addr<19>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_18)) + (portRef Q (instanceRef xjtag_bus_uut_addr_19)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_19_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_20_ "xjtag_bus_uut/addr<20>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_19)) + (portRef Q (instanceRef xjtag_bus_uut_addr_20)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_20_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_21_ "xjtag_bus_uut/addr<21>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_20)) + (portRef Q (instanceRef xjtag_bus_uut_addr_21)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_21_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_22_ "xjtag_bus_uut/addr<22>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_21)) + (portRef Q (instanceRef xjtag_bus_uut_addr_22)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_22_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_23_ "xjtag_bus_uut/addr<23>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_22)) + (portRef Q (instanceRef xjtag_bus_uut_addr_23)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_23_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_24_ "xjtag_bus_uut/addr<24>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_23)) + (portRef Q (instanceRef xjtag_bus_uut_addr_24)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_24_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_25_ "xjtag_bus_uut/addr<25>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_24)) + (portRef Q (instanceRef xjtag_bus_uut_addr_25)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_25_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_26_ "xjtag_bus_uut/addr<26>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_25)) + (portRef Q (instanceRef xjtag_bus_uut_addr_26)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_26_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_27_ "xjtag_bus_uut/addr<27>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_26)) + (portRef Q (instanceRef xjtag_bus_uut_addr_27)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_27_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_28_ "xjtag_bus_uut/addr<28>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_27)) + (portRef Q (instanceRef xjtag_bus_uut_addr_28)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_28_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_29_ "xjtag_bus_uut/addr<29>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_28)) + (portRef Q (instanceRef xjtag_bus_uut_addr_29)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_29_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_30_ "xjtag_bus_uut/addr<30>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_29)) + (portRef Q (instanceRef xjtag_bus_uut_addr_30)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_30_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_addr_31_ "xjtag_bus_uut/addr<31>") + (joined + (portRef D (instanceRef xjtag_bus_uut_addr_30)) + (portRef Q (instanceRef xjtag_bus_uut_addr_31)) + (portRef I0 (instanceRef xjtag_bus_uut_Mxor_addr_31__icrab_data_31__xor_39_OUT_31_xo_0_1)) + ) + ) + (net (rename xjtag_bus_uut_icmd_rd_0_ "xjtag_bus_uut/icmd_rd<0>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icmd_rd_0)) + (portRef I1 (instanceRef xjtag_bus_uut_ird_valid_icmd_rd_1__AND_11_o1)) + (portRef I0 (instanceRef xjtag_bus_uut_icmd_rd_0_dpot1_renamed_46)) + (portRef I0 (instanceRef xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o1_SW0)) + ) + ) + (net (rename xjtag_bus_uut_icmd_rd_1_ "xjtag_bus_uut/icmd_rd<1>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_icmd_rd_1)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT110)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT121)) + (portRef I0 (instanceRef xjtag_bus_uut_ird_valid_icmd_rd_1__AND_11_o1)) + (portRef I0 (instanceRef xjtag_bus_uut_icmd_rd_1_dpot1_renamed_47)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT210)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT35)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT41)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT51)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT61)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT71)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT81)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT91)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT101)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT111)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT131)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT141)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT151)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT161)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT171)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT181)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT191)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT201)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT211)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT221)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT241)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT251)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT261)) + (portRef I2 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT271)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT281)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT291)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT301)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT311)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT321)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT331)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT341)) + (portRef I3 (instanceRef xjtag_bus_uut_Mmux_oshift_33__oshift_33__mux_91_OUT231)) + (portRef I1 (instanceRef xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o1_SW0)) + ) + ) + (net (rename xjtag_bus_uut_ird_valid "xjtag_bus_uut/ird_valid") + (joined + (portRef I2 (instanceRef xjtag_bus_uut_ird_valid_icmd_rd_1__AND_11_o1)) + (portRef Q (instanceRef xjtag_bus_uut_ird_valid_renamed_39)) + (portRef I1 (instanceRef xjtag_bus_uut_axi_rvalid_rstpot_renamed_54)) + ) + ) + (net (rename xjtag_bus_uut_iwr_valid "xjtag_bus_uut/iwr_valid") + (joined + (portRef CE (instanceRef xjtag_bus_uut_axi_wmask_0)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wmask_1)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wmask_2)) + (portRef CE (instanceRef xjtag_bus_uut_axi_wmask_3)) + (portRef I0 (instanceRef xjtag_bus_uut__n0211_inv1)) + (portRef I0 (instanceRef xjtag_bus_uut__n0207_inv1)) + (portRef I2 (instanceRef xjtag_bus_uut__n0216_inv1)) + (portRef Q (instanceRef xjtag_bus_uut_iwr_valid_renamed_38)) + (portRef I3 (instanceRef xjtag_bus_uut_axi_wvalid_rstpot_renamed_63)) + ) + ) + (net (rename xjtag_bus_uut_chip_r_2_ "xjtag_bus_uut/chip_r<2>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_chip_r_2)) + (portRef I0 (instanceRef xjtag_bus_uut_iwr_valid_rstpot_renamed_53)) + ) + ) + (net (rename xjtag_bus_uut_chip_r_0_ "xjtag_bus_uut/chip_r<0>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_chip_r_0)) + (portRef D (instanceRef xjtag_bus_uut_chip_r_1)) + ) + ) + (net (rename xjtag_bus_uut_chip_r_1_ "xjtag_bus_uut/chip_r<1>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_chip_r_1)) + (portRef D (instanceRef xjtag_bus_uut_chip_r_2)) + (portRef I0 (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_val1)) + (portRef I1 (instanceRef xjtag_bus_uut__n0200_inv1_rstpot_renamed_43)) + (portRef I1 (instanceRef xjtag_bus_uut_iwr_valid_rstpot_renamed_53)) + ) + ) + (net (rename xjtag_bus_uut_dop_clk_r_3_ "xjtag_bus_uut/dop_clk_r<3>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_dop_clk_r_3)) + (portRef I2 (instanceRef xjtag_bus_uut_ird_valid_rstpot_renamed_42)) + (portRef I2 (instanceRef xjtag_bus_uut__n0200_inv1_rstpot_renamed_43)) + ) + ) + (net (rename xjtag_bus_uut_dop_clk_r_0_ "xjtag_bus_uut/dop_clk_r<0>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_dop_clk_r_0)) + (portRef D (instanceRef xjtag_bus_uut_dop_clk_r_1)) + ) + ) + (net (rename xjtag_bus_uut_dop_clk_r_1_ "xjtag_bus_uut/dop_clk_r<1>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_dop_clk_r_1)) + (portRef D (instanceRef xjtag_bus_uut_dop_clk_r_2)) + (portRef I1 (instanceRef xjtag_bus_uut_dop_clk_r_2__dop_clk_r_1__AND_3_o1)) + (portRef I1 (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_renamed_12)) + (portRef I3 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_SW1)) + (portRef I1 (instanceRef xjtag_bus_uut_dop1950_r_0_rstpot_SW0)) + (portRef I0 (instanceRef xjtag_bus_uut__n0231_inv1)) + ) + ) + (net (rename xjtag_bus_uut_dop_clk_r_2_ "xjtag_bus_uut/dop_clk_r<2>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_dop_clk_r_2)) + (portRef D (instanceRef xjtag_bus_uut_dop_clk_r_3)) + (portRef I0 (instanceRef xjtag_bus_uut_dop_clk_r_2__dop_clk_r_1__AND_3_o1)) + (portRef I0 (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_renamed_12)) + (portRef I1 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_renamed_13)) + (portRef I1 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_SW1)) + (portRef I0 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_rstpot_renamed_48)) + ) + ) + (net (rename xjtag_bus_uut_dop1949_r_0_ "xjtag_bus_uut/dop1949_r<0>") + (joined + (portRef Q (instanceRef xjtag_bus_uut_dop1949_r_0)) + (portRef D (instanceRef xjtag_bus_uut_dop1949_r_1)) + ) + ) + (net (rename xjtag_bus_uut_dop1949_r_1_ "xjtag_bus_uut/dop1949_r<1>") + (joined + (portRef D (instanceRef xjtag_bus_uut_wdata_31)) + (portRef Q (instanceRef xjtag_bus_uut_dop1949_r_1)) + ) + ) + (net N2 + (joined + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0284_SW0)) + (portRef I5 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0284_renamed_10)) + ) + ) + (net N4 + (joined + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_SW0)) + (portRef I5 (instanceRef xjtag_axi_v1_0_M00_AXI_inst__n0276_renamed_11)) + ) + ) + (net N6 + (joined + (portRef O (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_SW0)) + (portRef I5 (instanceRef xjtag_bus_uut_dop_clk_r_2__GND_2_o_AND_15_o_renamed_12)) + ) + ) + (net N8 + (joined + (portRef O (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_SW0)) + (portRef I5 (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_renamed_13)) + (portRef I4 (instanceRef xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_arvalid_glue_set "xjtag_axi_v1_0_M00_AXI_inst/axi_arvalid_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_arvalid_renamed_14)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_arvalid_glue_set_renamed_66)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_wvalid_glue_set "xjtag_axi_v1_0_M00_AXI_inst/axi_wvalid_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wvalid_renamed_15)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_wvalid_glue_set_renamed_57)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_awvalid_glue_set "xjtag_axi_v1_0_M00_AXI_inst/axi_awvalid_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awvalid_renamed_16)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_awvalid_glue_set_renamed_58)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_issued_glue_set "xjtag_axi_v1_0_M00_AXI_inst/read_issued_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_issued_renamed_17)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_issued_glue_set_renamed_49)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_write_issued_glue_set "xjtag_axi_v1_0_M00_AXI_inst/write_issued_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_issued_renamed_18)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_issued_glue_set_renamed_50)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_start_single_write_glue_set "xjtag_axi_v1_0_M00_AXI_inst/start_single_write_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_write_renamed_19)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_write_glue_set_renamed_51)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_start_single_read_glue_set "xjtag_axi_v1_0_M00_AXI_inst/start_single_read_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_read_renamed_20)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_start_single_read_glue_set_renamed_52)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_rready_glue_set "xjtag_axi_v1_0_M00_AXI_inst/axi_rready_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_rready_renamed_21)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_M_AXI_RVALID_axi_rready_AND_30_o1)) + ) + ) + (net (rename m00_axi_arprot_1_ "m00_axi_arprot<1>") + (joined + (portRef G (instanceRef XST_GND)) + (portRef (member m00_axi_arprot 1)) + (portRef (member m00_axi_arprot 0)) + (portRef (member m00_axi_awprot 2)) + (portRef (member m00_axi_awprot 1)) + (portRef (member m00_axi_awprot 0)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_0__)) + (portRef CI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_0__)) + (portRef DI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_1__)) + (portRef DI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_2__)) + (portRef DI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_3__)) + (portRef DI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_4__)) + (portRef DI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_5__)) + (portRef DI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_6__)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_axi_bready_glue_set "xjtag_axi_v1_0_M00_AXI_inst/axi_bready_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_axi_bready_renamed_22)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_M_AXI_BVALID_axi_bready_AND_22_o1)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_ifinish_glue_set "xjtag_axi_v1_0_M00_AXI_inst/ifinish_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_ifinish_renamed_23)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_ifinish_glue_set_renamed_65)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_iwr_rd_glue_set "xjtag_axi_v1_0_M00_AXI_inst/iwr_rd_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iwr_rd_renamed_24)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_iwr_rd_glue_set_renamed_64)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_reads_done_glue_set "xjtag_axi_v1_0_M00_AXI_inst/reads_done_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_reads_done_renamed_25)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_reads_done_glue_set_renamed_59)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_last_read_glue_set "xjtag_axi_v1_0_M00_AXI_inst/last_read_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_read_renamed_26)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_read_glue_set_renamed_60)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_writes_done_glue_set "xjtag_axi_v1_0_M00_AXI_inst/writes_done_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_writes_done_renamed_27)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_writes_done_glue_set_renamed_61)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_last_write_glue_set "xjtag_axi_v1_0_M00_AXI_inst/last_write_glue_set") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_write_renamed_28)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_last_write_glue_set_renamed_62)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_6__rt "xjtag_bus_uut/Mcount_ishift_cnt_cy<6>_rt") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_6__rt_renamed_29)) + (portRef S (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_6__)) + (portRef LI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_6__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_5__rt "xjtag_bus_uut/Mcount_ishift_cnt_cy<5>_rt") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_5__rt_renamed_30)) + (portRef S (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_5__)) + (portRef LI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_5__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_4__rt "xjtag_bus_uut/Mcount_ishift_cnt_cy<4>_rt") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_4__rt_renamed_31)) + (portRef S (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_4__)) + (portRef LI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_4__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_3__rt "xjtag_bus_uut/Mcount_ishift_cnt_cy<3>_rt") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_3__rt_renamed_32)) + (portRef S (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_3__)) + (portRef LI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_3__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_2__rt "xjtag_bus_uut/Mcount_ishift_cnt_cy<2>_rt") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_2__rt_renamed_33)) + (portRef S (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_2__)) + (portRef LI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_2__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_cy_1__rt "xjtag_bus_uut/Mcount_ishift_cnt_cy<1>_rt") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_1__rt_renamed_34)) + (portRef S (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_cy_1__)) + (portRef LI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_1__)) + ) + ) + (net (rename xjtag_bus_uut_Mcount_ishift_cnt_xor_7__rt "xjtag_bus_uut/Mcount_ishift_cnt_xor<7>_rt") + (joined + (portRef O (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_7__rt_renamed_35)) + (portRef LI (instanceRef xjtag_bus_uut_Mcount_ishift_cnt_xor_7__)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_write_index_0_rstpot "xjtag_axi_v1_0_M00_AXI_inst/write_index_0_rstpot") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_index_0_renamed_36)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_write_index_0_rstpot_renamed_55)) + ) + ) + (net (rename xjtag_axi_v1_0_M00_AXI_inst_read_index_0_rstpot "xjtag_axi_v1_0_M00_AXI_inst/read_index_0_rstpot") + (joined + (portRef D (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_index_0_renamed_37)) + (portRef O (instanceRef xjtag_axi_v1_0_M00_AXI_inst_read_index_0_rstpot_renamed_56)) + ) + ) + (net (rename xjtag_bus_uut_iwr_valid_rstpot "xjtag_bus_uut/iwr_valid_rstpot") + (joined + (portRef D (instanceRef xjtag_bus_uut_iwr_valid_renamed_38)) + (portRef O (instanceRef xjtag_bus_uut_iwr_valid_rstpot_renamed_53)) + ) + ) + (net (rename xjtag_bus_uut_ird_valid_rstpot "xjtag_bus_uut/ird_valid_rstpot") + (joined + (portRef D (instanceRef xjtag_bus_uut_ird_valid_renamed_39)) + (portRef O (instanceRef xjtag_bus_uut_ird_valid_rstpot_renamed_42)) + ) + ) + (net (rename xjtag_bus_uut_axi_rvalid_rstpot "xjtag_bus_uut/axi_rvalid_rstpot") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_rvalid_renamed_40)) + (portRef O (instanceRef xjtag_bus_uut_axi_rvalid_rstpot_renamed_54)) + ) + ) + (net (rename xjtag_bus_uut_axi_wvalid_rstpot "xjtag_bus_uut/axi_wvalid_rstpot") + (joined + (portRef D (instanceRef xjtag_bus_uut_axi_wvalid_renamed_41)) + (portRef O (instanceRef xjtag_bus_uut_axi_wvalid_rstpot_renamed_63)) + ) + ) + (net N10 + (joined + (portRef O (instanceRef xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o1_SW0)) + (portRef I3 (instanceRef xjtag_bus_uut__n0231_inv1)) + ) + ) + (net N14 + (joined + (portRef O (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_SW1)) + (portRef I5 (instanceRef xjtag_bus_uut_dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + ) + ) + (net (rename xjtag_bus_uut__n0200_inv1_rstpot "xjtag_bus_uut/_n0200_inv1_rstpot") + (joined + (portRef O (instanceRef xjtag_bus_uut__n0200_inv1_rstpot_renamed_43)) + (portRef I2 (instanceRef xjtag_bus_uut_icmd_rd_0_dpot1_renamed_46)) + (portRef I2 (instanceRef xjtag_bus_uut_icmd_rd_1_dpot1_renamed_47)) + ) + ) + (net (rename xjtag_bus_uut_dop1950_r_0_rstpot "xjtag_bus_uut/dop1950_r_0_rstpot") + (joined + (portRef D (instanceRef xjtag_bus_uut_dop1950_r_0_renamed_44)) + (portRef O (instanceRef xjtag_bus_uut_dop1950_r_0_rstpot_renamed_45)) + ) + ) + (net N16 + (joined + (portRef O (instanceRef xjtag_bus_uut_dop1950_r_0_rstpot_SW0)) + (portRef I3 (instanceRef xjtag_bus_uut_dop1950_r_0_rstpot_renamed_45)) + ) + ) + (net (rename xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_rstpot "xjtag_bus_uut/chip_r[1]_ishift_cnt[7]_AND_9_o1_rstpot") + (joined + (portRef I1 (instanceRef xjtag_bus_uut_icmd_rd_0_dpot1_renamed_46)) + (portRef I1 (instanceRef xjtag_bus_uut_icmd_rd_1_dpot1_renamed_47)) + (portRef O (instanceRef xjtag_bus_uut_chip_r_1__ishift_cnt_7__AND_9_o1_rstpot_renamed_48)) + ) + ) + (net (rename xjtag_bus_uut_icmd_rd_0_dpot1 "xjtag_bus_uut/icmd_rd_0_dpot1") + (joined + (portRef D (instanceRef xjtag_bus_uut_icmd_rd_0)) + (portRef O (instanceRef xjtag_bus_uut_icmd_rd_0_dpot1_renamed_46)) + ) + ) + (net (rename xjtag_bus_uut_icmd_rd_1_dpot1 "xjtag_bus_uut/icmd_rd_1_dpot1") + (joined + (portRef D (instanceRef xjtag_bus_uut_icmd_rd_1)) + (portRef O (instanceRef xjtag_bus_uut_icmd_rd_1_dpot1_renamed_47)) + ) + ) + ) + ) + ) + ) + + (design xjtag_axi + (cellRef xjtag_axi + (libraryRef xjtag_axi_lib) + ) + (property PART (string "xc7k70t-2-fbg676") (owner "Xilinx")) + ) +) + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.vivado.begin.rst b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..2b6ea82 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.vivado.end.rst b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/ISEWrap.js b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000..898ddd7 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/ISEWrap.sh b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/__synthesis_is_complete__ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/dont_touch.xdc b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/dont_touch.xdc new file mode 100644 index 0000000..14e0936 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/dont_touch.xdc @@ -0,0 +1,23 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# XDC: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc + +# Block Designs: bd/design_1/design_1.bd +set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==design_1 || ORIG_REF_NAME==design_1} -quiet] -quiet + +# IP: bd/design_1/ip/design_1_xjtag_axi_0_0/design_1_xjtag_axi_0_0.xci +set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==design_1_xjtag_axi_0_0 || ORIG_REF_NAME==design_1_xjtag_axi_0_0} -quiet] -quiet + +# IP: bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xci +set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==design_1_axi_gpio_0_0 || ORIG_REF_NAME==design_1_axi_gpio_0_0} -quiet] -quiet + +# XDC: bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc +set_property DONT_TOUCH TRUE [get_cells [split [join [get_cells -hier -filter {REF_NAME==design_1_axi_gpio_0_0 || ORIG_REF_NAME==design_1_axi_gpio_0_0} -quiet] {/U0 } ]/U0 ] -quiet] -quiet + +# XDC: bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_ooc.xdc + +# XDC: bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc +#dup# set_property DONT_TOUCH TRUE [get_cells [split [join [get_cells -hier -filter {REF_NAME==design_1_axi_gpio_0_0 || ORIG_REF_NAME==design_1_axi_gpio_0_0} -quiet] {/U0 } ]/U0 ] -quiet] -quiet + +# XDC: bd/design_1/design_1_ooc.xdc diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/gen_run.xml b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..a5475cb --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/gen_run.xml @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/htr.txt b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/htr.txt new file mode 100644 index 0000000..2e3b15a --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log t160_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/planAhead.ngc2edif.log b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/planAhead.ngc2edif.log new file mode 100644 index 0000000..87ef309 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/planAhead.ngc2edif.log @@ -0,0 +1,11 @@ +Release 14.7 - ngc2edif P_INT.20180321 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design xjtag_axi.ngc ... +WARNING:NetListWriters:298 - No output is written to xjtag_axi.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file xjtag_axi.edif ... +ngc2edif: Total memory usage is 89640 kilobytes + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/rundef.js b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/rundef.js new file mode 100644 index 0000000..3d60bce --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;"; +} else { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log t160_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/runme.bat b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/runme.bat new file mode 100644 index 0000000..73c8b46 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/runme.log b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/runme.log new file mode 100644 index 0000000..2d7550a --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/runme.log @@ -0,0 +1,1046 @@ + +*** Running vivado + with args -log t160_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source t160_top.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Xilinx/xjtag/xjtag_ip/axi_bus_ip'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2018.2/data/ip'. +Command: synth_design -top t160_top -part xc7k160tffg676-2 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 7432 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 399.355 ; gain = 97.930 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 't160_top' [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.v:1] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.Xil/Vivado-8184-PC2018/realtime/clk_wiz_0_stub.v:5] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (1#1) [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.Xil/Vivado-8184-PC2018/realtime/clk_wiz_0_stub.v:5] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (2#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/imports/hdl/design_1_wrapper.v:12] +INFO: [Synth 8-6157] synthesizing module 'design_1' [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.v:13] +INFO: [Synth 8-638] synthesizing module 'design_1_axi_gpio_0_0' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:86] + Parameter C_FAMILY bound to: kintex7 - type: string + Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer + Parameter C_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_GPIO2_WIDTH bound to: 32 - type: integer + Parameter C_ALL_INPUTS bound to: 0 - type: integer + Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer + Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000000000000000000000 + Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111 + Parameter C_IS_DUAL bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000 + Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111 +INFO: [Synth 8-3491] module 'axi_gpio' declared at 'd:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1265' bound to instance 'U0' of component 'axi_gpio' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:172] +INFO: [Synth 8-638] synthesizing module 'axi_gpio' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1358] + Parameter C_FAMILY bound to: kintex7 - type: string + Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer + Parameter C_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_GPIO2_WIDTH bound to: 32 - type: integer + Parameter C_ALL_INPUTS bound to: 0 - type: integer + Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer + Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT bound to: 0 - type: integer + Parameter C_TRI_DEFAULT bound to: -1 - type: integer + Parameter C_IS_DUAL bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer + Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer +INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1295] +INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1296] +INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] + Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer + Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111 + Parameter C_USE_WSTRB bound to: 0 - type: integer + Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer + Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 + Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 + Parameter C_FAMILY bound to: kintex7 - type: string +INFO: [Synth 8-638] synthesizing module 'slave_attachment' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] + Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 + Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 + Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer + Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer + Parameter C_USE_WSTRB bound to: 0 - type: integer + Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer + Parameter C_FAMILY bound to: kintex7 - type: string +INFO: [Synth 8-638] synthesizing module 'address_decoder' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] + Parameter C_BUS_AWIDTH bound to: 9 - type: integer + Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer + Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 + Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-638] synthesizing module 'pselect_f' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b00 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f' (3#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b01 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (3#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b10 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (3#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b11 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (3#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-256] done synthesizing module 'address_decoder' (4#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] +INFO: [Synth 8-226] default block is never used [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] +INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (5#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] +INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (6#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] +INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:178] + Parameter C_DW bound to: 32 - type: integer + Parameter C_AW bound to: 9 - type: integer + Parameter C_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_GPIO2_WIDTH bound to: 32 - type: integer + Parameter C_MAX_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT bound to: 0 - type: integer + Parameter C_TRI_DEFAULT bound to: -1 - type: integer + Parameter C_IS_DUAL bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer + Parameter C_ALL_INPUTS bound to: 0 - type: integer + Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer + Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer + Parameter C_FAMILY bound to: kintex7 - type: string +INFO: [Synth 8-226] default block is never used [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:443] +INFO: [Synth 8-638] synthesizing module 'cdc_sync' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] + Parameter C_CDC_TYPE bound to: 1 - type: integer + Parameter C_RESET_STATE bound to: 0 - type: integer + Parameter C_SINGLE_BIT bound to: 0 - type: integer + Parameter C_FLOP_INPUT bound to: 0 - type: integer + Parameter C_VECTOR_WIDTH bound to: 32 - type: integer + Parameter C_MTBF_STAGES bound to: 4 - type: integer + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] +INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (7#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (8#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:178] +INFO: [Synth 8-256] done synthesizing module 'axi_gpio' (9#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1358] +INFO: [Synth 8-256] done synthesizing module 'design_1_axi_gpio_0_0' (10#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:86] +INFO: [Synth 8-6157] synthesizing module 'design_1_xjtag_axi_0_0' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/synth/design_1_xjtag_axi_0_0.v:58] +INFO: [Synth 8-6157] synthesizing module 'xjtag_axi' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/2284/src/xjtag_axi.v:4] + Parameter JTAG_SEL bound to: 3 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'xjtag_axi' (11#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/2284/src/xjtag_axi.v:4] +INFO: [Synth 8-6155] done synthesizing module 'design_1_xjtag_axi_0_0' (12#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/synth/design_1_xjtag_axi_0_0.v:58] +WARNING: [Synth 8-350] instance 'xjtag_axi_0' of module 'design_1_xjtag_axi_0_0' requires 21 connections, but only 19 given [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.v:76] +INFO: [Synth 8-6155] done synthesizing module 'design_1' (13#1) [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.v:13] +INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (14#1) [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/imports/hdl/design_1_wrapper.v:12] +WARNING: [Synth 8-350] instance 'uut' of module 'design_1_wrapper' requires 5 connections, but only 4 given [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.v:32] +INFO: [Synth 8-6155] done synthesizing module 't160_top' (15#1) [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.v:1] +WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_aclk +WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_resetn +WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_in +WARNING: [Synth 8-3331] design cdc_sync has unconnected port scndry_resetn +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[1] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[2] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[3] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[4] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[7] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[8] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[0] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[1] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[2] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[3] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[0] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[1] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[2] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[3] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[4] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[5] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[6] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[7] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[8] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[9] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[10] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[11] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[12] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[13] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[14] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[15] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[16] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[17] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[18] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[19] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[20] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[21] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[22] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[23] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[24] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[25] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[26] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[27] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[28] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[29] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[30] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[31] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[0] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[1] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[2] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[3] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[4] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[7] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[8] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Bus_RNW +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[3] +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[2] +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[1] +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[0] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 451.266 ; gain = 149.840 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 451.266 ; gain = 149.840 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 451.266 ; gain = 149.840 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 192 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_uut' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_uut' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/t160_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/t160_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/dont_touch.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/t160_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/t160_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 192 instances were transformed. + FDR => FDRE: 192 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 815.996 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for sys_clkn. (constraint file d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 3). +Applied set_property CLOCK_BUFFER_TYPE = NONE for sys_clkn. (constraint file d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 4). +Applied set_property IO_BUFFER_TYPE = NONE for sys_clkp. (constraint file d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 5). +Applied set_property CLOCK_BUFFER_TYPE = NONE for sys_clkp. (constraint file d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6). +Applied set_property DONT_TOUCH = true for uut/design_1_i. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for uut/design_1_i/xjtag_axi_0. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for uut/design_1_i/axi_gpio_0. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for uut/design_1_i/axi_gpio_0/U0. (constraint file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/dont_touch.xdc, line 16). +Applied set_property DONT_TOUCH = true for clk_uut. (constraint file auto generated constraint, line ). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment' +INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE2 | 0001 | 00 + iSTATE | 0010 | 01 + iSTATE0 | 0100 | 10 + iSTATE1 | 1000 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 5 + 9 Bit Registers := 1 + 4 Bit Registers := 1 + 2 Bit Registers := 3 + 1 Bit Registers := 82 ++---Muxes : + 2 Input 32 Bit Muxes := 2 + 5 Input 32 Bit Muxes := 1 + 2 Input 9 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 5 + 7 Input 2 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 43 + 4 Input 1 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module pselect_f +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module pselect_f__parameterized0 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module pselect_f__parameterized1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module pselect_f__parameterized2 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module address_decoder +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 6 +Module slave_attachment +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 9 Bit Registers := 1 + 4 Bit Registers := 1 + 2 Bit Registers := 3 + 1 Bit Registers := 7 ++---Muxes : + 2 Input 9 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 5 + 7 Input 2 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 4 + 4 Input 1 Bit Muxes := 3 +Module GPIO_Core +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 3 + 1 Bit Registers := 66 ++---Muxes : + 2 Input 32 Bit Muxes := 2 + 5 Input 32 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 35 +Module axi_gpio +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 1 + 1 Bit Registers := 3 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-4471] merging register 'bus2ip_reset_reg' into 'AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1684] +WARNING: [Synth 8-6014] Unused sequential element bus2ip_reset_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1684] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[3] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[2] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[1] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[0] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[31] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[30] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[29] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[28] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[27] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[26] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[25] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[24] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[23] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[22] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[21] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[20] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[19] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[18] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[17] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[16] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[15] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[14] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[13] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[12] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[11] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[10] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[9] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[8] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[7] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[6] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[5] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[4] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[3] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[2] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[1] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[0] +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uut/design_1_i /axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uut/design_1_i /axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uut/design_1_i /axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uut/design_1_i /axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[1] ) +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[1]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[1]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[7]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[6]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[5]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[4]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[1]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[0]) is unused and will be removed from module axi_gpio. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +INFO: [Synth 8-5578] Moved timing constraint from pin 'clk_uut/clk_out1' to pin 'clk_uut/bbstub_clk_out1/O' +INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 826.445 ; gain = 525.020 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |clk_wiz_0 | 1| +|2 |xjtag_axi | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+----------+------+ +| |Cell |Count | ++------+----------+------+ +|1 |clk_wiz_0 | 1| +|2 |xjtag_axi | 1| +|3 |BUFG | 1| +|4 |LUT1 | 2| +|5 |LUT2 | 9| +|6 |LUT3 | 7| +|7 |LUT4 | 6| +|8 |LUT5 | 108| +|9 |LUT6 | 8| +|10 |FDR | 128| +|11 |FDRE | 221| +|12 |FDSE | 33| +|13 |OBUF | 4| ++------+----------+------+ + +Report Instance Areas: ++------+------------------------------------------+-----------------------+------+ +| |Instance |Module |Cells | ++------+------------------------------------------+-----------------------+------+ +|1 |top | | 640| +|2 | uut |design_1_wrapper | 633| +|3 | design_1_i |design_1 | 633| +|4 | axi_gpio_0 |design_1_axi_gpio_0_0 | 522| +|5 | U0 |axi_gpio | 522| +|6 | AXI_LITE_IPIF_I |axi_lite_ipif | 131| +|7 | I_SLAVE_ATTACHMENT |slave_attachment | 131| +|8 | I_DECODER |address_decoder | 55| +|9 | gpio_core_1 |GPIO_Core | 357| +|10 | \Not_Dual.INPUT_DOUBLE_REGS3 |cdc_sync | 128| +|11 | xjtag_axi_0 |design_1_xjtag_axi_0_0 | 111| ++------+------------------------------------------+-----------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 37 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 838.070 ; gain = 171.914 +Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +INFO: [Project 1-571] Translating synthesized netlist +Release 14.7 - ngc2edif P_INT.20180321 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design xjtag_axi.ngc ... +WARNING:NetListWriters:298 - No output is written to xjtag_axi.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file xjtag_axi.edif ... +ngc2edif: Total memory usage is 89640 kilobytes + +Reading core file 'd:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/src/xjtag_axi.ngc' for (cell view 'xjtag_axi', library 'work') +Parsing EDIF File [./.ngc2edfcache/xjtag_axi_ngc_2e71882e.edif] +Finished Parsing EDIF File [./.ngc2edfcache/xjtag_axi_ngc_2e71882e.edif] +INFO: [Netlist 29-17] Analyzing 285 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Xilinx ngc2edif P_INT.20180321 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 272 instances were transformed. + (MUXCY,XORCY) => CARRY4: 2 instances + BSCAN_SPARTAN6 => BSCANE2: 1 instances + FD => FDRE: 4 instances + FDE => FDRE: 2 instances + FDR => FDRE: 261 instances + INV => LUT1: 2 instances + +INFO: [Common 17-83] Releasing license: Synthesis +252 Infos, 129 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 852.180 ; gain = 560.461 +INFO: [Common 17-600] The following parameters have non-default value. +tcl.collectionResultDisplayLimit +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file t160_top_utilization_synth.rpt -pb t160_top_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.088 . Memory (MB): peak = 852.180 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Tue Jun 30 17:34:24 2020... diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/runme.sh b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/runme.sh new file mode 100644 index 0000000..412d89c --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin +else + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log t160_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.dcp b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.dcp new file mode 100644 index 0000000..738bc57 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.dcp differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.tcl b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.tcl new file mode 100644 index 0000000..ae8d4fc --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.tcl @@ -0,0 +1,76 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param tcl.collectionResultDisplayLimit 0 +set_param xicom.use_bs_reader 1 +set_msg_config -id {HDL-1065} -limit 10000 +create_project -in_memory -part xc7k160tffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/wt [current_project] +set_property parent.project_path D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.xpr [current_project] +set_property XPM_LIBRARIES XPM_CDC [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_repo_paths d:/Xilinx/xjtag/xjtag_ip/axi_bus_ip [current_project] +set_property ip_output_repo d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/imports/hdl/design_1_wrapper.v + D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.v +} +add_files D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1.bd +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_ooc.xdc] +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] +set_property used_in_implementation false [get_files -all D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1_ooc.xdc] + +read_ip -quiet D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc +set_property used_in_implementation false [get_files D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc] + +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top t160_top -part xc7k160tffg676-2 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef t160_top.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file t160_top_utilization_synth.rpt -pb t160_top_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.vds b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.vds new file mode 100644 index 0000000..e39fadf --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.vds @@ -0,0 +1,1047 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jun 30 17:33:46 2020 +# Process ID: 8184 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1 +# Command line: vivado.exe -log t160_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl +# Log file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.vds +# Journal file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source t160_top.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/Xilinx/xjtag/xjtag_ip/axi_bus_ip'. +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2018.2/data/ip'. +Command: synth_design -top t160_top -part xc7k160tffg676-2 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 7432 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 399.355 ; gain = 97.930 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 't160_top' [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.v:1] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.Xil/Vivado-8184-PC2018/realtime/clk_wiz_0_stub.v:5] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (1#1) [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/.Xil/Vivado-8184-PC2018/realtime/clk_wiz_0_stub.v:5] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (2#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/imports/hdl/design_1_wrapper.v:12] +INFO: [Synth 8-6157] synthesizing module 'design_1' [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.v:13] +INFO: [Synth 8-638] synthesizing module 'design_1_axi_gpio_0_0' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:86] + Parameter C_FAMILY bound to: kintex7 - type: string + Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer + Parameter C_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_GPIO2_WIDTH bound to: 32 - type: integer + Parameter C_ALL_INPUTS bound to: 0 - type: integer + Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer + Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000000000000000000000 + Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111 + Parameter C_IS_DUAL bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000 + Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111 +INFO: [Synth 8-3491] module 'axi_gpio' declared at 'd:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1265' bound to instance 'U0' of component 'axi_gpio' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:172] +INFO: [Synth 8-638] synthesizing module 'axi_gpio' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1358] + Parameter C_FAMILY bound to: kintex7 - type: string + Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer + Parameter C_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_GPIO2_WIDTH bound to: 32 - type: integer + Parameter C_ALL_INPUTS bound to: 0 - type: integer + Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer + Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT bound to: 0 - type: integer + Parameter C_TRI_DEFAULT bound to: -1 - type: integer + Parameter C_IS_DUAL bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer + Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer +INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1295] +INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1296] +INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] + Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer + Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111 + Parameter C_USE_WSTRB bound to: 0 - type: integer + Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer + Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 + Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 + Parameter C_FAMILY bound to: kintex7 - type: string +INFO: [Synth 8-638] synthesizing module 'slave_attachment' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] + Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 + Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 + Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer + Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer + Parameter C_USE_WSTRB bound to: 0 - type: integer + Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer + Parameter C_FAMILY bound to: kintex7 - type: string +INFO: [Synth 8-638] synthesizing module 'address_decoder' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] + Parameter C_BUS_AWIDTH bound to: 9 - type: integer + Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer + Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 + Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-638] synthesizing module 'pselect_f' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b00 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f' (3#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b01 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (3#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b10 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (3#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] + Parameter C_AB bound to: 2 - type: integer + Parameter C_AW bound to: 2 - type: integer + Parameter C_BAR bound to: 2'b11 + Parameter C_FAMILY bound to: nofamily - type: string +INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (3#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] +INFO: [Synth 8-256] done synthesizing module 'address_decoder' (4#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] +INFO: [Synth 8-226] default block is never used [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] +INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (5#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] +INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (6#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] +INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:178] + Parameter C_DW bound to: 32 - type: integer + Parameter C_AW bound to: 9 - type: integer + Parameter C_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_GPIO2_WIDTH bound to: 32 - type: integer + Parameter C_MAX_GPIO_WIDTH bound to: 32 - type: integer + Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT bound to: 0 - type: integer + Parameter C_TRI_DEFAULT bound to: -1 - type: integer + Parameter C_IS_DUAL bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS bound to: 0 - type: integer + Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer + Parameter C_ALL_INPUTS bound to: 0 - type: integer + Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer + Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer + Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer + Parameter C_FAMILY bound to: kintex7 - type: string +INFO: [Synth 8-226] default block is never used [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:443] +INFO: [Synth 8-638] synthesizing module 'cdc_sync' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] + Parameter C_CDC_TYPE bound to: 1 - type: integer + Parameter C_RESET_STATE bound to: 0 - type: integer + Parameter C_SINGLE_BIT bound to: 0 - type: integer + Parameter C_FLOP_INPUT bound to: 0 - type: integer + Parameter C_VECTOR_WIDTH bound to: 32 - type: integer + Parameter C_MTBF_STAGES bound to: 4 - type: integer + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804] +INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 + Parameter INIT bound to: 1'b0 +INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (7#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].GPIO_DBus_i_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:384] +INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (8#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:178] +INFO: [Synth 8-256] done synthesizing module 'axi_gpio' (9#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1358] +INFO: [Synth 8-256] done synthesizing module 'design_1_axi_gpio_0_0' (10#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:86] +INFO: [Synth 8-6157] synthesizing module 'design_1_xjtag_axi_0_0' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/synth/design_1_xjtag_axi_0_0.v:58] +INFO: [Synth 8-6157] synthesizing module 'xjtag_axi' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/2284/src/xjtag_axi.v:4] + Parameter JTAG_SEL bound to: 3 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'xjtag_axi' (11#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/2284/src/xjtag_axi.v:4] +INFO: [Synth 8-6155] done synthesizing module 'design_1_xjtag_axi_0_0' (12#1) [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/synth/design_1_xjtag_axi_0_0.v:58] +WARNING: [Synth 8-350] instance 'xjtag_axi_0' of module 'design_1_xjtag_axi_0_0' requires 21 connections, but only 19 given [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.v:76] +INFO: [Synth 8-6155] done synthesizing module 'design_1' (13#1) [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.v:13] +INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (14#1) [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/imports/hdl/design_1_wrapper.v:12] +WARNING: [Synth 8-350] instance 'uut' of module 'design_1_wrapper' requires 5 connections, but only 4 given [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.v:32] +INFO: [Synth 8-6155] done synthesizing module 't160_top' (15#1) [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.v:1] +WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_aclk +WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_resetn +WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_in +WARNING: [Synth 8-3331] design cdc_sync has unconnected port scndry_resetn +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[1] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[2] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[3] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[4] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[7] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[8] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[0] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[1] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[2] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[3] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[0] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[1] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[2] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[3] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[4] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[5] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[6] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[7] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[8] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[9] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[10] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[11] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[12] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[13] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[14] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[15] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[16] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[17] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[18] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[19] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[20] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[21] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[22] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[23] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[24] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[25] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[26] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[27] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[28] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[29] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[30] +WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[31] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[0] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[1] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[2] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[3] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[4] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[7] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[8] +WARNING: [Synth 8-3331] design address_decoder has unconnected port Bus_RNW +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[3] +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[2] +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[1] +WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[0] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 451.266 ; gain = 149.840 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 451.266 ; gain = 149.840 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 451.266 ; gain = 149.840 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 192 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_uut' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_uut' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'uut/design_1_i/axi_gpio_0/U0' +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/src/t160_top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/t160_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/t160_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/dont_touch.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/t160_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/t160_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 192 instances were transformed. + FDR => FDRE: 192 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 815.996 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for sys_clkn. (constraint file d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 3). +Applied set_property CLOCK_BUFFER_TYPE = NONE for sys_clkn. (constraint file d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 4). +Applied set_property IO_BUFFER_TYPE = NONE for sys_clkp. (constraint file d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 5). +Applied set_property CLOCK_BUFFER_TYPE = NONE for sys_clkp. (constraint file d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6). +Applied set_property DONT_TOUCH = true for uut/design_1_i. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for uut/design_1_i/xjtag_axi_0. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for uut/design_1_i/axi_gpio_0. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for uut/design_1_i/axi_gpio_0/U0. (constraint file D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/dont_touch.xdc, line 16). +Applied set_property DONT_TOUCH = true for clk_uut. (constraint file auto generated constraint, line ). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment' +INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE2 | 0001 | 00 + iSTATE | 0010 | 01 + iSTATE0 | 0100 | 10 + iSTATE1 | 1000 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 5 + 9 Bit Registers := 1 + 4 Bit Registers := 1 + 2 Bit Registers := 3 + 1 Bit Registers := 82 ++---Muxes : + 2 Input 32 Bit Muxes := 2 + 5 Input 32 Bit Muxes := 1 + 2 Input 9 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 5 + 7 Input 2 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 43 + 4 Input 1 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module pselect_f +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module pselect_f__parameterized0 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module pselect_f__parameterized1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module pselect_f__parameterized2 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module address_decoder +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 6 +Module slave_attachment +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 9 Bit Registers := 1 + 4 Bit Registers := 1 + 2 Bit Registers := 3 + 1 Bit Registers := 7 ++---Muxes : + 2 Input 9 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 5 + 7 Input 2 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 4 + 4 Input 1 Bit Muxes := 3 +Module GPIO_Core +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 3 + 1 Bit Registers := 66 ++---Muxes : + 2 Input 32 Bit Muxes := 2 + 5 Input 32 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 35 +Module axi_gpio +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 1 + 1 Bit Registers := 3 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-4471] merging register 'bus2ip_reset_reg' into 'AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg' [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1684] +WARNING: [Synth 8-6014] Unused sequential element bus2ip_reset_reg was removed. [d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd:1684] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[3] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[2] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[1] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[0] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[31] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[30] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[29] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[28] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[27] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[26] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[25] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[24] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[23] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[22] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[21] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[20] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[19] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[18] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[17] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[16] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[15] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[14] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[13] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[12] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[11] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[10] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[9] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[8] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[7] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[6] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[5] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[4] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[3] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[2] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[1] +WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[0] +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uut/design_1_i /axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uut/design_1_i /axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uut/design_1_i /axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uut/design_1_i /axi_gpio_0/U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[1] ) +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[1]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[1]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[7]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[6]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[5]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[4]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[1]) is unused and will be removed from module axi_gpio. +INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[0]) is unused and will be removed from module axi_gpio. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +INFO: [Synth 8-5578] Moved timing constraint from pin 'clk_uut/clk_out1' to pin 'clk_uut/bbstub_clk_out1/O' +INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 815.996 ; gain = 514.570 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 826.445 ; gain = 525.020 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |clk_wiz_0 | 1| +|2 |xjtag_axi | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+----------+------+ +| |Cell |Count | ++------+----------+------+ +|1 |clk_wiz_0 | 1| +|2 |xjtag_axi | 1| +|3 |BUFG | 1| +|4 |LUT1 | 2| +|5 |LUT2 | 9| +|6 |LUT3 | 7| +|7 |LUT4 | 6| +|8 |LUT5 | 108| +|9 |LUT6 | 8| +|10 |FDR | 128| +|11 |FDRE | 221| +|12 |FDSE | 33| +|13 |OBUF | 4| ++------+----------+------+ + +Report Instance Areas: ++------+------------------------------------------+-----------------------+------+ +| |Instance |Module |Cells | ++------+------------------------------------------+-----------------------+------+ +|1 |top | | 640| +|2 | uut |design_1_wrapper | 633| +|3 | design_1_i |design_1 | 633| +|4 | axi_gpio_0 |design_1_axi_gpio_0_0 | 522| +|5 | U0 |axi_gpio | 522| +|6 | AXI_LITE_IPIF_I |axi_lite_ipif | 131| +|7 | I_SLAVE_ATTACHMENT |slave_attachment | 131| +|8 | I_DECODER |address_decoder | 55| +|9 | gpio_core_1 |GPIO_Core | 357| +|10 | \Not_Dual.INPUT_DOUBLE_REGS3 |cdc_sync | 128| +|11 | xjtag_axi_0 |design_1_xjtag_axi_0_0 | 111| ++------+------------------------------------------+-----------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 37 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 838.070 ; gain = 171.914 +Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 838.070 ; gain = 536.645 +INFO: [Project 1-571] Translating synthesized netlist +Release 14.7 - ngc2edif P_INT.20180321 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design xjtag_axi.ngc ... +WARNING:NetListWriters:298 - No output is written to xjtag_axi.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file xjtag_axi.edif ... +ngc2edif: Total memory usage is 89640 kilobytes + +Reading core file 'd:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/src/xjtag_axi.ngc' for (cell view 'xjtag_axi', library 'work') +Parsing EDIF File [./.ngc2edfcache/xjtag_axi_ngc_2e71882e.edif] +Finished Parsing EDIF File [./.ngc2edfcache/xjtag_axi_ngc_2e71882e.edif] +INFO: [Netlist 29-17] Analyzing 285 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Xilinx ngc2edif P_INT.20180321 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 272 instances were transformed. + (MUXCY,XORCY) => CARRY4: 2 instances + BSCAN_SPARTAN6 => BSCANE2: 1 instances + FD => FDRE: 4 instances + FDE => FDRE: 2 instances + FDR => FDRE: 261 instances + INV => LUT1: 2 instances + +INFO: [Common 17-83] Releasing license: Synthesis +252 Infos, 129 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 852.180 ; gain = 560.461 +INFO: [Common 17-600] The following parameters have non-default value. +tcl.collectionResultDisplayLimit +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file t160_top_utilization_synth.rpt -pb t160_top_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.088 . Memory (MB): peak = 852.180 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Tue Jun 30 17:34:24 2020... diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top_utilization_synth.pb b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top_utilization_synth.pb new file mode 100644 index 0000000..757f701 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top_utilization_synth.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top_utilization_synth.rpt b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top_utilization_synth.rpt new file mode 100644 index 0000000..291804e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top_utilization_synth.rpt @@ -0,0 +1,188 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:34:23 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_utilization -file t160_top_utilization_synth.rpt -pb t160_top_utilization_synth.pb +| Design : t160_top +| Device : 7k160tffg676-2 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 324 | 0 | 101400 | 0.32 | +| LUT as Logic | 324 | 0 | 101400 | 0.32 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 799 | 0 | 202800 | 0.39 | +| Register as Flip Flop | 799 | 0 | 202800 | 0.39 | +| Register as Latch | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 33 | Yes | Set | - | +| 766 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 4 | 0 | 400 | 1.00 | +| Bonded IPADs | 0 | 0 | 26 | 0.00 | +| Bonded OPADs | 0 | 0 | 16 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 384 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 2 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 8 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 400 | 0.00 | +| OLOGIC | 0 | 0 | 400 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 1 | 0 | 4 | 25.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 766 | Flop & Latch | +| LUT5 | 145 | LUT | +| LUT2 | 119 | LUT | +| FDSE | 33 | Flop & Latch | +| LUT6 | 21 | LUT | +| LUT4 | 20 | LUT | +| LUT3 | 17 | LUT | +| LUT1 | 11 | LUT | +| OBUF | 4 | IO | +| CARRY4 | 2 | CarryLogic | +| BUFG | 1 | Clock | +| BSCANE2 | 1 | Others | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++-----------+------+ +| Ref Name | Used | ++-----------+------+ +| clk_wiz_0 | 1 | ++-----------+------+ + + +9. Instantiated Netlists +------------------------ + ++-----------+------+ +| Ref Name | Used | ++-----------+------+ +| xjtag_axi | 1 | ++-----------+------+ + + diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/vivado.jou b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/vivado.jou new file mode 100644 index 0000000..085f9cb --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Tue Jun 30 17:33:46 2020 +# Process ID: 8184 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1 +# Command line: vivado.exe -log t160_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl +# Log file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/t160_top.vds +# Journal file: D:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source t160_top.tcl -notrace diff --git a/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/vivado.pb b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/vivado.pb new file mode 100644 index 0000000..b5ea97d Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.runs/synth_1/vivado.pb differ diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1.bd b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1.bd new file mode 100644 index 0000000..bc7106d --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1.bd @@ -0,0 +1,248 @@ +锘 + + + + xilinx.com + BlockDiagram + design_1 + 1.00.a + + + isTop + true + + + + + RST.RSTN + Reset + Reset + + + + + + + RST + + + rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.CLK + Clk + Clock + + + + + + + CLK + + + clk + + + + + + FREQ_HZ + 100000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + design_1_m00_axi_aclk_0 + + + + + + + + ASSOCIATED_RESET + rstn + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + gpio_in + + in + + 31 + 0 + + + + + gpio_out + + out + + 31 + 0 + + + + + rstn + + in + + + + clk + + in + + + + gpio_io_t_0 + + out + + 31 + 0 + + + + + + + + + xilinx.com + BlockDiagram + design_1_imp + 1.00.a + + + axi_gpio_0 + + + design_1_axi_gpio_0_0 + + + + xjtag_axi_0 + + + design_1_xjtag_axi_0_0 + + + + + + xjtag_axi_0_m00_axi + + + + + + + gpio_io_i_0_1 + + + + + axi_gpio_0_gpio_io_o + + + + + m00_axi_aresetn_0_1 + + + + + + m00_axi_aclk_0_1 + + + + + + axi_gpio_0_gpio_io_t + + + + + + + + xilinx.com + Addressing/xjtag_axi_0 + xjtag_axi + 1.0 + + + m00_axi + + + + + + + + + + m00_axi + 4G + 32 + + + SEG_axi_gpio_0_Reg + /axi_gpio_0/S_AXI/Reg + 0x40000000 + 64K + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1.bxml b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1.bxml new file mode 100644 index 0000000..10ed914 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1.bxml @@ -0,0 +1,61 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1_ooc.xdc b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1_ooc.xdc new file mode 100644 index 0000000..9a1eb45 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/design_1_ooc.xdc @@ -0,0 +1,11 @@ +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# This constraints file is not used in normal top-down synthesis (default flow +# of Vivado) +################################################################################ +create_clock -name clk -period 10 [get_ports clk] + +################################################################################ \ No newline at end of file diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v new file mode 100644 index 0000000..43908b3 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v @@ -0,0 +1,36 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +//Date : Tue Jun 30 17:32:55 2020 +//Host : PC2018 running 64-bit Service Pack 1 (build 7601) +//Command : generate_target design_1_wrapper.bd +//Design : design_1_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module design_1_wrapper + (clk, + gpio_in, + gpio_io_t_0, + gpio_out, + rstn); + input clk; + input [31:0]gpio_in; + output [31:0]gpio_io_t_0; + output [31:0]gpio_out; + input rstn; + + wire clk; + wire [31:0]gpio_in; + wire [31:0]gpio_io_t_0; + wire [31:0]gpio_out; + wire rstn; + + design_1 design_1_i + (.clk(clk), + .gpio_in(gpio_in), + .gpio_io_t_0(gpio_io_t_0), + .gpio_out(gpio_out), + .rstn(rstn)); +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh new file mode 100644 index 0000000..822169a --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh @@ -0,0 +1,576 @@ +锘 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl new file mode 100644 index 0000000..749ed1c --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl @@ -0,0 +1,200 @@ + +################################################################ +# This is a generated script based on design: design_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2018.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7k160tffg676-2 +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name design_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + + # Create ports + set clk [ create_bd_port -dir I -type clk clk ] + set gpio_in [ create_bd_port -dir I -from 31 -to 0 gpio_in ] + set gpio_io_t_0 [ create_bd_port -dir O -from 31 -to 0 gpio_io_t_0 ] + set gpio_out [ create_bd_port -dir O -from 31 -to 0 gpio_out ] + set rstn [ create_bd_port -dir I -type rst rstn ] + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + + # Create instance: xjtag_axi_0, and set properties + set xjtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:xjtag_axi:1.0 xjtag_axi_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net xjtag_axi_0_m00_axi [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins xjtag_axi_0/m00_axi] + + # Create port connections + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_ports gpio_out] [get_bd_pins axi_gpio_0/gpio_io_o] + connect_bd_net -net axi_gpio_0_gpio_io_t [get_bd_ports gpio_io_t_0] [get_bd_pins axi_gpio_0/gpio_io_t] + connect_bd_net -net gpio_io_i_0_1 [get_bd_ports gpio_in] [get_bd_pins axi_gpio_0/gpio_io_i] + connect_bd_net -net m00_axi_aclk_0_1 [get_bd_ports clk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins xjtag_axi_0/m00_axi_aclk] + connect_bd_net -net m00_axi_aresetn_0_1 [get_bd_ports rstn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins xjtag_axi_0/m00_axi_aresetn] + + # Create address segments + create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces xjtag_axi_0/m00_axi] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xci b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xci new file mode 100644 index 0000000..7f2a997 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xci @@ -0,0 +1,128 @@ + + + xilinx.com + xci + unknown + 1.0 + + + design_1_axi_gpio_0_0 + + + 1 + 9 + 0 + 0 + 0 + design_1_m00_axi_aclk_0 + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + design_1_m00_axi_aclk_0 + 100000000 + 0.000 + 0 + 0 + 0 + 0 + 0x00000000 + 0x00000000 + kintex7 + 32 + 32 + 0 + 0 + 0xFFFFFFFF + 0xFFFFFFFF + 0 + 0 + 0 + 0 + 0x00000000 + 0x00000000 + 32 + 32 + 0 + 0 + 0xFFFFFFFF + 0xFFFFFFFF + design_1_axi_gpio_0_0 + Custom + Custom + false + kintex7 + + xc7k160t + ffg676 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Integrator + 19 + TRUE + . + + ../../ipshared + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc new file mode 100644 index 0000000..535d6e2 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc @@ -0,0 +1,48 @@ +# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +set_false_path -to [get_pins -hier *cdc_to*/D] + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xml b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xml new file mode 100644 index 0000000..0e0d58f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xml @@ -0,0 +1,1984 @@ + + + xilinx.com + customized_ip + design_1_axi_gpio_0_0 + 1.0 + + + S_AXI + S_AXI + + + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 9 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 0 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_m00_axi_aclk_0 + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + S_AXI_ACLK + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + S_AXI + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_m00_axi_aclk_0 + + + none + + + + + + + S_AXI_ARESETN + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + IP2INTC_IRQ + IP2Intc_irq + + + + + + + INTERRUPT + + + ip2intc_irpt + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + GPIO + GPIO + + + + + + + TRI_I + + + gpio_io_i + + + + + TRI_O + + + gpio_io_o + + + + + TRI_T + + + gpio_io_t + + + + + + BOARD.ASSOCIATED_PARAM + GPIO_BOARD_INTERFACE + + + + required + + + + + + + + + true + + + + + + GPIO2 + GPIO2 + + + + + + + TRI_I + + + gpio2_io_i + + + + + TRI_O + + + gpio2_io_o + + + + + TRI_T + + + gpio2_io_t + + + + + + BOARD.ASSOCIATED_PARAM + GPIO2_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + + + S_AXI + S_AXI_MEM + Memory Map for S_AXI + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + GPIO_DATA + Channel-1 GPIO DATA + Channel-1 AXI GPIO Data register + 0x0 + 32 + true + read-write + + 0x0 + + + Channel-1 GPIO DATA + Channel-1 GPIO DATA + AXI GPIO Data Register. +For each I/O bit programmed as input + R - Reads value on the input pin. + W - No effect. +For each I/O bit programmed as output + R - Reads value on GPIO_O pins + W - Writes value to the corresponding AXI GPIO + data register bit and output pin + + 0 + 32 + true + read-write + + 0 + 0 + + false + + + + GPIO_TRI + Channel-1 GPIO TRI + Channel-1 AXI GPIO 3-State Control register + 0x4 + 32 + true + read-write + + 0x0 + + + Channel-1 GPIO TRI + Channel-1 GPIO DATA + AXI GPIO 3-State Control Register +Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input + + 0 + 32 + true + read-write + + 0 + 0 + + false + + + + GPIO2_DATA + Channel-2 GPIO DATA + Channel-2 AXI GPIO Data register + 0x8 + 32 + true + read-write + + 0x0 + + + Channel-2 GPIO DATA + Channel-2 GPIO DATA + AXI GPIO Data Register. +For each I/O bit programmed as input + R - Reads value on the input pin. + W - No effect. +For each I/O bit programmed as output + R - Reads value on GPIO_O pins + W - Writes value to the corresponding AXI GPIO + data register bit and output pin + + 0 + 32 + true + read-write + + 0 + 0 + + false + + + + GPIO2_TRI + Channel-2 GPIO TRI + Channel-2 AXI GPIO 3-State Control register + 0xC + 32 + true + read-write + + 0x0 + + + Channel-2 GPIO TRI + Channel-2 GPIO DATA + AXI GPIO 3-State Control Register +Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input + + 0 + 32 + true + read-write + + 0 + 0 + + false + + + + GIER + Global Interrupt Enable register + Global Interrupt Enable register + 0x11C + 32 + true + read-write + + 0x0 + + + Global Interrupt Enable + Global Interrupt Enable + Master enable for the device interrupt output + 0 - Disabled + 1 - Enabled + + 31 + 1 + true + read-write + + 0 + 0 + + false + + + + IP_IER + IP Interrupt Enable register + IP Interrupt Enable register + 0x128 + 32 + true + read-write + + 0x0 + + + Channel-1 Interrupt Enable + Channel-1 Interrupt Enable + Enable Channel 1 Interrupt + 0 - Disabled (masked) + 1 - Enabled + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + Channel-2 Interrupt Enable + Channel-2 Interrupt Enable + Enable Channel 2 Interrupt + 0 - Disabled (masked) + 1 - Enabled + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + IP_ISR + IP Interrupt Status register + IP Interrupt Status register + 0x120 + 32 + true + read-write + + 0x0 + + + Channel-1 Interrupt Status + Channel-1 Interrupt Status + Channel 1 Interrupt Status + 0 - No Channel 1 input interrupt + 1 - Channel 1 input interrupt + + 0 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + Channel-2 Interrupt Status + Channel-2 Interrupt Status + Channel 2 Interrupt Status + 0 - No Channel 2 input interrupt + 1 - Channel 2 input interrupt + + 1 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axi_gpio + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Tue Jun 30 01:40:57 UTC 2020 + + + outputProductCRC + 8:d47cbfde + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + design_1_axi_gpio_0_0 + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jun 30 01:40:57 UTC 2020 + + + outputProductCRC + 8:d47cbfde + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axi_gpio + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Tue Jun 30 01:40:57 UTC 2020 + + + outputProductCRC + 8:0e55727e + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + design_1_axi_gpio_0_0 + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Tue Jun 30 01:40:57 UTC 2020 + + + outputProductCRC + 8:0e55727e + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + GENtimestamp + Tue Jun 30 01:40:57 UTC 2020 + + + outputProductCRC + 8:d47cbfde + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + s_axi_awaddr + + in + + 8 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 8 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + ip2intc_irpt + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + gpio_io_i + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + gpio_io_o + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + gpio_io_t + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + gpio2_io_i + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + gpio2_io_o + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + gpio2_io_t + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + + + C_FAMILY + kintex7 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 9 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_GPIO_WIDTH + GPIO Width + 32 + + + C_GPIO2_WIDTH + GPIO2 Data Width + 32 + + + C_ALL_INPUTS + All Inputs + 0 + + + C_ALL_INPUTS_2 + All Inputs + 0 + + + C_ALL_OUTPUTS + All Outputs + 0 + + + C_ALL_OUTPUTS_2 + All Outputs + 0 + + + C_INTERRUPT_PRESENT + Enable Interrupt + 0 + + + C_DOUT_DEFAULT + Default DOUT value + 0x00000000 + + + C_TRI_DEFAULT + Default tri state value + 0xFFFFFFFF + + + C_IS_DUAL + Enable Dual channel + 0 + + + C_DOUT_DEFAULT_2 + Default DOUT value2 + 0x00000000 + + + C_TRI_DEFAULT_2 + Default tri state value2 + 0xFFFFFFFF + + + + + + choice_list_ac75ef1e + Custom + + + choice_pairs_4873554b + 0 + 1 + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + ../../ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd + vhdlSource + axi_lite_ipif_v3_0_4 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + ../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd + vhdlSource + lib_cdc_v1_0_2 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset + + ../../ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd + vhdlSource + interrupt_control_v3_1_4 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + design_1_axi_gpio_0_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + design_1_axi_gpio_0_0.xdc + xdc + + + ../../ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd + vhdlSource + axi_gpio_v2_0_19 + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/design_1_axi_gpio_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + ../../ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_lite_ipif_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + ../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd + vhdlSource + USED_IN_ipstatic + lib_cdc_v1_0_2 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset + + ../../ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + interrupt_control_v3_1_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_gpio_v2_0_19 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/design_1_axi_gpio_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_implementation_view_fileset + + design_1_axi_gpio_0_0_board.xdc + xdc + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + Advanced eXtensible Interface General Purpose Input/Output (AXI GPIO) core provides a general purpose input/output interface to the AXI interface. + + + C_TRI_DEFAULT + Default Tri State Value + 0xFFFFFFFF + + + + true + + + + + + C_GPIO_WIDTH + GPIO Width + 32 + + + + true + + + + + + C_GPIO2_WIDTH + GPIO Width + 32 + + + + false + + + + + + C_IS_DUAL + Enable Dual Channel + 0 + + + + true + + + + + + C_ALL_INPUTS + All Inputs + 0 + + + + true + + + + + + C_TRI_DEFAULT_2 + Default Tri State Value + 0xFFFFFFFF + + + + false + + + + + + C_DOUT_DEFAULT_2 + Default Output Value + 0x00000000 + + + + false + + + + + + C_DOUT_DEFAULT + Default Output Value + 0x00000000 + + + + true + + + + + + C_ALL_INPUTS_2 + All Inputs + 0 + + + + false + + + + + + C_INTERRUPT_PRESENT + Enable Interrupt + 0 + + + + true + + + + + + Component_Name + design_1_axi_gpio_0_0 + + + + true + + + + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + + true + + + + + + GPIO_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO2_BOARD_INTERFACE + Custom + + + + true + + + + + + C_ALL_OUTPUTS + All Outputs + 0 + + + + true + + + + + + C_ALL_OUTPUTS_2 + All Outputs + 0 + + + + false + + + + + + + + AXI GPIO + 19 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc new file mode 100644 index 0000000..3422a8e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc @@ -0,0 +1,2 @@ +#--------------------Physical Constraints----------------- + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_ooc.xdc b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_ooc.xdc new file mode 100644 index 0000000..907e9e9 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_ooc.xdc @@ -0,0 +1,62 @@ + +################################################################################ +# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# User should update the correct clock period before proceeding further +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# For best results the frequencies should be modified# to match the target +# frequencies. + + + create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk] +## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk] + +################################################################################ diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd new file mode 100644 index 0000000..a4f2370 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd @@ -0,0 +1,209 @@ +-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_gpio:2.0 +-- IP Revision: 19 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY axi_gpio_v2_0_19; +USE axi_gpio_v2_0_19.axi_gpio; + +ENTITY design_1_axi_gpio_0_0 IS + PORT ( + s_axi_aclk : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END design_1_axi_gpio_0_0; + +ARCHITECTURE design_1_axi_gpio_0_0_arch OF design_1_axi_gpio_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axi_gpio IS + GENERIC ( + C_FAMILY : STRING; + C_S_AXI_ADDR_WIDTH : INTEGER; + C_S_AXI_DATA_WIDTH : INTEGER; + C_GPIO_WIDTH : INTEGER; + C_GPIO2_WIDTH : INTEGER; + C_ALL_INPUTS : INTEGER; + C_ALL_INPUTS_2 : INTEGER; + C_ALL_OUTPUTS : INTEGER; + C_ALL_OUTPUTS_2 : INTEGER; + C_INTERRUPT_PRESENT : INTEGER; + C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_IS_DUAL : INTEGER; + C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + PORT ( + s_axi_aclk : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + ip2intc_irpt : OUT STD_LOGIC; + gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + END COMPONENT axi_gpio; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T"; + ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; + ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE"; + ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0, NUM_READ_THREADS 1, NUM_WRITE_THRE" & +"ADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; +BEGIN + U0 : axi_gpio + GENERIC MAP ( + C_FAMILY => "kintex7", + C_S_AXI_ADDR_WIDTH => 9, + C_S_AXI_DATA_WIDTH => 32, + C_GPIO_WIDTH => 32, + C_GPIO2_WIDTH => 32, + C_ALL_INPUTS => 0, + C_ALL_INPUTS_2 => 0, + C_ALL_OUTPUTS => 0, + C_ALL_OUTPUTS_2 => 0, + C_INTERRUPT_PRESENT => 0, + C_DOUT_DEFAULT => X"00000000", + C_TRI_DEFAULT => X"FFFFFFFF", + C_IS_DUAL => 0, + C_DOUT_DEFAULT_2 => X"00000000", + C_TRI_DEFAULT_2 => X"FFFFFFFF" + ) + PORT MAP ( + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_awready => s_axi_awready, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + gpio_io_i => gpio_io_i, + gpio_io_o => gpio_io_o, + gpio_io_t => gpio_io_t, + gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)) + ); +END design_1_axi_gpio_0_0_arch; diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd new file mode 100644 index 0000000..8f174df --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd @@ -0,0 +1,215 @@ +-- (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_gpio:2.0 +-- IP Revision: 19 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY axi_gpio_v2_0_19; +USE axi_gpio_v2_0_19.axi_gpio; + +ENTITY design_1_axi_gpio_0_0 IS + PORT ( + s_axi_aclk : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END design_1_axi_gpio_0_0; + +ARCHITECTURE design_1_axi_gpio_0_0_arch OF design_1_axi_gpio_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axi_gpio IS + GENERIC ( + C_FAMILY : STRING; + C_S_AXI_ADDR_WIDTH : INTEGER; + C_S_AXI_DATA_WIDTH : INTEGER; + C_GPIO_WIDTH : INTEGER; + C_GPIO2_WIDTH : INTEGER; + C_ALL_INPUTS : INTEGER; + C_ALL_INPUTS_2 : INTEGER; + C_ALL_OUTPUTS : INTEGER; + C_ALL_OUTPUTS_2 : INTEGER; + C_INTERRUPT_PRESENT : INTEGER; + C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_IS_DUAL : INTEGER; + C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + PORT ( + s_axi_aclk : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + ip2intc_irpt : OUT STD_LOGIC; + gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + END COMPONENT axi_gpio; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2018.2"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_gpio_0_0_arch : ARCHITECTURE IS "design_1_axi_gpio_0_0,axi_gpio,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "design_1_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=19,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=32,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T"; + ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; + ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE"; + ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0, NUM_READ_THREADS 1, NUM_WRITE_THRE" & +"ADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; +BEGIN + U0 : axi_gpio + GENERIC MAP ( + C_FAMILY => "kintex7", + C_S_AXI_ADDR_WIDTH => 9, + C_S_AXI_DATA_WIDTH => 32, + C_GPIO_WIDTH => 32, + C_GPIO2_WIDTH => 32, + C_ALL_INPUTS => 0, + C_ALL_INPUTS_2 => 0, + C_ALL_OUTPUTS => 0, + C_ALL_OUTPUTS_2 => 0, + C_INTERRUPT_PRESENT => 0, + C_DOUT_DEFAULT => X"00000000", + C_TRI_DEFAULT => X"FFFFFFFF", + C_IS_DUAL => 0, + C_DOUT_DEFAULT_2 => X"00000000", + C_TRI_DEFAULT_2 => X"FFFFFFFF" + ) + PORT MAP ( + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_awready => s_axi_awready, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + gpio_io_i => gpio_io_i, + gpio_io_o => gpio_io_o, + gpio_io_t => gpio_io_t, + gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)) + ); +END design_1_axi_gpio_0_0_arch; diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/design_1_xjtag_axi_0_0.xci b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/design_1_xjtag_axi_0_0.xci new file mode 100644 index 0000000..5ff8d9b --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/design_1_xjtag_axi_0_0.xci @@ -0,0 +1,103 @@ + + + xilinx.com + xci + unknown + 1.0 + + + design_1_xjtag_axi_0_0 + + + 4294967296 + 32 + 32 + 0 + 0 + 0 + design_1_m00_axi_aclk_0 + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + design_1_m00_axi_aclk_0 + 100000000 + 0.000 + 3 + design_1_xjtag_axi_0_0 + 3 + kintex7 + + xc7k160t + ffg676 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Integrator + 2 + TRUE + . + + ../../ipshared + 2018.2 + GLOBAL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/design_1_xjtag_axi_0_0.xml b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/design_1_xjtag_axi_0_0.xml new file mode 100644 index 0000000..e4b420e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/design_1_xjtag_axi_0_0.xml @@ -0,0 +1,1058 @@ + + + xilinx.com + customized_ip + design_1_xjtag_axi_0_0 + 1.0 + + + m00_axi + + + + + + + + + AWADDR + + + m00_axi_awaddr + + + + + AWPROT + + + m00_axi_awprot + + + + + AWVALID + + + m00_axi_awvalid + + + + + AWREADY + + + m00_axi_awready + + + + + WDATA + + + m00_axi_wdata + + + + + WSTRB + + + m00_axi_wstrb + + + + + WVALID + + + m00_axi_wvalid + + + + + WREADY + + + m00_axi_wready + + + + + BRESP + + + m00_axi_bresp + + + + + BVALID + + + m00_axi_bvalid + + + + + BREADY + + + m00_axi_bready + + + + + ARADDR + + + m00_axi_araddr + + + + + ARPROT + + + m00_axi_arprot + + + + + ARVALID + + + m00_axi_arvalid + + + + + ARREADY + + + m00_axi_arready + + + + + RDATA + + + m00_axi_rdata + + + + + RRESP + + + m00_axi_rresp + + + + + RVALID + + + m00_axi_rvalid + + + + + RREADY + + + m00_axi_rready + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 32 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 1 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 0 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_m00_axi_aclk_0 + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + m00_axi_aresetn + + + + + + + RST + + + m00_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m00_axi_aclk + + + + + + + CLK + + + m00_axi_aclk + + + + + + ASSOCIATED_BUSIF + m00_axi + + + ASSOCIATED_RESET + m00_axi_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_m00_axi_aclk_0 + + + none + + + + + + + + + m00_axi + 4294967296 + 32 + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + xjtag_axi + + xilinx_anylanguagesynthesis_view_fileset + + + + GENtimestamp + Tue Jun 30 09:32:55 UTC 2020 + + + outputProductCRC + 8:9f1c57ca + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + design_1_xjtag_axi_0_0 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Tue Jun 30 09:32:55 UTC 2020 + + + outputProductCRC + 8:9f1c57ca + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + xjtag_axi + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Tue Jun 30 09:32:55 UTC 2020 + + + outputProductCRC + 8:7f9db52e + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + design_1_xjtag_axi_0_0 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Tue Jun 30 09:32:55 UTC 2020 + + + outputProductCRC + 8:7f9db52e + + + + + + + m00_axi_aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awaddr + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awprot + + out + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_wdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_wstrb + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_wvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_wready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_bresp + + in + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_bvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_bready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_araddr + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_arprot + + out + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_arvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_arready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_rdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_rresp + + in + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_rvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_rready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + JTAG_SEL + Jtag Sel + 3 + + + + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/xjtag_axi.ngc + ngc + + + ../../ipshared/2284/src/xjtag_axi.v + verilogSource + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/design_1_xjtag_axi_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../ipshared/2284/src/xjtag_axi.v + verilogSource + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/design_1_xjtag_axi_0_0.v + verilogSource + xil_defaultlib + + + + xjtag_axi_v1_0 + + + JTAG_SEL + Jtag Sel + 3 + + + Component_Name + design_1_xjtag_axi_0_0 + + + + + xjtag_axi_v1_0 + package_project + 2 + + + d:/Xilinx/xjtag/xjtag_ise_axi/xjtag_axi + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v new file mode 100644 index 0000000..d99b83f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/sim/design_1_xjtag_axi_0_0.v @@ -0,0 +1,153 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:user:xjtag_axi:1.0 +// IP Revision: 2 + +`timescale 1ns/1ps + +(* IP_DEFINITION_SOURCE = "package_project" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xjtag_axi_0_0 ( + m00_axi_aclk, + m00_axi_aresetn, + m00_axi_awaddr, + m00_axi_awprot, + m00_axi_awvalid, + m00_axi_awready, + m00_axi_wdata, + m00_axi_wstrb, + m00_axi_wvalid, + m00_axi_wready, + m00_axi_bresp, + m00_axi_bvalid, + m00_axi_bready, + m00_axi_araddr, + m00_axi_arprot, + m00_axi_arvalid, + m00_axi_arready, + m00_axi_rdata, + m00_axi_rresp, + m00_axi_rvalid, + m00_axi_rready +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_BUSIF m00_axi, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m00_axi_aclk CLK" *) +input wire m00_axi_aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m00_axi_aresetn RST" *) +input wire m00_axi_aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWADDR" *) +output wire [31 : 0] m00_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWPROT" *) +output wire [2 : 0] m00_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWVALID" *) +output wire m00_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWREADY" *) +input wire m00_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WDATA" *) +output wire [31 : 0] m00_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WSTRB" *) +output wire [3 : 0] m00_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WVALID" *) +output wire m00_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WREADY" *) +input wire m00_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BRESP" *) +input wire [1 : 0] m00_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BVALID" *) +input wire m00_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BREADY" *) +output wire m00_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARADDR" *) +output wire [31 : 0] m00_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARPROT" *) +output wire [2 : 0] m00_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARVALID" *) +output wire m00_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARREADY" *) +input wire m00_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RDATA" *) +input wire [31 : 0] m00_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RRESP" *) +input wire [1 : 0] m00_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RVALID" *) +input wire m00_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0, NUM_READ_THREADS 1, NUM_WRITE_T\ +HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RREADY" *) +output wire m00_axi_rready; + + xjtag_axi #( + .JTAG_SEL(3) + ) inst ( + .m00_axi_aclk(m00_axi_aclk), + .m00_axi_aresetn(m00_axi_aresetn), + .m00_axi_awaddr(m00_axi_awaddr), + .m00_axi_awprot(m00_axi_awprot), + .m00_axi_awvalid(m00_axi_awvalid), + .m00_axi_awready(m00_axi_awready), + .m00_axi_wdata(m00_axi_wdata), + .m00_axi_wstrb(m00_axi_wstrb), + .m00_axi_wvalid(m00_axi_wvalid), + .m00_axi_wready(m00_axi_wready), + .m00_axi_bresp(m00_axi_bresp), + .m00_axi_bvalid(m00_axi_bvalid), + .m00_axi_bready(m00_axi_bready), + .m00_axi_araddr(m00_axi_araddr), + .m00_axi_arprot(m00_axi_arprot), + .m00_axi_arvalid(m00_axi_arvalid), + .m00_axi_arready(m00_axi_arready), + .m00_axi_rdata(m00_axi_rdata), + .m00_axi_rresp(m00_axi_rresp), + .m00_axi_rvalid(m00_axi_rvalid), + .m00_axi_rready(m00_axi_rready) + ); +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/src/xjtag_axi.ngc b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/src/xjtag_axi.ngc new file mode 100644 index 0000000..16be3c0 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/src/xjtag_axi.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/synth/design_1_xjtag_axi_0_0.v b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/synth/design_1_xjtag_axi_0_0.v new file mode 100644 index 0000000..dc0375c --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ip/design_1_xjtag_axi_0_0/synth/design_1_xjtag_axi_0_0.v @@ -0,0 +1,154 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:user:xjtag_axi:1.0 +// IP Revision: 2 + +(* X_CORE_INFO = "xjtag_axi,Vivado 2018.2" *) +(* CHECK_LICENSE_TYPE = "design_1_xjtag_axi_0_0,xjtag_axi,{}" *) +(* CORE_GENERATION_INFO = "design_1_xjtag_axi_0_0,xjtag_axi,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=xjtag_axi,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,JTAG_SEL=3}" *) +(* IP_DEFINITION_SOURCE = "package_project" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_xjtag_axi_0_0 ( + m00_axi_aclk, + m00_axi_aresetn, + m00_axi_awaddr, + m00_axi_awprot, + m00_axi_awvalid, + m00_axi_awready, + m00_axi_wdata, + m00_axi_wstrb, + m00_axi_wvalid, + m00_axi_wready, + m00_axi_bresp, + m00_axi_bvalid, + m00_axi_bready, + m00_axi_araddr, + m00_axi_arprot, + m00_axi_arvalid, + m00_axi_arready, + m00_axi_rdata, + m00_axi_rresp, + m00_axi_rvalid, + m00_axi_rready +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_BUSIF m00_axi, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m00_axi_aclk CLK" *) +input wire m00_axi_aclk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m00_axi_aresetn RST" *) +input wire m00_axi_aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWADDR" *) +output wire [31 : 0] m00_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWPROT" *) +output wire [2 : 0] m00_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWVALID" *) +output wire m00_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWREADY" *) +input wire m00_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WDATA" *) +output wire [31 : 0] m00_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WSTRB" *) +output wire [3 : 0] m00_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WVALID" *) +output wire m00_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi WREADY" *) +input wire m00_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BRESP" *) +input wire [1 : 0] m00_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BVALID" *) +input wire m00_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi BREADY" *) +output wire m00_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARADDR" *) +output wire [31 : 0] m00_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARPROT" *) +output wire [2 : 0] m00_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARVALID" *) +output wire m00_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi ARREADY" *) +input wire m00_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RDATA" *) +input wire [31 : 0] m00_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RRESP" *) +input wire [1 : 0] m00_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RVALID" *) +input wire m00_axi_rvalid; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_m00_axi_aclk_0, NUM_READ_THREADS 1, NUM_WRITE_T\ +HREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RREADY" *) +output wire m00_axi_rready; + + xjtag_axi #( + .JTAG_SEL(3) + ) inst ( + .m00_axi_aclk(m00_axi_aclk), + .m00_axi_aresetn(m00_axi_aresetn), + .m00_axi_awaddr(m00_axi_awaddr), + .m00_axi_awprot(m00_axi_awprot), + .m00_axi_awvalid(m00_axi_awvalid), + .m00_axi_awready(m00_axi_awready), + .m00_axi_wdata(m00_axi_wdata), + .m00_axi_wstrb(m00_axi_wstrb), + .m00_axi_wvalid(m00_axi_wvalid), + .m00_axi_wready(m00_axi_wready), + .m00_axi_bresp(m00_axi_bresp), + .m00_axi_bvalid(m00_axi_bvalid), + .m00_axi_bready(m00_axi_bready), + .m00_axi_araddr(m00_axi_araddr), + .m00_axi_arprot(m00_axi_arprot), + .m00_axi_arvalid(m00_axi_arvalid), + .m00_axi_arready(m00_axi_arready), + .m00_axi_rdata(m00_axi_rdata), + .m00_axi_rresp(m00_axi_rresp), + .m00_axi_rvalid(m00_axi_rvalid), + .m00_axi_rready(m00_axi_rready) + ); +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/2284/src/xjtag_axi.v b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/2284/src/xjtag_axi.v new file mode 100644 index 0000000..2a4ec61 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/2284/src/xjtag_axi.v @@ -0,0 +1,39 @@ + +`timescale 1 ns / 1 ps + + module xjtag_axi # + ( + parameter JTAG_SEL =3 + + ) + ( + // Users to add ports here + // Ports of Axi Master Bus Interface M00_AXI + //input wire m00_axi_init_axi_txn, + //output wire m00_axi_error, + //output wire m00_axi_txn_done, + input wire m00_axi_aclk, + input wire m00_axi_aresetn, + output wire [31 : 0] m00_axi_awaddr, + output wire [2 : 0] m00_axi_awprot, + output wire m00_axi_awvalid, + input wire m00_axi_awready, + output wire [31 : 0] m00_axi_wdata, + output wire [3 : 0] m00_axi_wstrb, + output wire m00_axi_wvalid, + input wire m00_axi_wready, + input wire [1 : 0] m00_axi_bresp, + input wire m00_axi_bvalid, + output wire m00_axi_bready, + output wire [31 : 0] m00_axi_araddr, + output wire [2 : 0] m00_axi_arprot, + output wire m00_axi_arvalid, + input wire m00_axi_arready, + input wire [31 : 0] m00_axi_rdata, + input wire [1 : 0] m00_axi_rresp, + input wire m00_axi_rvalid, + output wire m00_axi_rready + ); + + + endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd new file mode 100644 index 0000000..9dbdb5d --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/8e66/hdl/interrupt_control_v3_1_vh_rfs.vhd @@ -0,0 +1,1430 @@ +------------------------------------------------------------------- +-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +------------------------------------------------------------------- +-- Filename: interrupt_control.vhd +-- +-- Description: This VHDL design file is the parameterized interrupt control +-- module for the ipif which permits parameterizing 1 or 2 levels +-- of interrupt registers. This module has been optimized +-- for the 64 bit wide PLB bus. +-- +-- +-- +------------------------------------------------------------------------------- +-- Structure: +-- +-- interrupt_control.vhd +-- +-- +------------------------------------------------------------------------------- +-- BEGIN_CHANGELOG EDK_I_SP2 +-- +-- Initial Release +-- +-- END_CHANGELOG +------------------------------------------------------------------------------- +-- @BEGIN_CHANGELOG EDK_K_SP3 +-- +-- Updated to use proc_common_v4_0_2 library +-- +-- @END_CHANGELOG +------------------------------------------------------------------------------- +-- Author: Doug Thorpe +-- +-- History: +-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release) +-- Mike Lovejoy Oct 9, 2001 -- V1.01a +-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC. +-- When one source of interrupts Device ISC is redundant and +-- can be eliminated to reduce LUT count. When 7 interrupts +-- are included, the LUT count is reduced from 49 to 17. +-- Also removed the "wrapper" which required redefining +-- ports and generics herein. +-- +-- det Feb-19-02 +-- - Added additional selections of input processing on the IP +-- interrupt inputs. This was done by replacing the +-- C_IP_IRPT_NUM Generic with an unconstrained input array +-- of integers selecting the type of input processing for each +-- bit. +-- +-- det Mar-22-02 +-- - Corrected a reset problem with pos edge detect interrupt +-- input processing (a high on the input when recovering from +-- reset caused an eroneous interrupt to be latched in the IP_ +-- ISR reg. +-- +-- blt Nov-18-02 -- V1.01b +-- - Updated library and use statements to use ipif_common_v1_00_b +-- +-- DET 11/5/2003 v1_00_e +-- ~~~~~~ +-- - Revamped register topology to take advantage of 64 bit wide data bus +-- interface. This required adding the Bus2IP_BE_sa input port to +-- provide byte lane qualifiers for write operations. +-- ^^^^^^ +-- +-- +-- DET 3/25/2004 ipif to v1_00_f +-- ~~~~~~ +-- - Changed proc_common library reference to v2_00_a +-- - Removed ipif_common library reference +-- ^^^^^^ +-- GAB 06/29/2005 v2_00_a +-- ~~~~~~ +-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make +-- a common version that supports 32,64, and 128-Bit Data Bus Widths. +-- - Changed to use ieee.numeric_std library and removed +-- ieee.std_logic_arith.all +-- ^^^^^^ +-- GAB 09/01/2006 v2_00_a +-- ~~~~~~ +-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs +-- - Removed strobe from interrupt enable registers where it was not needed +-- ^^^^^^ +-- GAB 07/02/2008 v3_1 +-- ~~~~~~ +-- - Modified to used proc_common_v4_0_2 library +-- ^^^^^^ +-- ~~~~~~ +-- SK 12/16/12 -- v3.0 +-- 1. up reved to major version for 2013.1 Vivado release. No logic updates. +-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format +-- 3. updated the proc common version to proc_common_v4_0_2 +-- 4. No Logic Updates +-- ^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +-- +-- +------------------------------------------------------------------------------- +-- Special information +-- +-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array +-- of integers. The number of entries specifies how many IP interrupts +-- are to be processed. Each entry in the array specifies the type of input +-- processing for each IP interrupt input. The following table +-- lists the defined values for entries in the array: +-- +-- 1 = Level Pass through (non-inverted input) +-- 2 = Level Pass through (invert input) +-- 3 = Registered Level (non-inverted input) +-- 4 = Registered Level (inverted input) +-- 5 = Rising Edge Detect (non-inverted input) +-- 6 = Falling Edge Detect (non-inverted input) +-- +------------------------------------------------------------------------------- +-- Library definitions + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_misc.all; +use ieee.numeric_std.all; + +library axi_lite_ipif_v3_0_4; +use axi_lite_ipif_v3_0_4.ipif_pkg.all; + +---------------------------------------------------------------------- + +entity interrupt_control is + Generic( + C_NUM_CE : integer range 4 to 16 := 4; + -- Number of register chip enables required + -- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16 + -- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8 + -- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4 + + C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4; + + C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := + ( + 1, -- pass through (non-inverting) + 2 -- pass through (inverting) + ); + -- Interrupt Modes + --1, -- pass through (non-inverting) + --2, -- pass through (inverting) + --3, -- registered level (non-inverting) + --4, -- registered level (inverting) + --5, -- positive edge detect + --6 -- negative edge detect + + C_INCLUDE_DEV_PENCODER : boolean := false; + -- Specifies device Priority Encoder function + + C_INCLUDE_DEV_ISC : boolean := false; + -- Specifies device ISC hierarchy + -- Exclusion of Device ISC requires + -- exclusion of Priority encoder + + C_IPIF_DWIDTH : integer range 32 to 128 := 128 + ); + port( + + -- Inputs From the IPIF Bus + bus2ip_clk : In std_logic; + bus2ip_reset : In std_logic; + bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1); + bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1); + interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1); + interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1); + + -- Interrupt inputs from the IPIF sources that will + -- get registered in this design + ipif_reg_interrupts : In std_logic_vector(0 to 1); + + -- Level Interrupt inputs from the IPIF sources + ipif_lvl_interrupts : In std_logic_vector + (0 to C_NUM_IPIF_IRPT_SRC-1); + + -- Inputs from the IP Interface + ip2bus_intrevent : In std_logic_vector + (0 to C_IP_INTR_MODE_ARRAY'length-1); + + -- Final Device Interrupt Output + intr2bus_devintr : Out std_logic; + + -- Status Reply Outputs to the Bus + intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1); + intr2bus_wrack : Out std_logic; + intr2bus_rdack : Out std_logic; + intr2bus_error : Out std_logic; + intr2bus_retry : Out std_logic; + intr2bus_toutsup : Out std_logic + ); + end interrupt_control; + +------------------------------------------------------------------------------- + +architecture implementation of interrupt_control is + +------------------------------------------------------------------------------- +-- Function max2 +-- +-- This function returns the greater of two numbers. +------------------------------------------------------------------------------- +function max2 (num1, num2 : integer) return integer is +begin + if num1 >= num2 then + return num1; + else + return num2; + end if; +end function max2; + +------------------------------------------------------------------------------- +-- Function declarations +------------------------------------------------------------------------------- + +------------------------------------------------------------------- +-- Function +-- +-- Function Name: get_max_allowed_irpt_width +-- +-- Function Description: +-- This function determines the maximum number of interrupts that +-- can be processed from the User IP based on the IPIF data bus width +-- and the number of interrupt entries desired. +-- +------------------------------------------------------------------- +function get_max_allowed_irpt_width(data_bus_width : integer; + num_intrpts_entered : integer) + return integer is + Variable temp_max : Integer; + begin + If (data_bus_width >= num_intrpts_entered) Then + temp_max := num_intrpts_entered; + else + temp_max := data_bus_width; + End if; + return(temp_max); + +end function get_max_allowed_irpt_width; + +------------------------------------------------------------------------------- +-- Function data_port_map +-- This function will return an index within a 'reg_width' divided port +-- having a width of 'port_width' based on an address 'offset'. +-- For instance if the port_width is 128-bits and the register width +-- reg_width = 32 bits and the register address offset=16 (0x10), this +-- function will return a index of 0. +-- +-- Address Offset Returned Index Return Index Returned Index +-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus) +-- 0x00 0 0 0 +-- 0x04 1 1 0 +-- 0x08 2 0 0 +-- 0x0C 3 1 0 +-- 0x10 0 0 0 +-- 0x14 1 1 0 +-- 0x18 2 0 0 +-- 0x1C 3 1 0 +------------------------------------------------------------------------------- +function data_port_map(offset : integer; + reg_width : integer; + port_width : integer) + return integer is + variable upper_index : integer; + variable vector_range : integer; + variable reg_offset : std_logic_vector(0 to 7); + variable word_offset_i : integer; + begin + + -- Calculate index position to start decoding the address offset + upper_index := log2(port_width/8); + + -- Calculate the number of bits to look at in decoding + -- the address offset + vector_range := max2(1,log2(port_width/reg_width)); + + -- Convert address offset into a std_logic_vector in order to + -- strip out a set of bits for decoding + reg_offset := std_logic_vector(to_unsigned(offset,8)); + + -- Calculate an index representing the word position of + -- a register with respect to the port width. + word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length + - upper_index to (reg_offset'length + - upper_index) + vector_range - 1))); + return word_offset_i; + end data_port_map; + + +------------------------------------------------------------------------------- +-- Type declarations +------------------------------------------------------------------------------- + + -- no Types + +------------------------------------------------------------------------------- +-- Constant declarations +------------------------------------------------------------------------------- + + -- general use constants + Constant LOGIC_LOW : std_logic := '0'; + Constant LOGIC_HIGH : std_logic := '1'; + + + -- figure out if 32 bits wide or 64 bits wide + Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1; + Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32); + + constant BITS_PER_REG : integer := 32; + constant BYTES_PER_REG : integer := BITS_PER_REG/8; + + -- Register Index + Constant DEVICE_ISR_INDEX : integer := 0; + Constant DEVICE_IPR_INDEX : integer := 1; + Constant DEVICE_IER_INDEX : integer := 2; + Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD + Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD + Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD + Constant DEVICE_IIR_INDEX : integer := 6; + Constant DEVICE_GIE_INDEX : integer := 7; + Constant IP_ISR_INDEX : integer := 8; + Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD + Constant IP_IER_INDEX : integer := 10; + Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD + Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD + Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD + Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD + Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD + + -- Chip Enable Selection mapping (applies to RdCE and WrCE inputs) + Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth; + Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth; + Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth; + Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth; + Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth; + Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth; + Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth; + Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth; + Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth; + Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth; + Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth; + Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth; + Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth; + Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth; + Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth; + Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth; + + + -- Register Address Offset + Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG; + Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG; + Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG; + Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG; + Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG; + Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG; + Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG; + Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG; + Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG; + Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG; + Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG; + Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG; + Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG; + Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG; + Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG; + Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG; + + + -- Column Selection mapping (applies to RdCE and WrCE inputs) + Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH); + Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH); + Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH); + Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH); + Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH); + Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH); + Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH); + Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH); + Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH); + Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH); + Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH); + Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH); + Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH); + Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH); + Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH); + Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH); + + -- Generic to constant mapping + Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1; + Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length; + + + -- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1; + + Constant IP_IRPT_HIGH_INDEX : Integer := + get_max_allowed_irpt_width(C_IPIF_DWIDTH, + NUM_USER_DESIRED_IRPTS) + -1; + + + + Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2; + -- (2 level + 1 IP + Number of latched inputs) - 1 + Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1; + + -- Priority encoder support constants + Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits + Constant NO_INTR_VALUE : Integer := 128; + -- no interrupt pending code = "10000000" + +------------------------------------------------------------------------------- +-- Signal declarations +------------------------------------------------------------------------------- + Signal trans_reg_irpts : std_logic_vector(1 downto 0); + Signal trans_lvl_irpts : std_logic_vector + (IPIF_LVL_IRPT_HIGH_INDEX downto 0); + + Signal trans_ip_irpts : std_logic_vector + (IP_IRPT_HIGH_INDEX downto 0); + + Signal edgedtct_ip_irpts : std_logic_vector + (0 to IP_IRPT_HIGH_INDEX); + + signal irpt_read_data : std_logic_vector + (DBUS_WIDTH_MINUS1 downto 0); + Signal irpt_rdack : std_logic; + Signal irpt_wrack : std_logic; + + signal ip_irpt_status_reg : std_logic_vector + (IP_IRPT_HIGH_INDEX downto 0); + + signal ip_irpt_enable_reg : std_logic_vector + (IP_IRPT_HIGH_INDEX downto 0); + + signal ip_irpt_pending_value : std_logic_vector + (IP_IRPT_HIGH_INDEX downto 0); + + Signal ip_interrupt_or : std_logic; + signal ipif_irpt_status_reg : std_logic_vector(1 downto 0); + + signal ipif_irpt_status_value : std_logic_vector + (IPIF_IRPT_HIGH_INDEX downto 0); + + signal ipif_irpt_enable_reg : std_logic_vector + (IPIF_IRPT_HIGH_INDEX downto 0); + + signal ipif_irpt_pending_value : std_logic_vector + (IPIF_IRPT_HIGH_INDEX downto 0); + + Signal ipif_glbl_irpt_enable_reg : std_logic; + Signal ipif_interrupt : std_logic; + Signal ipif_interrupt_or : std_logic; + Signal ipif_pri_encode_present : std_logic; + Signal ipif_priority_encode_value : std_logic_vector + (PRIORITY_ENC_WIDTH-1 downto 0); + + Signal column_sel : std_logic_vector + (0 to LSB_BYTLE_LANE_COL_OFFSET); + + signal interrupt_wrce_strb : std_logic; + signal irpt_wrack_d1 : std_logic; + signal irpt_rdack_d1 : std_logic; +------------------------------------------------------------------------------- +-- Architecture +------------------------------------------------------------------------------- + +begin + + + -- Misc I/O and Signal assignments + + Intr2Bus_DevIntr <= ipif_interrupt; + Intr2Bus_Error <= LOGIC_LOW; + Intr2Bus_Retry <= LOGIC_LOW; + Intr2Bus_ToutSup <= LOGIC_LOW; + + REG_WRACK_PROCESS : process(Bus2IP_Clk) + begin + if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then + if(Bus2IP_Reset = '1')then + irpt_wrack_d1 <= '0'; + Intr2Bus_WrAck <= '0'; + else + irpt_wrack_d1 <= irpt_wrack; + Intr2Bus_WrAck <= interrupt_wrce_strb; + end if; + end if; + end process REG_WRACK_PROCESS; + + interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1; + + + REG_RDACK_PROCESS : process(Bus2IP_Clk) + begin + if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then + if(Bus2IP_Reset = '1')then + irpt_rdack_d1 <= '0'; + Intr2Bus_RdAck <= '0'; + else + irpt_rdack_d1 <= irpt_rdack; + Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1; + end if; + end if; + end process REG_RDACK_PROCESS; + + + ------------------------------------------------------------- + -- Combinational Process + -- + -- Label: ASSIGN_COL + -- + -- Process Description: + -- + -- + ------------------------------------------------------------- + ASSIGN_COL : process (Bus2IP_BE) + begin + + -- Assign the 32-bit column selects from BE inputs + for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop + column_sel(i) <= Bus2IP_BE(i*4); + end loop; + + end process ASSIGN_COL; + + +---------------------------------------------------------------------------------------------------------------- +--- IP Interrupt processing start + + + ------------------------------------------------------------------------------------------ + -- Convert Little endian register to big endian data bus + ------------------------------------------------------------------------------------------ + LITTLE_TO_BIG : process (irpt_read_data) + Begin + + for k in 0 to DBUS_WIDTH_MINUS1 loop + Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus + End loop; + + End process; -- LITTLE_TO_BIG + + + + ------------------------------------------------------------------------------------------ + -- Convert big endian interrupt inputs to Little endian registers + ------------------------------------------------------------------------------------------ + BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts) + Begin + + for i in 0 to 1 loop + trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format + End loop; + + for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop + trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format + End loop; + + for k in 0 to IP_IRPT_HIGH_INDEX loop + trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format + End loop; + + End process; -- BIG_TO_LITTLE + + + + + ------------------------------------------------------------------------------------------ + -- Implement the IP Interrupt Input Processing + ------------------------------------------------------------------------------------------ + DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate + + + + GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or + C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate + + edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index); + + end generate GEN_NON_INVERT_PASS_THROUGH; + + + + GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or + C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate + + edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index)); + + end generate GEN_INVERT_PASS_THROUGH; + + + + + GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate + + Signal irpt_dly1 : std_logic; + Signal irpt_dly2 : std_logic; + + + begin + + REG_THE_IRPTS : process (Bus2IP_Clk) + begin + + If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then + + If (Bus2IP_Reset = '1') Then + + irpt_dly1 <= '1'; -- setting to '1' protects reset transition + irpt_dly2 <= '1'; -- where interrupt inputs are preset high + + Else + + irpt_dly1 <= IP2Bus_IntrEvent(irpt_index); + irpt_dly2 <= irpt_dly1; + + End if; + + else + null; + End if; + + End process; -- REG_THE_IRPTS + + -- now detect rising edge + edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2); + + end generate GEN_POS_EDGE_DETECT; + + + + + + GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate + + Signal irpt_dly1 : std_logic; + Signal irpt_dly2 : std_logic; + + begin + + REG_THE_IRPTS : process (Bus2IP_Clk) + begin + + If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then + + If (Bus2IP_Reset = '1') Then + + irpt_dly1 <= '0'; + irpt_dly2 <= '0'; + + Else + + irpt_dly1 <= IP2Bus_IntrEvent(irpt_index); + irpt_dly2 <= irpt_dly1; + + End if; + + else + null; + End if; + + End process; -- REG_THE_IRPTS + + edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2; + + end generate GEN_NEG_EDGE_DETECT; + + + + GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate + + edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input + + end generate GEN_INVALID_TYPE; + + + End generate DO_IRPT_INPUT; + + + + + -- Generate the IP Interrupt Status register + GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate + + + GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate + + DO_STATUS_BIT : process (Bus2IP_Clk) + Begin + + if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then + + If (Bus2IP_Reset = '1') Then + + ip_irpt_status_reg(irpt_index) <= '0'; + + elsif (Interrupt_WrCE(IP_ISR) = '1' and + column_sel(IP_ISR_COL) = '1' and + interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs + +-- (GAB) + ip_irpt_status_reg(irpt_index) <= + (Bus2IP_Data((BITS_PER_REG * IP_ISR_COL) + +(BITS_PER_REG - 1) + - irpt_index) xor -- toggle bits on write of '1' + ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming + trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits + + + + + + else + ip_irpt_status_reg(irpt_index) <= + ip_irpt_status_reg(irpt_index) or + trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits + + End if; + + Else + null; + End if; + + End process; -- DO_STATUS_BIT + + End generate GEN_REG_STATUS; + + + + + GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or + C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate + + ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index); + + End generate GEN_PASS_THROUGH_STATUS; + + + End generate GEN_IP_IRPT_STATUS_REG; + + + + + ------------------------------------------------------------------------------------------ + -- Implement the IP Interrupt Enable Register Write and Clear Functions + ------------------------------------------------------------------------------------------ + DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk) + Begin + + + if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then + + If (Bus2IP_Reset = '1') Then + + ip_irpt_enable_reg <= (others => '0'); + + elsif (Interrupt_WrCE(IP_IER) = '1' and + column_sel(IP_IER_COL) = '1') then +-- interrupt_wrce_strb = '1') Then + +-- (GAB) + ip_irpt_enable_reg <= Bus2IP_Data + ( (BITS_PER_REG * IP_IER_COL) + +(BITS_PER_REG - 1) + - IP_IRPT_HIGH_INDEX to + + (BITS_PER_REG * IP_IER_COL) + +(BITS_PER_REG - 1) + ); + else + null; -- no change + End if; + + Else + null; + End if; + + End process; -- DO_IP_IRPT_ENABLE_REG + + + + ------------------------------------------------------------------------------------------ + -- Implement the IP Interrupt Enable/Masking function + ------------------------------------------------------------------------------------------ + DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg) + Begin + + for i in 0 to IP_IRPT_HIGH_INDEX loop + ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and + ip_irpt_enable_reg(i); -- enable/mask interrupt bits + End loop; + + End process; -- DO_IP_INTR_ENABLE + + + ------------------------------------------------------------------------------------------ + -- Implement the IP Interrupt 'OR' Functions + ------------------------------------------------------------------------------------------ + DO_IP_INTR_OR : process (ip_irpt_pending_value) + + Variable ip_loop_or : std_logic; + + Begin + + ip_loop_or := '0'; + + for i in 0 to IP_IRPT_HIGH_INDEX loop + ip_loop_or := ip_loop_or or ip_irpt_pending_value(i); + End loop; + + ip_interrupt_or <= ip_loop_or; + + + End process; -- DO_IP_INTR_OR + + +-------------------------------------------------------------------------------------------- +--- IP Interrupt processing end +-------------------------------------------------------------------------------------------- + + +--========================================================================================== + + + +Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate +begin +-------------------------------------------------------------------------------------------- +--- IPIF Interrupt processing Start +-------------------------------------------------------------------------------------------- + + + ------------------------------------------------------------------------------------------ + -- Implement the IPIF Interrupt Status Register Write and Clear Functions + -- This is only 2 bits wide (the only inputs latched at this level...the others just flow + -- through) + ------------------------------------------------------------------------------------------ + DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk) + Begin + + + if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then + + If (Bus2IP_Reset = '1') Then + + ipif_irpt_status_reg <= (others => '0'); + + elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and + column_sel(DEVICE_ISR_COL) = '1' and + interrupt_wrce_strb = '1') Then + + for i in 0 to 1 loop +-- (GAB) + ipif_irpt_status_reg(i) <= (Bus2IP_Data + ( (BITS_PER_REG * DEVICE_ISR_COL) + +(BITS_PER_REG - 1) + - i) xor -- toggle bits on write of '1' + ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming + trans_reg_irpts(i); -- in on non-cleared interrupt bits + End loop; + + else + + for i in 0 to 1 loop + ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i); + -- latch and hold asserted interrupts + End loop; + + End if; + + Else + null; + End if; + + End process; -- DO_IPIF_IRPT_STATUS_REG + + + + DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or) + Begin + + ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg; + ipif_irpt_status_value(2) <= ip_interrupt_or; + + for i in 3 to IPIF_IRPT_HIGH_INDEX loop + ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3); + End loop; + + + End process; -- DO_IPIF_IRPT_STATUS_VALUE + + + + + + ------------------------------------------------------------------------------------------ + -- Implement the IPIF Interrupt Enable Register Write and Clear Functions + ------------------------------------------------------------------------------------------ + DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk) + Begin + + if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then + + If (Bus2IP_Reset = '1') Then + + ipif_irpt_enable_reg <= (others => '0'); + + elsif (Interrupt_WrCE(DEVICE_IER) = '1' and + column_sel(DEVICE_IER_COL) = '1') then +-- interrupt_wrce_strb = '1') Then + +-- (GAB) + ipif_irpt_enable_reg <= Bus2IP_Data + ( + (BITS_PER_REG * DEVICE_IER_COL) + +(BITS_PER_REG - 1) + - IPIF_IRPT_HIGH_INDEX to + + (BITS_PER_REG * DEVICE_IER_COL) + +(BITS_PER_REG - 1) + ); + else + null; -- no change + End if; + + Else + null; + End if; + + End process; -- DO_IPIF_IRPT_ENABLE_REG + + + + ------------------------------------------------------------------------------------------ + -- Implement the IPIF Interrupt Enable/Masking function + ------------------------------------------------------------------------------------------ + DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg) + Begin + + for i in 0 to IPIF_IRPT_HIGH_INDEX loop + ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits + End loop; + + End process; -- DO_IPIF_INTR_ENABLE + + + +end generate Include_Device_ISC_generate; + +Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate +begin + ipif_irpt_status_reg <= (others => '0'); + ipif_irpt_status_value <= (others => '0'); + ipif_irpt_enable_reg <= (others => '0'); + ipif_irpt_pending_value <= (others => '0'); +end generate Initialize_when_not_include_Device_ISC_generate; + + + ------------------------------------------------------------------------------------------ + -- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions + ------------------------------------------------------------------------------------------ + DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk) + Begin + + if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then + + If (Bus2IP_Reset = '1') Then + + ipif_glbl_irpt_enable_reg <= '0'; + + elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and + column_sel(DEVICE_GIE_COL) = '1' )then + --interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs + +-- (GAB) + ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL); + + else + null; -- no change + End if; + + Else + null; + End if; + + End process; -- DO_IPIF_IRPT_MASTER_ENABLE + + + + + + INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate + ------------------------------------------------------------------------------------------ + -- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value + -- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected. + -- This method implies a positional priority of MSB to LSB. + ------------------------------------------------------------------------------------------ + + + ipif_pri_encode_present <= '1'; + + + + DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value) + + Variable irpt_position : Integer; + Variable irpt_detected : Boolean; + Variable loop_count : integer; + + Begin + + loop_count := IPIF_IRPT_HIGH_INDEX + 1; + irpt_position := 0; + irpt_detected := FALSE; + + -- Search through the pending interrupt values starting with the MSB + while (loop_count > 0) loop + + If (ipif_irpt_pending_value(loop_count-1) = '1') Then + irpt_detected := TRUE; + irpt_position := loop_count-1; + else + null; -- do nothing + End if; + + loop_count := loop_count - 1; + + End loop; + + -- now assign the encoder output value to the bit position of the last interrupt encountered + If (irpt_detected) Then + ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH)); + ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function + else + ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH)); + ipif_interrupt_or <= '0'; + End if; + + + + End process; -- DO_PRIORITY_ENCODER + + +end generate INCLUDE_DEV_PRIORITY_ENCODER; + + + + + + +DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate + + + + ipif_pri_encode_present <= '0'; + + + + ipif_priority_encode_value <= (others => '0'); + + + ------------------------------------------------------------------------------------------ + -- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed) + ------------------------------------------------------------------------------------------ + DO_IPIF_INTR_OR : process (ipif_irpt_pending_value) + + Variable ipif_loop_or : std_logic; + + Begin + + ipif_loop_or := '0'; + + for i in 0 to IPIF_IRPT_HIGH_INDEX loop + ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i); + End loop; + + ipif_interrupt_or <= ipif_loop_or; + + End process; -- DO_IPIF_INTR_OR + + +end generate DELETE_DEV_PRIORITY_ENCODER; + + + ------------------------------------------------------------------------------------------- + -- Perform the final Master enable function on the 'ORed' interrupts +OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate + begin + ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg) + begin + ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg; + end process ipif_interrupt_PROCESS; +end generate OR_operation_with_Dev_ISC_generate; + + + +OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate + begin + ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg) + begin + ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg; + end process ipif_interrupt_PROCESS; +end generate OR_operation_withOUT_Dev_ISC_generate; + +----------------------------------------------------------------------------------------------------------- +--- IPIF Interrupt processing end +---------------------------------------------------------------------------------------------------------------- +Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate +begin + GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE, + column_sel + ) + Begin + + irpt_wrack <= ( + Interrupt_WrCE(DEVICE_ISR) and + column_sel(DEVICE_ISR_COL) + ) + or + ( + Interrupt_WrCE(DEVICE_IER) and + column_sel(DEVICE_IER_COL) + ) + or + ( + Interrupt_WrCE(DEVICE_GIE) and + column_sel(DEVICE_GIE_COL) + ) + or + ( + Interrupt_WrCE(IP_ISR) and + column_sel(IP_ISR_COL) + ) + or + ( + Interrupt_WrCE(IP_IER) and + column_sel(IP_IER_COL) + ); + + + End process; -- GEN_WRITE_ACKNOWLEGDGE +end generate Include_Dev_ISC_WrAck_OR_generate; + + + +Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate +begin + GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE, + column_sel + ) + Begin + + irpt_wrack <= + ( + Interrupt_WrCE(DEVICE_GIE) and + column_sel(DEVICE_GIE_COL) + ) + or + ( + Interrupt_WrCE(IP_ISR) and + column_sel(IP_ISR_COL) + ) + or + ( + Interrupt_WrCE(IP_IER) and + column_sel(IP_IER_COL) + ); + + + End process; -- GEN_WRITE_ACKNOWLEGDGE +end generate Exclude_Dev_ISC_WrAck_OR_generate; + + + ----------------------------------------------------------------------------------------------------------- + --- IPIF Bus Data Read Mux and Read Acknowledge generation + ---------------------------------------------------------------------------------------------------------------- +Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate +begin + GET_READ_DATA : process (Interrupt_RdCE, column_sel, + ip_irpt_status_reg, + ip_irpt_enable_reg, + ipif_irpt_pending_value, + ipif_irpt_enable_reg, + ipif_pri_encode_present, + ipif_priority_encode_value, + ipif_irpt_status_value, + ipif_glbl_irpt_enable_reg) + Begin + + irpt_read_data <= (others => '0'); -- default to driving zeroes + + + + If (Interrupt_RdCE(IP_ISR) = '1' + and column_sel(IP_ISR_COL) = '1') Then + + for i in 0 to IP_IRPT_HIGH_INDEX loop +-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values + + irpt_read_data + (i+(C_IPIF_DWIDTH + - (BITS_PER_REG*IP_ISR_COL) + - BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values + + End loop; + + irpt_rdack <= '1'; -- set the acknowledge handshake + + Elsif (Interrupt_RdCE(IP_IER) = '1' + and column_sel(IP_IER_COL) = '1') Then + + for i in 0 to IP_IRPT_HIGH_INDEX loop +-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values + irpt_read_data + (i+(C_IPIF_DWIDTH + - (BITS_PER_REG*IP_IER_COL) + - BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values + + End loop; + + irpt_rdack <= '1'; -- set the acknowledge handshake + + + Elsif (Interrupt_RdCE(DEVICE_ISR) = '1' + and column_sel(DEVICE_ISR_COL) = '1')then + for i in 0 to IPIF_IRPT_HIGH_INDEX loop +-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values + irpt_read_data + (i+(C_IPIF_DWIDTH + - (BITS_PER_REG*DEVICE_ISR_COL) + - BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values + End loop; + irpt_rdack <= '1'; -- set the acknowledge handshake + + Elsif (Interrupt_RdCE(DEVICE_IPR) = '1' + and column_sel(DEVICE_IPR_COL) = '1')then + + for i in 0 to IPIF_IRPT_HIGH_INDEX loop +-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values + + irpt_read_data + (i+(C_IPIF_DWIDTH + - (BITS_PER_REG*DEVICE_IPR_COL) + - BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values + + End loop; + + irpt_rdack <= '1'; -- set the acknowledge handshake + + Elsif (Interrupt_RdCE(DEVICE_IER) = '1' + and column_sel(DEVICE_IER_COL) = '1') Then + + for i in 0 to IPIF_IRPT_HIGH_INDEX loop +-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values + irpt_read_data + (i+(C_IPIF_DWIDTH + - (BITS_PER_REG*DEVICE_IER_COL) + - BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values + End loop; + + irpt_rdack <= '1'; -- set the acknowledge handshake + + Elsif (Interrupt_RdCE(DEVICE_IIR) = '1' + and column_sel(DEVICE_IIR_COL) = '1') Then + +-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values + + irpt_read_data( (C_IPIF_DWIDTH + - (BITS_PER_REG*DEVICE_IIR_COL) + - BITS_PER_REG) + PRIORITY_ENC_WIDTH-1 + downto (C_IPIF_DWIDTH + - (BITS_PER_REG*DEVICE_IIR_COL) + - BITS_PER_REG)) <= ipif_priority_encode_value; + + irpt_rdack <= '1'; -- set the acknowledge handshake + + Elsif (Interrupt_RdCE(DEVICE_GIE) = '1' + and column_sel(DEVICE_GIE_COL) = '1') Then + +-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value + irpt_read_data(C_IPIF_DWIDTH + - (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg; + + irpt_rdack <= '1'; -- set the acknowledge handshake + + else + + irpt_rdack <= '0'; -- don't set the acknowledge handshake + + End if; + + + End process; -- GET_READ_DATA +end generate Include_Dev_ISC_RdAck_OR_generate; + + +Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate +begin + GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg, + ipif_glbl_irpt_enable_reg,column_sel) + Begin + + irpt_read_data <= (others => '0'); -- default to driving zeroes + + + + If (Interrupt_RdCE(IP_ISR) = '1' + and column_sel(IP_ISR_COL) = '1') Then + + for i in 0 to IP_IRPT_HIGH_INDEX loop +-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values + irpt_read_data + (i+(C_IPIF_DWIDTH + - (BITS_PER_REG*IP_ISR_COL) + - BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values + + + End loop; + + irpt_rdack <= '1'; -- set the acknowledge handshake + + Elsif (Interrupt_RdCE(IP_IER) = '1' + and column_sel(IP_IER_COL) = '1') Then + + for i in 0 to IP_IRPT_HIGH_INDEX loop +-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values + irpt_read_data + (i+(C_IPIF_DWIDTH + - (BITS_PER_REG*IP_IER_COL) + - BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values + + End loop; + + irpt_rdack <= '1'; -- set the acknowledge handshake + + Elsif (Interrupt_RdCE(DEVICE_GIE) = '1' + and column_sel(DEVICE_GIE_COL) = '1') Then + +-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value + irpt_read_data(C_IPIF_DWIDTH + - (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg; + + irpt_rdack <= '1'; -- set the acknowledge handshake + + else + + irpt_rdack <= '0'; -- don't set the acknowledge handshake + + End if; + + + End process; -- GET_READ_DATA + +end generate Exclude_Dev_ISC_RdAck_OR_generate; + + + +end implementation; + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd new file mode 100644 index 0000000..8c78442 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/c193/hdl/axi_gpio_v2_0_vh_rfs.vhd @@ -0,0 +1,1911 @@ +------------------------------------------------------------------------------- +-- gpio_core - entity/architecture pair +------------------------------------------------------------------------------- +-- *************************************************************************** +-- DISCLAIMER OF LIABILITY +-- +-- This file contains proprietary and confidential information of +-- Xilinx, Inc. ("Xilinx"), that is distributed under a license +-- from Xilinx, and may be used, copied and/or disclosed only +-- pursuant to the terms of a valid license agreement with Xilinx. +-- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION +-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER +-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT +-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, +-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx +-- does not warrant that functions included in the Materials will +-- meet the requirements of Licensee, or that the operation of the +-- Materials will be uninterrupted or error-free, or that defects +-- in the Materials will be corrected. Furthermore, Xilinx does +-- not warrant or make any representations regarding use, or the +-- results of the use, of the Materials in terms of correctness, +-- accuracy, reliability or otherwise. +-- +-- Xilinx products are not designed or intended to be fail-safe, +-- or for use in any application requiring fail-safe performance, +-- such as life-support or safety devices or systems, Class III +-- medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could +-- lead to death, personal injury or severe property or +-- environmental damage (individually and collectively, "critical +-- applications"). Customer assumes the sole risk and liability +-- of any use of Xilinx products in critical applications, +-- subject only to applicable laws and regulations governing +-- limitations on product liability. +-- +-- Copyright 2009 Xilinx, Inc. +-- All rights reserved. +-- +-- This disclaimer and copyright notice must be retained as part +-- of this file at all times. +-- *************************************************************************** +-- +------------------------------------------------------------------------------- +-- Filename: gpio_core.vhd +-- Version: v1.01a +-- Description: General Purpose I/O for AXI Interface +-- +------------------------------------------------------------------------------- +-- Structure: +-- axi_gpio.vhd +-- -- axi_lite_ipif.vhd +-- -- interrupt_control.vhd +-- -- gpio_core.vhd +-- +------------------------------------------------------------------------------- +-- +-- Author: KSB +-- History: +-- ~~~~~~~~~~~~~~ +-- KSB 09/15/09 +-- ^^^^^^^^^^^^^^ + +-- ~~~~~~~~~~~~~~ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_cmb" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.std_logic_1164.all; + +library lib_cdc_v1_0_2; + +------------------------------------------------------------------------------- +-- Definition of Generics : -- +------------------------------------------------------------------------------- +-- C_DW -- Data width of PLB BUS. +-- C_AW -- Address width of PLB BUS. +-- C_GPIO_WIDTH -- GPIO Data Bus width. +-- C_GPIO2_WIDTH -- GPIO2 Data Bus width. +-- C_INTERRUPT_PRESENT -- GPIO Interrupt. +-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. +-- C_TRI_DEFAULT -- GPIO_TRI Register reset value. +-- C_IS_DUAL -- Dual Channel GPIO. +-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. +-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. +-- C_FAMILY -- XILINX FPGA family +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- Definition of Ports -- +------------------------------------------------------------------------------- +-- Clk -- Input clock +-- Rst -- Reset +-- ABus_Reg -- Bus to IP address +-- BE_Reg -- Bus to IP byte enables +-- DBus_Reg -- Bus to IP data bus +-- RNW_Reg -- Bus to IP read write control +-- GPIO_DBus -- IP to Bus data bus +-- GPIO_xferAck -- GPIO transfer acknowledge +-- GPIO_intr -- GPIO channel 1 interrupt to IPIC +-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC +-- GPIO_Select -- GPIO select +-- +-- GPIO_IO_I -- Channel 1 General purpose I/O in port +-- GPIO_IO_O -- Channel 1 General purpose I/O out port +-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port +-- GPIO2_IO_I -- Channel 2 General purpose I/O in port +-- GPIO2_IO_O -- Channel 2 General purpose I/O out port +-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port +------------------------------------------------------------------------------- + +entity GPIO_Core is + generic + ( + C_DW : integer := 32; + C_AW : integer := 32; + C_GPIO_WIDTH : integer := 32; + C_GPIO2_WIDTH : integer := 32; + C_MAX_GPIO_WIDTH : integer := 32; + C_INTERRUPT_PRESENT : integer := 0; + C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000"; + C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF"; + C_IS_DUAL : integer := 0; + C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 + C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 + C_ALL_INPUTS : integer range 0 to 1 := 0; + C_ALL_INPUTS_2 : integer range 0 to 1 := 0; + C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000"; + C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF"; + C_FAMILY : string := "virtex7" + ); + port + ( + Clk : in std_logic; + Rst : in std_logic; + ABus_Reg : in std_logic_vector(0 to C_AW-1); + BE_Reg : in std_logic_vector(0 to C_DW/8-1); + DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1); + Bus2IP_RdCE : in std_logic_vector (0 to 3); + RNW_Reg : in std_logic; + GPIO_DBus : out std_logic_vector(0 to C_DW-1); + GPIO_xferAck : out std_logic; + GPIO_intr : out std_logic; + GPIO2_intr : out std_logic; + GPIO_Select : in std_logic; + + GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1); + GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1); + GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1); + GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1); + GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1); + GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1) + ); +end entity GPIO_Core; + +------------------------------------------------------------------------------- +-- Architecture section +------------------------------------------------------------------------------- + +architecture IMP of GPIO_Core is + +-- Pragma Added to supress synth warnings +attribute DowngradeIPIdentifiedWarnings: string; +attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; + +---------------------------------------------------------------------- +-- Function for Reduction OR +---------------------------------------------------------------------- + function or_reduce(l : std_logic_vector) return std_logic is + variable v : std_logic := '0'; + begin + for i in l'range loop + v := v or l(i); + end loop; + return v; + end; +--------------------------------------------------------------------- +-- End of Function +------------------------------------------------------------------- + --constant GPIO_G_W : integer = C_GPIO_WIDTH when (C_GPIO_WIDTH > C_GPIO2_WIDTH) else C_GPIO2_; + signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL); + signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL); + signal Read_Reg_Rst : STD_LOGIC; + signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); + signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); + signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1); + signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal or_ints : std_logic_vector(0 to 0); + signal or_ints2 : std_logic_vector(0 to 0); + signal iGPIO_xferAck : STD_LOGIC; + signal gpio_xferAck_Reg : STD_LOGIC; + signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1); + signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal gpio_reg_en : std_logic; + signal reg1, reg2 : std_logic_vector (0 to C_DW-1); + signal reg3, reg4 : std_logic_vector (0 to C_DW-1); + +begin -- architecture IMP + + + reset_zeros <= (others => '0'); + reset2_zeros <= (others => '0'); + + TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate + SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate + dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW); + tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW); + end generate SELECT_BITS_GENERATE; + end generate TIE_DEFAULTS_GENERATE; + + TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate + SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate + dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); + tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); + end generate SELECT_BITS_2_GENERATE; + end generate TIE_DEFAULTS_2_GENERATE; + + + Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or + (GPIO_Select and not RNW_Reg); + gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0'; + + ----------------------------------------------------------------------------- + -- XFER_ACK_PROCESS + ----------------------------------------------------------------------------- + -- Generation of Transfer Ack signal for one clock pulse + ----------------------------------------------------------------------------- + XFER_ACK_PROCESS : process (Clk) is + begin + if (Clk'EVENT and Clk = '1') then + if (Rst = '1') then + iGPIO_xferAck <= '0'; + else + iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg; + if iGPIO_xferAck = '1' then + iGPIO_xferAck <= '0'; + end if; + end if; + end if; + end process XFER_ACK_PROCESS; + + ----------------------------------------------------------------------------- + -- DELAYED_XFER_ACK_PROCESS + ----------------------------------------------------------------------------- + -- Single Reg stage to make Transfer Ack period one clock pulse wide + ----------------------------------------------------------------------------- + DELAYED_XFER_ACK_PROCESS : process (Clk) is + begin + if (Clk'EVENT and Clk = '1') then + if (Rst = '1') then + gpio_xferAck_Reg <= '0'; + else + gpio_xferAck_Reg <= iGPIO_xferAck; + end if; + end if; + end process DELAYED_XFER_ACK_PROCESS; + + GPIO_xferAck <= iGPIO_xferAck; + + ----------------------------------------------------------------------------- + -- Drive GPIO interrupts to '0' when interrupt not present + ----------------------------------------------------------------------------- + + DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate + gpio_intr <= '0'; + gpio2_intr <= '0'; + end generate DONT_GEN_INTERRUPT; + + ---------------------------------------------------------------------------- + -- When only one channel is used, the additional logic for the second + -- channel ports is not present + ----------------------------------------------------------------------------- + Not_Dual : if (C_IS_DUAL = 0) generate + + GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1); + GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1); + + ALLOUT_ND : if (C_ALL_OUTPUTS = 1) generate + READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate + ---------------------------------------------------------------------------- + -- XFER_ACK_PROCESS + ---------------------------------------------------------------------------- + -- Generation of Transfer Ack signal for one clock pulse + ---------------------------------------------------------------------------- + GPIO_DBUS_I_PROC : process(Clk) + begin + if Clk'event and Clk = '1' then + if Read_Reg_Rst = '1' then + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; + reg1(i-C_GPIO_WIDTH+C_DW) <= '0'; + else + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); + reg1(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); + end if; + end if; + end process; + end generate READ_REG_GEN; + + reg2 <= x"FFFFFFFF"; + reg3 <= x"00000000"; + reg4 <= x"FFFFFFFF"; + TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate + GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + end generate TIE_DBUS_GENERATE; + + end generate ALLOUT_ND; + + ALLIN1_ND : if (C_ALL_INPUTS = 1) generate + + READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate + ---------------------------------------------------------------------------- + -- XFER_ACK_PROCESS + ---------------------------------------------------------------------------- + -- Generation of Transfer Ack signal for one clock pulse + ---------------------------------------------------------------------------- + GPIO_DBUS_I_PROC : process(Clk) + begin + if Clk'event and Clk = '1' then + if Read_Reg_Rst = '1' then + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; + reg1(i-C_GPIO_WIDTH+C_DW) <= '0'; + else + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); + reg1(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); + end if; + end if; + end process; + end generate READ_REG_GEN; + + reg2 <= x"FFFFFFFF"; + reg3 <= x"00000000"; + reg4 <= x"FFFFFFFF"; + + TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate + GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + end generate TIE_DBUS_GENERATE; + + end generate ALLIN1_ND; + + ALLOUT0_ND : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate + + READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate + ---------------------------------------------------------------------------- + -- XFER_ACK_PROCESS + ---------------------------------------------------------------------------- + -- Generation of Transfer Ack signal for one clock pulse + ---------------------------------------------------------------------------- + GPIO_DBUS_I_PROC : process(Clk) + begin + if Clk'event and Clk = '1' then + if Read_Reg_Rst = '1' then + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; + reg1(i-C_GPIO_WIDTH+C_DW) <= '0'; + reg2(i-C_GPIO_WIDTH+C_DW) <= '0'; + else + if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0')then + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); + reg1(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); + else + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); + reg2(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); + reg1(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); + end if; + --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); + end if; + end if; + end process; + end generate READ_REG_GEN; + + reg3 <= x"00000000"; + reg4 <= x"FFFFFFFF"; + + TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate + GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + reg2(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + end generate TIE_DBUS_GENERATE; + + end generate ALLOUT0_ND; + + + ----------------------------------------------------------------------------- + -- GPIO_DBUS_PROCESS + ----------------------------------------------------------------------------- + -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on + -- the channel select signals + ----------------------------------------------------------------------------- + -- GPIO_DBus <= GPIO_DBus_i; +with bus2ip_rdce(0 to 3) select +GPIO_DBus(0 to 31) <= reg1 when "1000", + reg2 when "0100", + reg3 when "0010", + reg4 when "0001", + (others=>'0') when others; + + + ----------------------------------------------------------------------------- + -- REG_SELECT_PROCESS + ----------------------------------------------------------------------------- + -- GPIO REGISTER selection decoder for single channel configuration + ----------------------------------------------------------------------------- + --REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is + REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is + begin + gpio_Data_Select(0) <= '0'; + gpio_OE_Select(0) <= '0'; + + --if GPIO_Select = '1' then + if gpio_reg_en = '1' then + if (ABus_Reg(5) = '0') then + case ABus_Reg(6) is -- bit A29 + when '0' => gpio_Data_Select(0) <= '1'; + when '1' => gpio_OE_Select(0) <= '1'; + -- coverage off + when others => null; + -- coverage on + end case; + end if; + end if; + end process REG_SELECT_PROCESS; + + INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync + generic map ( + C_CDC_TYPE => 1, + C_RESET_STATE => 0, + C_SINGLE_BIT => 0, + C_VECTOR_WIDTH => C_GPIO_WIDTH, + C_MTBF_STAGES => 4 + ) + port map ( + prmry_aclk => '0', + prmry_resetn => '0', + prmry_in => '0', + prmry_vect_in => GPIO_IO_I, + + scndry_aclk => Clk, + scndry_resetn => '0', + scndry_out => open, + scndry_vect_out => gpio_io_i_d2 + ); + + + --------------------------------------------------------------------------- + -- GPIO_INDATA_BIRDIR_PROCESS + --------------------------------------------------------------------------- + -- Reading of channel 1 data from Bidirectional GPIO port + -- to GPIO_DATA REGISTER + --------------------------------------------------------------------------- + GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is + begin + if Clk = '1' and Clk'EVENT then + -- gpio_io_i_d1 <= GPIO_IO_I; + -- gpio_io_i_d2 <= gpio_io_i_d1; + gpio_Data_In <= gpio_io_i_d2; + end if; + end process GPIO_INDATA_BIRDIR_PROCESS; + + + + --------------------------------------------------------------------------- + -- GPIO_OUTDATA_PROCESS + --------------------------------------------------------------------------- + -- Writing to Channel 1 GPIO_DATA REGISTER + --------------------------------------------------------------------------- + GPIO_OUTDATA_PROCESS : process(Clk) is + begin + if Clk = '1' and Clk'EVENT then + if (Rst = '1') then + gpio_Data_Out <= dout_default_i; + elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then + for i in 0 to C_GPIO_WIDTH-1 loop + gpio_Data_Out(i) <= DBus_Reg(i); + end loop; + end if; + end if; + end process GPIO_OUTDATA_PROCESS; + + --------------------------------------------------------------------------- + -- READ_MUX_PROCESS + --------------------------------------------------------------------------- + -- Selects GPIO_TRI control or GPIO_DATA Register to be read + --------------------------------------------------------------------------- + READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE, + gpio_OE_Select,gpio_Data_Out) is + begin + Read_Reg_In <= (others => '0'); + if gpio_Data_Select(0) = '1' then + Read_Reg_In <= gpio_Data_In; + --Read_Reg_In <= gpio_Data_In; + elsif gpio_OE_Select(0) = '1' then + Read_Reg_In <= gpio_OE; + end if; + end process READ_MUX_PROCESS; + --------------------------------------------------------------------------- + -- GPIO_OE_PROCESS + --------------------------------------------------------------------------- + -- Writing to Channel 1 GPIO_TRI Control REGISTER + --------------------------------------------------------------------------- + GPIO_OE_PROCESS : process(Clk) is + begin + + if Clk = '1' and Clk'EVENT then + if (Rst = '1') then + gpio_OE <= tri_default_i; + elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then + for i in 0 to C_GPIO_WIDTH-1 loop + gpio_OE(i) <= DBus_Reg(i); + end loop; + end if; + end if; + end process GPIO_OE_PROCESS; + + GPIO_IO_O <= gpio_Data_Out; + GPIO_IO_T <= gpio_OE; + + + ---------------------------------------------------------------------------- + -- INTERRUPT IS PRESENT + ---------------------------------------------------------------------------- + -- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether + -- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In + -- port + ---------------------------------------------------------------------------- + + GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate + gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; + + ------------------------------------------------------------------------- + -- An interrupt conditon exists if there is a change on any bit. + ------------------------------------------------------------------------- + or_ints(0) <= or_reduce(gpio_data_in_xor_reg); + + ------------------------------------------------------------------------- + -- Registering Interrupt condition + ------------------------------------------------------------------------- + REGISTER_XOR_INTR : process (Clk) is + begin + if (Clk'EVENT and Clk = '1') then + if (Rst = '1') then + gpio_data_in_xor_reg <= reset_zeros; + GPIO_intr <= '0'; + else + gpio_data_in_xor_reg <= gpio_data_in_xor; + GPIO_intr <= or_ints(0); + end if; + end if; + end process REGISTER_XOR_INTR; + + gpio2_intr <= '0'; -- Channel 2 interrupt is driven low + + end generate GEN_INTERRUPT; + + end generate Not_Dual; + + ---)(------------------------------------------------------------------------ + -- When both the channels are used, the additional logic for the second + -- channel ports + ----------------------------------------------------------------------------- + Dual : if (C_IS_DUAL = 1) generate + signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); + signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); + signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1); + signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1); + begin + + + ALLOUT0_ND_G0 : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate + + READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate + ---------------------------------------------------------------------------- + -- XFER_ACK_PROCESS + ---------------------------------------------------------------------------- + -- Generation of Transfer Ack signal for one clock pulse + ---------------------------------------------------------------------------- + GPIO_DBUS_I_PROC : process(Clk) + begin + if Clk'event and Clk = '1' then + if Read_Reg_Rst = '1' then + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; + reg1(i-C_GPIO_WIDTH+C_DW) <= '0'; + reg2(i-C_GPIO_WIDTH+C_DW) <= '0'; + else + if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0') then + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); + reg1(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); + else + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); + reg2(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); + reg1(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); + end if; + --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); + end if; + end if; + end process; + end generate READ_REG_GEN; + + + TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate + GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + reg2(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + end generate TIE_DBUS_GENERATE; + + end generate ALLOUT0_ND_G0; + + ALLIN0_ND_G0 : if (C_ALL_INPUTS = 1) generate + + READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate + ---------------------------------------------------------------------------- + -- XFER_ACK_PROCESS + ---------------------------------------------------------------------------- + -- Generation of Transfer Ack signal for one clock pulse + ---------------------------------------------------------------------------- + GPIO_DBUS_I_PROC : process(Clk) + begin + if Clk'event and Clk = '1' then + if Read_Reg_Rst = '1' then + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; + reg1(i-C_GPIO_WIDTH+C_DW) <= '0'; + else + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); + reg1(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); + end if; + end if; + end process; + end generate READ_REG_GEN; + + TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate + GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + end generate TIE_DBUS_GENERATE; + + reg2 <= (others => '1'); + + end generate ALLIN0_ND_G0; + + ALLOUT0_ND_G1 : if (C_ALL_OUTPUTS = 1) generate + + READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate + begin + -------------------------------------------------------------------------- + -- GPIO_DBUS_I_PROCESS + -------------------------------------------------------------------------- + -- This process generates the GPIO CHANNEL1 DATA BUS + -------------------------------------------------------------------------- + GPIO_DBUS_I_PROC : process(Clk) + begin + if Clk'event and Clk = '1' then + if Read_Reg_Rst = '1' then + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; + reg1(i-C_GPIO_WIDTH+C_DW) <= '0'; + else + GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); + reg1(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); + end if; + end if; + end process; + end generate READ_REG_GEN; + reg2 <= (others => '1'); + TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate + GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); + end generate TIE_DBUS_GENERATE; + end generate ALLOUT0_ND_G1; + + + ALLIN0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 1) generate + + READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate + -------------------------------------------------------------------------- + -- GPIO2_DBUS_I_PROCESS + -------------------------------------------------------------------------- + -- This process generates the GPIO CHANNEL2 DATA BUS + -------------------------------------------------------------------------- + GPIO2_DBUS_I_PROC : process(Clk) + begin + if Clk'event and Clk = '1' then + if Read_Reg_Rst = '1' then + GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; + reg3(i-C_GPIO2_WIDTH+C_DW) <= '0'; + else + GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); + reg3(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); + --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); + end if; + end if; + end process; + end generate READ_REG2_GEN; + + reg4 <= (others => '1'); + + TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate + GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); + reg3(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); + end generate TIE_DBUS2_GENERATE; + end generate ALLIN0_ND_G2; + + ALLOUT0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 0) generate + + READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate + -------------------------------------------------------------------------- + -- GPIO2_DBUS_I_PROCESS + -------------------------------------------------------------------------- + -- This process generates the GPIO CHANNEL2 DATA BUS + -------------------------------------------------------------------------- + GPIO2_DBUS_I_PROC : process(Clk) + begin + if Clk'event and Clk = '1' then + if Read_Reg_Rst = '1' then + GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; + reg3(i-C_GPIO2_WIDTH+C_DW) <= '0'; + reg4(i-C_GPIO2_WIDTH+C_DW) <= '0'; + else + if (gpio2_OE(i) = '0' and gpio_OE_Select(1) = '0') then + GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); + reg3(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); + else + GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); + reg4(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); + reg3(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); + end if; + -- GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i) when (gpio2_OE(i) = '1') else Read_Reg2_In(i); + --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); + end if; + end if; + end process; + end generate READ_REG2_GEN; + TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate + GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); + reg3(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); + reg4(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); + end generate TIE_DBUS2_GENERATE; + end generate ALLOUT0_ND_G2; + + ALLOUT1_ND_G2 : if (C_ALL_OUTPUTS_2 = 1) generate + + READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate + -------------------------------------------------------------------------- + -- GPIO2_DBUS_I_PROCESS + -------------------------------------------------------------------------- + -- This process generates the GPIO CHANNEL2 DATA BUS + -------------------------------------------------------------------------- + GPIO2_DBUS_I_PROC : process(Clk) + begin + if Clk'event and Clk = '1' then + if Read_Reg_Rst = '1' then + GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; + reg3(i-C_GPIO2_WIDTH+C_DW) <= '0'; + else + GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); + reg3(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); + end if; + end if; + end process; + end generate READ_REG2_GEN; + reg4 <= (others => '1'); + TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate + GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); + reg3(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); + end generate TIE_DBUS2_GENERATE; + end generate ALLOUT1_ND_G2; + + + --------------------------------------------------------------------------- + -- GPIO_DBUS_PROCESS + --------------------------------------------------------------------------- + -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and + -- GPIO2_DBUS_I based on which channel is selected + --------------------------------------------------------------------------- +-- GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or +-- (gpio_OE_Select(0) = '1')) and (RNW_Reg = '1')) +-- else GPIO2_DBus_i; + +with bus2ip_rdce(0 to 3) select +GPIO_DBus(0 to 31) <= reg1 when "1000", + reg2 when "0100", + reg3 when "0010", + reg4 when "0001", + (others=>'0') when others; + ----------------------------------------------------------------------------- + -- DUAL_REG_SELECT_PROCESS + ----------------------------------------------------------------------------- + -- GPIO REGISTER selection decoder for Dual channel configuration + ----------------------------------------------------------------------------- + --DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is + DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is + variable ABus_reg_select : std_logic_vector(0 to 1); + begin + ABus_reg_select := ABus_Reg(5 to 6); + gpio_Data_Select <= (others => '0'); + gpio_OE_Select <= (others => '0'); + --if GPIO_Select = '1' then + if gpio_reg_en = '1' then + -- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual + case ABus_reg_select is -- bit A28,A29 for dual + when "00" => gpio_Data_Select(0) <= '1'; + when "01" => gpio_OE_Select(0) <= '1'; + when "10" => gpio_Data_Select(1) <= '1'; + when "11" => gpio_OE_Select(1) <= '1'; + -- coverage off + when others => null; + -- coverage on + end case; + end if; + end process DUAL_REG_SELECT_PROCESS; + --------------------------------------------------------------------------- + -- GPIO_INDATA_BIRDIR_PROCESS + --------------------------------------------------------------------------- + -- Reading of channel 1 data from Bidirectional GPIO port + -- to GPIO_DATA REGISTER + --------------------------------------------------------------------------- + + INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync + generic map ( + C_CDC_TYPE => 1, + C_RESET_STATE => 0, + C_SINGLE_BIT => 0, + C_VECTOR_WIDTH => C_GPIO_WIDTH, + C_MTBF_STAGES => 4 + ) + port map ( + prmry_aclk => '0', + prmry_resetn => '0', + prmry_in => '0', + prmry_vect_in => GPIO_IO_I, + + scndry_aclk => Clk, + scndry_resetn => '0', + scndry_out => open, + scndry_vect_out => gpio_io_i_d2 + ); + + + GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is + begin + if Clk = '1' and Clk'EVENT then + -- gpio_io_i_d1 <= GPIO_IO_I; + -- gpio_io_i_d2 <= gpio_io_i_d1; + --if (C_ALL_OUTPUTS = '1') then + -- gpio_Data_In <= gpio_Data_Out; + -- else + gpio_Data_In <= gpio_io_i_d2; + -- end if; + end if; + end process GPIO_INDATA_BIRDIR_PROCESS; + + INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync + generic map ( + C_CDC_TYPE => 1, + C_RESET_STATE => 0, + C_SINGLE_BIT => 0, + C_VECTOR_WIDTH => C_GPIO2_WIDTH, + C_MTBF_STAGES => 4 + ) + port map ( + prmry_aclk => '0', + prmry_resetn => '0', + prmry_in => '0', + prmry_vect_in => GPIO2_IO_I, + + scndry_aclk => Clk, + scndry_resetn => '0', + scndry_out => open, + scndry_vect_out => gpio2_io_i_d2 + ); + --------------------------------------------------------------------------- + -- GPIO2_INDATA_BIRDIR_PROCESS + --------------------------------------------------------------------------- + -- Reading of channel 2 data from Bidirectional GPIO2 port + -- to GPIO2_DATA REGISTER + --------------------------------------------------------------------------- + GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is + begin + if Clk = '1' and Clk'EVENT then + -- gpio2_io_i_d1 <= GPIO2_IO_I; + -- gpio2_io_i_d2 <= gpio2_io_i_d1; + -- if (C_ALL_OUTPUTS = '1') then + -- gpio2_Data_In <= gpio2_Data_Out; + -- else + gpio2_Data_In <= gpio2_io_i_d2; + -- end if; + end if; + end process GPIO2_INDATA_BIRDIR_PROCESS; + + + --------------------------------------------------------------------------- + -- GPIO_OUTDATA_PROCESS_0_0 + --------------------------------------------------------------------------- + -- Writing to Channel 1 GPIO_DATA REGISTER + --------------------------------------------------------------------------- + GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is + begin + if Clk = '1' and Clk'EVENT then + if (Rst = '1') then + gpio_Data_Out <= dout_default_i; + elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then + for i in 0 to C_GPIO_WIDTH-1 loop + gpio_Data_Out(i) <= DBus_Reg(i); + end loop; + end if; + end if; + end process GPIO_OUTDATA_PROCESS_0_0; + + --------------------------------------------------------------------------- + -- GPIO_OE_PROCESS_0_0 + --------------------------------------------------------------------------- + -- Writing to Channel 1 GPIO_TRI Control REGISTER + --------------------------------------------------------------------------- + GPIO_OE_PROCESS : process(Clk) is + begin + + if Clk = '1' and Clk'EVENT then + if (Rst = '1') then + gpio_OE <= tri_default_i; + elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then + for i in 0 to C_GPIO_WIDTH-1 loop + gpio_OE(i) <= DBus_Reg(i); +-- end if; + end loop; + end if; + end if; + end process GPIO_OE_PROCESS; + + + --------------------------------------------------------------------------- + -- GPIO2_OUTDATA_PROCESS_0_0 + --------------------------------------------------------------------------- + -- Writing to Channel 2 GPIO2_DATA REGISTER + --------------------------------------------------------------------------- + GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is + begin + if Clk = '1' and Clk'EVENT then + if (Rst = '1') then + gpio2_Data_Out <= dout2_default_i; + elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then + for i in 0 to C_GPIO2_WIDTH-1 loop + gpio2_Data_Out(i) <= DBus_Reg(i); + -- end if; + end loop; + end if; + end if; + end process GPIO2_OUTDATA_PROCESS_0_0; + + --------------------------------------------------------------------------- + -- GPIO2_OE_PROCESS_0_0 + --------------------------------------------------------------------------- + -- Writing to Channel 2 GPIO2_TRI Control REGISTER + --------------------------------------------------------------------------- + GPIO2_OE_PROCESS_0_0 : process(Clk) is + begin + if Clk = '1' and Clk'EVENT then + if (Rst = '1') then + gpio2_OE <= tri2_default_i; + elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then + for i in 0 to C_GPIO2_WIDTH-1 loop + gpio2_OE(i) <= DBus_Reg(i); + end loop; + end if; + end if; + end process GPIO2_OE_PROCESS_0_0; + + GPIO_IO_O <= gpio_Data_Out; + GPIO_IO_T <= gpio_OE; + + GPIO2_IO_O <= gpio2_Data_Out; + GPIO2_IO_T <= gpio2_OE; + --------------------------------------------------------------------------- + -- READ_MUX_PROCESS_0_0 + --------------------------------------------------------------------------- + -- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA + -- GPIO2_TRI REGISTERS for reading + --------------------------------------------------------------------------- + READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In, + gpio_Data_Select, gpio_OE, + gpio_OE_Select,gpio_Data_Out,gpio2_Data_Out) is + begin + Read_Reg_In <= (others => '0'); + Read_Reg2_In <= (others => '0'); + if gpio_Data_Select(0) = '1' then + Read_Reg_In <= gpio_Data_In; + --Read_Reg_In <= gpio_Data_In; + elsif gpio_OE_Select(0) = '1' then + Read_Reg_In <= gpio_OE; + elsif gpio_Data_Select(1) = '1' then + Read_Reg2_In <= gpio2_Data_In; + --Read_Reg2_In <= gpio2_Data_In; + --Read_Reg2_In<= gpio2_Data_In; + elsif gpio_OE_Select(1) = '1' then + Read_Reg2_In <= gpio2_OE; + end if; + end process READ_MUX_PROCESS_0_0; + + --------------------------------------------------------------------------- + -- INTERRUPT IS PRESENT + --------------------------------------------------------------------------- + gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate + + gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; + gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2; + + + ------------------------------------------------------------------------- + -- An interrupt conditon exists if there is a change any bit. + ------------------------------------------------------------------------- + or_ints(0) <= or_reduce(gpio_data_in_xor_reg); + or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg); + + ------------------------------------------------------------------------- + -- Registering Interrupt condition + ------------------------------------------------------------------------- + REGISTER_XORs_INTRs : process (Clk) is + begin + if (Clk'EVENT and Clk = '1') then + if (Rst = '1') then + gpio_data_in_xor_reg <= reset_zeros; + gpio2_data_in_xor_reg <= reset2_zeros; + GPIO_intr <= '0'; + GPIO2_intr <= '0'; + else + gpio_data_in_xor_reg <= gpio_data_in_xor; + gpio2_data_in_xor_reg <= gpio2_data_in_xor; + GPIO_intr <= or_ints(0); + GPIO2_intr <= or_ints2(0); + end if; + end if; + end process REGISTER_XORs_INTRs; + + + end generate gen_interrupt_dual; + + end generate Dual; + + +end architecture IMP; + + +------------------------------------------------------------------------------- +-- AXI_GPIO - entity/architecture pair +------------------------------------------------------------------------------- +-- +-- *************************************************************************** +-- DISCLAIMER OF LIABILITY +-- +-- This file contains proprietary and confidential information of +-- Xilinx, Inc. ("Xilinx"), that is distributed under a license +-- from Xilinx, and may be used, copied and/or disclosed only +-- pursuant to the terms of a valid license agreement with Xilinx. +-- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION +-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER +-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT +-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, +-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx +-- does not warrant that functions included in the Materials will +-- meet the requirements of Licensee, or that the operation of the +-- Materials will be uninterrupted or error-free, or that defects +-- in the Materials will be corrected. Furthermore, Xilinx does +-- not warrant or make any representations regarding use, or the +-- results of the use, of the Materials in terms of correctness, +-- accuracy, reliability or otherwise. +-- +-- Xilinx products are not designed or intended to be fail-safe, +-- or for use in any application requiring fail-safe performance, +-- such as life-support or safety devices or systems, Class III +-- medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could +-- lead to death, personal injury or severe property or +-- environmental damage (individually and collectively, "critical +-- applications"). Customer assumes the sole risk and liability +-- of any use of Xilinx products in critical applications, +-- subject only to applicable laws and regulations governing +-- limitations on product liability. +-- +-- Copyright 2009 Xilinx, Inc. +-- All rights reserved. +-- +-- This disclaimer and copyright notice must be retained as part +-- of this file at all times. +-- *************************************************************************** +-- +------------------------------------------------------------------------------- +-- Filename: axi_gpio.vhd +-- Version: v2.0 +-- Description: General Purpose I/O for AXI Interface +-- +------------------------------------------------------------------------------- +-- Structure: +-- axi_gpio.vhd +-- -- axi_lite_ipif.vhd +-- -- interrupt_control.vhd +-- -- gpio_core.vhd +------------------------------------------------------------------------------- +-- Author: KSB +-- History: +-- ~~~~~~~~~~~~~~ +-- KSB 07/28/09 +-- ^^^^^^^^^^^^^^ +-- First version of axi_gpio. Based on xps_gpio 2.00a +-- +-- KSB 05/20/10 +-- ^^^^^^^^^^^^^^ +-- Updated for holes in address range +-- ~~~~~~~~~~~~~~ +-- VB 09/23/10 +-- ^^^^^^^^^^^^^^ +-- Updated for axi_lite_ipfi_v1_01_a +-- ~~~~~~~~~~~~~~ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_cmb" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +use ieee.std_logic_misc.all; +use std.textio.all; +------------------------------------------------------------------------------- +-- AXI common package of the proc common library is used for different +-- function declarations +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- axi_gpio_v2_0_19 library is used for axi4 component declarations +------------------------------------------------------------------------------- +library axi_lite_ipif_v3_0_4; +use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce; +use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE; +use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE; + +------------------------------------------------------------------------------- +-- axi_gpio_v2_0_19 library is used for interrupt controller component +-- declarations +------------------------------------------------------------------------------- + +library interrupt_control_v3_1_4; + +------------------------------------------------------------------------------- +-- axi_gpio_v2_0_19 library is used for axi_gpio component declarations +------------------------------------------------------------------------------- + +library axi_gpio_v2_0_19; + +------------------------------------------------------------------------------- +-- Defination of Generics : -- +------------------------------------------------------------------------------- +-- AXI generics +-- C_BASEADDR -- Base address of the core +-- C_HIGHADDR -- Permits alias of address space +-- by making greater than xFFF +-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits) +-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits) + +-- C_FAMILY -- XILINX FPGA family +-- C_INSTANCE -- Instance name ot the core in the EDK system + +-- C_GPIO_WIDTH -- GPIO Data Bus width. +-- C_ALL_INPUTS -- Inputs Only. +-- C_INTERRUPT_PRESENT -- GPIO Interrupt. +-- C_IS_BIDIR -- Selects gpio_io_i as input. +-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. +-- C_TRI_DEFAULT -- GPIO_TRI Register reset value. +-- C_IS_DUAL -- Dual Channel GPIO. +-- C_ALL_INPUTS_2 -- Channel2 Inputs only. +-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input. +-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. +-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Defination of Ports -- +------------------------------------------------------------------------------- +-- AXI signals +-- s_axi_awaddr -- AXI Write address +-- s_axi_awvalid -- Write address valid +-- s_axi_awready -- Write address ready +-- s_axi_wdata -- Write data +-- s_axi_wstrb -- Write strobes +-- s_axi_wvalid -- Write valid +-- s_axi_wready -- Write ready +-- s_axi_bresp -- Write response +-- s_axi_bvalid -- Write response valid +-- s_axi_bready -- Response ready +-- s_axi_araddr -- Read address +-- s_axi_arvalid -- Read address valid +-- s_axi_arready -- Read address ready +-- s_axi_rdata -- Read data +-- s_axi_rresp -- Read response +-- s_axi_rvalid -- Read valid +-- s_axi_rready -- Read ready + +-- GPIO Signals +-- gpio_io_i -- Channel 1 General purpose I/O in port +-- gpio_io_o -- Channel 1 General purpose I/O out port +-- gpio_io_t -- Channel 1 General purpose I/O + -- TRI-STATE control port +-- gpio2_io_i -- Channel 2 General purpose I/O in port +-- gpio2_io_o -- Channel 2 General purpose I/O out port +-- gpio2_io_t -- Channel 2 General purpose I/O + -- TRI-STATE control port +-- System Signals +-- s_axi_aclk -- AXI Clock +-- s_axi_aresetn -- AXI Reset +-- ip2intc_irpt -- AXI GPIO Interrupt + +------------------------------------------------------------------------------- + +entity axi_gpio is + generic + ( +-- -- System Parameter + + C_FAMILY : string := "virtex7"; + +-- -- AXI Parameters + C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9; + C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32; + +-- -- GPIO Parameter + C_GPIO_WIDTH : integer range 1 to 32 := 32; + C_GPIO2_WIDTH : integer range 1 to 32 := 32; + C_ALL_INPUTS : integer range 0 to 1 := 0; + C_ALL_INPUTS_2 : integer range 0 to 1 := 0; + + C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 + C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 + + C_INTERRUPT_PRESENT : integer range 0 to 1 := 0; + C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000"; + C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF"; + C_IS_DUAL : integer range 0 to 1 := 0; + C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000"; + C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF" + ); + port + ( + -- AXI interface Signals -------------------------------------------------- + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 + downto 0); + s_axi_awvalid : in std_logic; + s_axi_awready : out std_logic; + + s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 + downto 0); + s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 + downto 0); + s_axi_wvalid : in std_logic; + s_axi_wready : out std_logic; + + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_bready : in std_logic; + + s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 + downto 0); + s_axi_arvalid : in std_logic; + s_axi_arready : out std_logic; + + s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 + downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic; + + -- Interrupt--------------------------------------------------------------- + ip2intc_irpt : out std_logic; + + -- GPIO Signals------------------------------------------------------------ + gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0); + gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); + gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); + gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0); + gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0); + gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0) + ); + +------------------------------------------------------------------------------- +-- fan-out attributes for XST +------------------------------------------------------------------------------- + + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of s_axi_aclk : signal is "10000"; + attribute MAX_FANOUT of s_axi_aresetn : signal is "10000"; +------------------------------------------------------------------------------- +-- Attributes for MPD file +------------------------------------------------------------------------------- + attribute IP_GROUP : string ; + attribute IP_GROUP of axi_gpio : entity is "LOGICORE"; + attribute SIGIS : string ; + attribute SIGIS of s_axi_aclk : signal is "Clk"; + attribute SIGIS of s_axi_aresetn : signal is "Rst"; + attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH"; + +end entity axi_gpio; +------------------------------------------------------------------------------- +-- Architecture Section +------------------------------------------------------------------------------- + +architecture imp of axi_gpio is + +-- Pragma Added to supress synth warnings +attribute DowngradeIPIdentifiedWarnings: string; +attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; +------------------------------------------------------------------------------- +-- constant added for webtalk information +------------------------------------------------------------------------------- +--function chr(sl: std_logic) return character is +-- variable c: character; +-- begin +-- case sl is +-- when '0' => c:= '0'; +-- when '1' => c:= '1'; +-- when 'Z' => c:= 'Z'; +-- when 'U' => c:= 'U'; +-- when 'X' => c:= 'X'; +-- when 'W' => c:= 'W'; +-- when 'L' => c:= 'L'; +-- when 'H' => c:= 'H'; +-- when '-' => c:= '-'; +-- end case; +-- return c; +-- end chr; +-- +--function str(slv: std_logic_vector) return string is +-- variable result : string (1 to slv'length); +-- variable r : integer; +-- begin +-- r := 1; +-- for i in slv'range loop +-- result(r) := chr(slv(i)); +-- r := r + 1; +-- end loop; +-- return result; +-- end str; + +type bo2na_type is array (boolean) of natural; -- boolean to + --natural conversion +constant bo2na : bo2na_type := (false => 0, true => 1); + +------------------------------------------------------------------------------- +-- Function Declarations +------------------------------------------------------------------------------- +type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean; + +---------------------------------------------------------------------------- +-- This function returns the number of elements that are true in +-- a boolean array. +---------------------------------------------------------------------------- +function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is + variable n : natural := 0; +begin + for i in ba'range loop + n := n + bo2na(ba(i)); + end loop; + return n; +end; + +---------------------------------------------------------------------------- +-- This function returns a num_ce integer array that is constructed by +-- taking only those elements of superset num_ce integer array +-- that will be defined by the current case. +-- The superset num_ce array is given by parameter num_ce_by_ard. +-- The current case the ard elements that will be used is given +-- by parameter defined_ards. +---------------------------------------------------------------------------- +function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE; + num_ce_by_ard : INTEGER_ARRAY_TYPE + ) return INTEGER_ARRAY_TYPE is + variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0); + variable i : natural := 0; + variable j : natural := defined_ards'left; +begin + while i /= res'length loop + -- coverage off + while defined_ards(j) = false loop + j := j+1; + end loop; + -- coverage on + res(i) := num_ce_by_ard(j); + i := i+1; + j := j+1; + end loop; + return res; +end; + + +---------------------------------------------------------------------------- +-- This function returns a addr_range array that is constructed by +-- taking only those elements of superset addr_range array +-- that will be defined by the current case. +-- The superset addr_range array is given by parameter addr_range_by_ard. +-- The current case the ard elements that will be used is given +-- by parameter defined_ards. +---------------------------------------------------------------------------- +function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE; + addr_range_by_ard : SLV64_ARRAY_TYPE + ) return SLV64_ARRAY_TYPE is + variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1); + variable i : natural := 0; + variable j : natural := defined_ards'left; +begin + while i /= res'length loop + -- coverage off + while defined_ards(j) = false loop + j := j+1; + end loop; + -- coverage on + res(i) := addr_range_by_ard(2*j); + res(i+1) := addr_range_by_ard((2*j)+1); + i := i+2; + j := j+1; + end loop; + return res; +end; + +function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE + ) return std_logic_vector is + variable res : std_logic_vector(0 to 31); +begin + res := (others => '0'); + if defined_ards(defined_ards'right) then + res(0 to 3) := "1111"; + res(12) := '1'; + res(13) := '1'; + res(15) := '1'; + else + res(0 to 3) := "1111"; + end if; + return res; +end; + +---------------------------------------------------------------------------- +-- This function returns the maximum width amongst the two GPIO Channels +-- and if there is only one channel, it returns just the width of that +-- channel. +---------------------------------------------------------------------------- +function max_width( dual_channel : INTEGER; + channel1_width : INTEGER; + channel2_width : INTEGER + ) return INTEGER is +begin + if (dual_channel = 0) then + return channel1_width; + else + if (channel1_width > channel2_width) then + return channel1_width; + else + return channel2_width; + end if; + end if; + +end; + + +------------------------------------------------------------------------------- +-- Constant Declarations +------------------------------------------------------------------------------- +constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; +constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := + (others => '0'); + +constant INTR_TYPE : integer := 5; + +constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100"; +constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF"; +constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F"; + +constant MAX_GPIO_WIDTH : integer := max_width + (C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH); + + +constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := + qual_ard_addr_range_array( + (true,C_INTERRUPT_PRESENT=1), + (ZERO_ADDR_PAD & X"00000000", + ZERO_ADDR_PAD & GPIO_HIGHADDR, + ZERO_ADDR_PAD & INTR_BASEADDR, + ZERO_ADDR_PAD & INTR_HIGHADDR + ) + ); + +constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := + qual_ard_num_ce_array( + (true,C_INTERRUPT_PRESENT=1), + (4,16) + ); + +constant ARD_CE_VALID : std_logic_vector(0 to 31) := + qual_ard_ce_valid( + (true,C_INTERRUPT_PRESENT=1) + ); + +constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1)) + := (others => 5); + +constant C_USE_WSTRB : integer := 0; +constant C_DPHASE_TIMEOUT : integer := 8; + +------------------------------------------------------------------------------- +-- Signal and Type Declarations +------------------------------------------------------------------------------- + +signal ip2bus_intrevent : std_logic_vector(0 to 1); + +signal GPIO_xferAck_i : std_logic; +signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); +signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); +signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); +-- IPIC Used Signals + +signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); + +signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1); +signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); +signal bus2ip_rnw : std_logic; +signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na + (C_INTERRUPT_PRESENT=1)); +signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); +signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); + +signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15); +signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15); +signal intr_wr_ce_or_reduce : std_logic; +signal intr_rd_ce_or_reduce : std_logic; +signal ip2Bus_RdAck_intr_reg_hole : std_logic; +signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic; +signal ip2Bus_WrAck_intr_reg_hole : std_logic; +signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic; + + + +signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1); +signal bus2ip_clk : std_logic; +signal bus2ip_reset : std_logic; +signal bus2ip_resetn : std_logic; +signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); +signal intr2bus_wrack : std_logic; +signal intr2bus_rdack : std_logic; +signal intr2bus_error : std_logic; + +signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); +signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); +signal ip2bus_wrack_i : std_logic; +signal ip2bus_wrack_i_D1 : std_logic; +signal ip2bus_rdack_i : std_logic; +signal ip2bus_rdack_i_D1 : std_logic; +signal ip2bus_error_i : std_logic; +signal IP2INTC_Irpt_i : std_logic; + +------------------------------------------------------------------------------- +-- Architecture +------------------------------------------------------------------------------- + +begin -- architecture IMP + + + AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif + generic map + ( + C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, + C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, + C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE, + C_USE_WSTRB => C_USE_WSTRB, + C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, + C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, + C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, + C_FAMILY => C_FAMILY + ) + port map + ( + S_AXI_ACLK => s_axi_aclk, + S_AXI_ARESETN => s_axi_aresetn, + S_AXI_AWADDR => s_axi_awaddr, + S_AXI_AWVALID => s_axi_awvalid, + S_AXI_AWREADY => s_axi_awready, + S_AXI_WDATA => s_axi_wdata, + S_AXI_WSTRB => s_axi_wstrb, + S_AXI_WVALID => s_axi_wvalid, + S_AXI_WREADY => s_axi_wready, + S_AXI_BRESP => s_axi_bresp, + S_AXI_BVALID => s_axi_bvalid, + S_AXI_BREADY => s_axi_bready, + S_AXI_ARADDR => s_axi_araddr, + S_AXI_ARVALID => s_axi_arvalid, + S_AXI_ARREADY => s_axi_arready, + S_AXI_RDATA => s_axi_rdata, + S_AXI_RRESP => s_axi_rresp, + S_AXI_RVALID => s_axi_rvalid, + S_AXI_RREADY => s_axi_rready, + + -- IP Interconnect (IPIC) port signals + Bus2IP_Clk => bus2ip_clk, + Bus2IP_Resetn => bus2ip_resetn, + IP2Bus_Data => ip2bus_data_i_D1, + IP2Bus_WrAck => ip2bus_wrack_i_D1, + IP2Bus_RdAck => ip2bus_rdack_i_D1, + --IP2Bus_WrAck => ip2bus_wrack_i, + --IP2Bus_RdAck => ip2bus_rdack_i, + IP2Bus_Error => ip2bus_error_i, + Bus2IP_Addr => bus2ip_addr, + Bus2IP_Data => bus2ip_data, + Bus2IP_RNW => bus2ip_rnw, + Bus2IP_BE => bus2ip_be, + Bus2IP_CS => bus2ip_cs, + Bus2IP_RdCE => bus2ip_rdce, + Bus2IP_WrCE => bus2ip_wrce + ); + + + + ip2bus_data_i <= intr2bus_data or ip2bus_data; + + ip2bus_wrack_i <= intr2bus_wrack or + (GPIO_xferAck_i and not(bus2ip_rnw)) or + ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range + + ip2bus_rdack_i <= intr2bus_rdack or + (GPIO_xferAck_i and bus2ip_rnw) or + ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range + + + I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is + begin + if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then + if (bus2ip_reset = '1') then + ip2bus_wrack_i_D1 <= '0'; + ip2bus_rdack_i_D1 <= '0'; + ip2bus_data_i_D1 <= (others => '0'); + else + ip2bus_wrack_i_D1 <= ip2bus_wrack_i; + ip2bus_rdack_i_D1 <= ip2bus_rdack_i; + ip2bus_data_i_D1 <= ip2bus_data_i; + end if; + end if; + end process I_WRACK_RDACK_DELAYS; + + + ip2bus_error_i <= intr2bus_error; + + ---------------------- + --REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of + -- the core. + ---------------------- + REG_RESET_FROM_IPIF: process (s_axi_aclk) is + begin + if(s_axi_aclk'event and s_axi_aclk = '1') then + bus2ip_reset <= not(bus2ip_resetn); + end if; + end process REG_RESET_FROM_IPIF; + --------------------------------------------------------------------------- + -- Interrupts + --------------------------------------------------------------------------- + + INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate + constant NUM_IPIF_IRPT_SRC : natural := 1; + constant NUM_CE : integer := 16; + + signal errack_reserved : std_logic_vector(0 to 1); + signal ipif_lvl_interrupts : std_logic_vector(0 to + NUM_IPIF_IRPT_SRC-1); + begin + + ipif_lvl_interrupts <= (others => '0'); + errack_reserved <= (others => '0'); + + + --- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes + + Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0' + & bus2ip_rdce(14) & "00000"; + + Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0' + & bus2ip_wrce(14) & "00000"; + + + intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or + Bus2IP_RdCE(13) or + or_reduce(Bus2IP_RdCE(15 to 19)); + + intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or + bus2ip_wrce(13) or + or_reduce(bus2ip_wrce(15 to 19)); + + I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is + begin + if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then + if (bus2ip_reset = '1') then + ip2Bus_RdAck_intr_reg_hole <= '0'; + ip2Bus_RdAck_intr_reg_hole_d1 <= '0'; + else + ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce; + ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and + (not ip2Bus_RdAck_intr_reg_hole_d1); + end if; + end if; + end process I_READ_ACK_INTR_HOLES; + + + + I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is + begin + if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then + if (bus2ip_reset = '1') then + ip2Bus_WrAck_intr_reg_hole <= '0'; + ip2Bus_WrAck_intr_reg_hole_d1 <= '0'; + else + ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce; + ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and + (not ip2Bus_WrAck_intr_reg_hole_d1); + end if; + end if; + end process I_WRITE_ACK_INTR_HOLES; + + + INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_4.interrupt_control + generic map + ( + C_NUM_CE => NUM_CE, + C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC, + C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, + C_INCLUDE_DEV_PENCODER => false, + C_INCLUDE_DEV_ISC => false, + C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH + ) + port map + ( + -- Inputs From the IPIF Bus + Bus2IP_Clk => Bus2IP_Clk, + Bus2IP_Reset => bus2ip_reset, + Bus2IP_Data => bus2ip_data, + Bus2IP_BE => bus2ip_be, + Interrupt_RdCE => Intrpt_bus2ip_rdce, + Interrupt_WrCE => Intrpt_bus2ip_wrce, + + -- Interrupt inputs from the IPIF sources that will + -- get registered in this design + IPIF_Reg_Interrupts => errack_reserved, + + -- Level Interrupt inputs from the IPIF sources + IPIF_Lvl_Interrupts => ipif_lvl_interrupts, + + -- Inputs from the IP Interface + IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range), + + -- Final Device Interrupt Output + Intr2Bus_DevIntr => IP2INTC_Irpt_i, + + -- Status Reply Outputs to the Bus + Intr2Bus_DBus => intr2bus_data, + Intr2Bus_WrAck => intr2bus_wrack, + Intr2Bus_RdAck => intr2bus_rdack, + Intr2Bus_Error => intr2bus_error, + Intr2Bus_Retry => open, + Intr2Bus_ToutSup => open + ); + + -- registering interrupt + I_INTR_DELAY: process(Bus2IP_Clk) is + begin + if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then + if (bus2ip_reset = '1') then + ip2intc_irpt <= '0'; + else + ip2intc_irpt <= IP2INTC_Irpt_i; + end if; + end if; + end process I_INTR_DELAY; + + end generate INTR_CTRLR_GEN; + ----------------------------------------------------------------------- + -- Assigning the intr2bus signal to zero's when interrupt is not + -- present + ----------------------------------------------------------------------- + REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate + + intr2bus_data <= (others => '0'); + ip2intc_irpt <= '0'; + intr2bus_error <= '0'; + intr2bus_rdack <= '0'; + intr2bus_wrack <= '0'; + ip2Bus_WrAck_intr_reg_hole <= '0'; + ip2Bus_RdAck_intr_reg_hole <= '0'; + + end generate REMOVE_INTERRUPT; + + gpio_core_1 : entity axi_gpio_v2_0_19.gpio_core + generic map + ( + C_DW => C_S_AXI_DATA_WIDTH, + C_AW => C_S_AXI_ADDR_WIDTH, + C_GPIO_WIDTH => C_GPIO_WIDTH, + C_GPIO2_WIDTH => C_GPIO2_WIDTH, + C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH, + C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT, + C_DOUT_DEFAULT => C_DOUT_DEFAULT, + C_TRI_DEFAULT => C_TRI_DEFAULT, + C_IS_DUAL => C_IS_DUAL, + C_ALL_OUTPUTS => C_ALL_OUTPUTS, + C_ALL_INPUTS => C_ALL_INPUTS, + C_ALL_INPUTS_2 => C_ALL_INPUTS_2, + C_ALL_OUTPUTS_2 => C_ALL_OUTPUTS_2, + C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2, + C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2, + C_FAMILY => C_FAMILY + ) + + port map + ( + Clk => Bus2IP_Clk, + Rst => bus2ip_reset, + ABus_Reg => Bus2IP_Addr, + BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1), + DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1), + RNW_Reg => Bus2IP_RNW, + Bus2IP_RdCE => bus2ip_rdce (0 to 3), + GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1), + GPIO_xferAck => GPIO_xferAck_i, + GPIO_Select => bus2ip_cs(0), + GPIO_intr => ip2bus_intrevent(0), + GPIO2_intr => ip2bus_intrevent(1), + GPIO_IO_I => gpio_io_i, + GPIO_IO_O => gpio_io_o, + GPIO_IO_T => gpio_io_t, + GPIO2_IO_I => gpio2_io_i, + GPIO2_IO_O => gpio2_io_o, + GPIO2_IO_T => gpio2_io_t + ); + + + + Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1' + and bus2ip_addr (5) = '0'else + Bus2IP2_Data_i; + + + BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate + Bus2IP1_Data_i(i) <= Bus2IP_Data(i+ + C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH); + end generate BUS_CONV_ch1; + + + + BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate + Bus2IP2_Data_i(i) <= Bus2IP_Data(i+ + C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH); + end generate BUS_CONV_ch2; + + + +end architecture imp; + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd new file mode 100644 index 0000000..db1ee12 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/cced/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd @@ -0,0 +1,3014 @@ +-- IPIF Common Library Package +------------------------------------------------------------------------------- +-- +-- ************************************************************************* +-- ** ** +-- ** DISCLAIMER OF LIABILITY ** +-- ** ** +-- ** This text/file contains proprietary, confidential ** +-- ** information of Xilinx, Inc., is distributed under ** +-- ** license from Xilinx, Inc., and may be used, copied ** +-- ** and/or disclosed only pursuant to the terms of a valid ** +-- ** license agreement with Xilinx, Inc. Xilinx hereby ** +-- ** grants you a license to use this text/file solely for ** +-- ** design, simulation, implementation and creation of ** +-- ** design files limited to Xilinx devices or technologies. ** +-- ** Use with non-Xilinx devices or technologies is expressly ** +-- ** prohibited and immediately terminates your license unless ** +-- ** covered by a separate agreement. ** +-- ** ** +-- ** Xilinx is providing this design, code, or information ** +-- ** "as-is" solely for use in developing programs and ** +-- ** solutions for Xilinx devices, with no obligation on the ** +-- ** part of Xilinx to provide support. By providing this design, ** +-- ** code, or information as one possible implementation of ** +-- ** this feature, application or standard, Xilinx is making no ** +-- ** representation that this implementation is free from any ** +-- ** claims of infringement. You are responsible for obtaining ** +-- ** any rights you may require for your implementation. ** +-- ** Xilinx expressly disclaims any warranty whatsoever with ** +-- ** respect to the adequacy of the implementation, including ** +-- ** but not limited to any warranties or representations that this ** +-- ** implementation is free from claims of infringement, implied ** +-- ** warranties of merchantability or fitness for a particular ** +-- ** purpose. ** +-- ** ** +-- ** Xilinx products are not intended for use in life support ** +-- ** appliances, devices, or systems. Use in such applications is ** +-- ** expressly prohibited. ** +-- ** ** +-- ** Any modifications that are made to the Source Code are ** +-- ** done at the user抯 sole risk and will be unsupported. ** +-- ** The Xilinx Support Hotline does not have access to source ** +-- ** code and therefore cannot answer specific questions related ** +-- ** to source HDL. The Xilinx Hotline support of original source ** +-- ** code IP shall only address issues and questions related ** +-- ** to the standard Netlist version of the core (and thus ** +-- ** indirectly, the original core source). ** +-- ** ** +-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. ** +-- ** ** +-- ** This copyright and support notice must be retained as part ** +-- ** of this text at all times. ** +-- ** ** +-- ************************************************************************* +-- + +------------------------------------------------------------------------------- +-- Filename: ipif_pkg.vhd +-- Version: Intital +-- Description: This file contains the constants and functions used in the +-- ipif common library components. +-- +------------------------------------------------------------------------------- +-- Structure: +-- +------------------------------------------------------------------------------- +-- Author: DET +-- History: +-- DET 02/21/02 -- Created from proc_common_pkg.vhd +-- +-- DET 03/13/02 -- PLB IPIF development updates +-- ^^^^^^ +-- - Commented out string types and string functions due to an XST +-- problem with string arrays and functions. THe string array +-- processing functions were replaced with comperable functions +-- operating on integer arrays. +-- ~~~~~~ +-- +-- +-- DET 4/30/2002 Initial +-- ~~~~~~ +-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and +-- rebuild_int_array to support removal of unused elements from the +-- ARD arrays. +-- ^^^^^^ -- +-- +-- FLO 8/12/2002 +-- ~~~~~~ +-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ, +-- and get_id_index_iboe. +-- (Removed provisional functions bits_needed_for_vacancy, +-- bits needed_for_occupancy, and bits_needed_for.) +-- ^^^^^^ +-- +-- FLO 3/24/2003 +-- ~~~~~~ +-- - Added dependent property paramters for channelized DMA. +-- - Added common property parameter array type. +-- - Definded the KEYHOLD_BURST common-property parameter. +-- ^^^^^^ +-- +-- FLO 10/22/2003 +-- ~~~~~~ +-- - Some adjustment to CHDMA parameterization. +-- - Cleanup of obsolete code and comments. (The former "XST workaround" +-- has become the officially deployed method.) +-- ^^^^^^ +-- +-- LSS 03/24/2004 +-- ~~~~~~ +-- - Added 5 functions +-- ^^^^^^ +-- +-- ALS 09/03/04 +-- ^^^^^^ +-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF +-- ~~~~~~ +-- +-- DET 1/17/2008 v4_0 +-- ~~~~~~ +-- - Changed proc_common library version to v4_0 +-- - Incorporated new disclaimer header +-- ^^^^^^ +-- +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +-- need conversion function to convert reals/integers to std logic vectors +use ieee.std_logic_arith.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +package ipif_pkg is + + +------------------------------------------------------------------------------- +-- Type Declarations +------------------------------------------------------------------------------- +type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31); +subtype SLV64_TYPE is std_logic_vector(0 to 63); +type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE; +type INTEGER_ARRAY_TYPE is array (natural range <>) of integer; + +------------------------------------------------------------------------------- +-- Function and Procedure Declarations +------------------------------------------------------------------------------- +function "=" (s1: in string; s2: in string) return boolean; + +function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN; + +function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer; + +function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE; + index : integer) return integer; + +function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer; + +function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer; + +function S32 (in_string : string) return string; + + +-------------------------------------------------------------------------------- +-- ARD support functions. +-- These function can be useful when operating with the ARD parameterization. +-------------------------------------------------------------------------------- + +function get_id_index (id_array :INTEGER_ARRAY_TYPE; + id : integer) + return integer; + +function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE; + id : integer) + return integer; + + +function find_ard_id (id_array : INTEGER_ARRAY_TYPE; + id : integer) return boolean; + + +function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE; + dwidth_array: INTEGER_ARRAY_TYPE; + id : integer; + default_i : integer) + return integer; + + +function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer; + +function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE; + id : integer) + return integer ; + + +function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE; + num_valid_pairs : integer) + return SLV32_ARRAY_TYPE; + +function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE; + num_valid_pairs : integer) + return SLV64_ARRAY_TYPE; + + +function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE; + num_valid_entry : integer) + return INTEGER_ARRAY_TYPE; + +-- 5 Functions Added 3/24/04 + +function populate_intr_mode_array (num_user_intr : integer; + intr_capture_mode : integer) + return INTEGER_ARRAY_TYPE ; + +function add_intr_ard_id_array(include_intr : boolean; + ard_id_array : INTEGER_ARRAY_TYPE) + return INTEGER_ARRAY_TYPE; + +function add_intr_ard_addr_range_array(include_intr : boolean; + ZERO_ADDR_PAD : std_logic_vector; + intr_baseaddr : std_logic_vector; + intr_highaddr : std_logic_vector; + ard_id_array : INTEGER_ARRAY_TYPE; + ard_addr_range_array : SLV64_ARRAY_TYPE) + return SLV64_ARRAY_TYPE; + +function add_intr_ard_num_ce_array(include_intr : boolean; + ard_id_array : INTEGER_ARRAY_TYPE; + ard_num_ce_array : INTEGER_ARRAY_TYPE) + return INTEGER_ARRAY_TYPE; + +function add_intr_ard_dwidth_array(include_intr : boolean; + intr_dwidth : integer; + ard_id_array : INTEGER_ARRAY_TYPE; + ard_dwidth_array : INTEGER_ARRAY_TYPE) + return INTEGER_ARRAY_TYPE; + +function log2(x : natural) return integer; +function clog2(x : positive) return natural; + + +------------------------------------------------------------------------------- +-- Constant Declarations +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Channel Protocols +-- The constant declarations below give symbolic-name aliases for values that +-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF. +------------------------------------------------------------------------------- +constant XCL : integer := 0; +constant DAG : integer := 1; + +-------------------------------------------------------------------------------- +-- Address range types. +-- The constant declarations, below, give symbolic-name aliases for values +-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set +-- gives aliases that are used to include IPIF services. +-------------------------------------------------------------------------------- +-- IPIF module aliases +Constant IPIF_INTR : integer := 1; +Constant IPIF_RST : integer := 2; +Constant IPIF_SESR_SEAR : integer := 3; +Constant IPIF_DMA_SG : integer := 4; +Constant IPIF_WRFIFO_REG : integer := 5; +Constant IPIF_WRFIFO_DATA : integer := 6; +Constant IPIF_RDFIFO_REG : integer := 7; +Constant IPIF_RDFIFO_DATA : integer := 8; +Constant IPIF_CHDMA_CHANNELS : integer := 9; +Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10; +Constant CHDMA_STATUS_FIFO : integer := 90; + +-- Some predefined user module aliases +Constant USER_00 : integer := 100; +Constant USER_01 : integer := 101; +Constant USER_02 : integer := 102; +Constant USER_03 : integer := 103; +Constant USER_04 : integer := 104; +Constant USER_05 : integer := 105; +Constant USER_06 : integer := 106; +Constant USER_07 : integer := 107; +Constant USER_08 : integer := 108; +Constant USER_09 : integer := 109; +Constant USER_10 : integer := 110; +Constant USER_11 : integer := 111; +Constant USER_12 : integer := 112; +Constant USER_13 : integer := 113; +Constant USER_14 : integer := 114; +Constant USER_15 : integer := 115; +Constant USER_16 : integer := 116; + + + +---( Start of Dependent Properties declarations +-------------------------------------------------------------------------------- +-- Declarations for Dependent Properties (properties that depend on the type of +-- the address range, or in other words, address-range-specific parameters). +-- There is one property, i.e. one parameter, encoded as an integer at +-- each index of the properties array. There is one properties array for +-- each address range. +-- +-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such +-- a properties array and it is usually giving its (static) value using a +-- VHDL aggregate construct. (--ToDo, give an example of this.) +-- +-- The the "assigned" default value of a dependent property is zero. This value +-- is usually specified the aggregate by leaving its (index) name out so that +-- it is covered by an "others => 0" choice in the aggregate. Some parameters, +-- as noted in the definitions, below, have an "effective" default value that is +-- different from the assigned default value of zero. In such cases, the +-- function, eff_dp, given below, can be used to get the effective value of +-- the dependent property. +-------------------------------------------------------------------------------- + +constant DEPENDENT_PROPS_SIZE : integer := 32; + +subtype DEPENDENT_PROPS_TYPE + is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1); + +type DEPENDENT_PROPS_ARRAY_TYPE + is array (natural range <>) of DEPENDENT_PROPS_TYPE; + + +-------------------------------------------------------------------------------- +-- Below are the indices of dependent properties for the different types of +-- address ranges. +-- +-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites +-- for a set of address ranges. Then, e.g., +-- +-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS) +-- +-- gives the fifo capacity in bits, provided that the i'th address range +-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA. +-- +-- These indices should be referenced only by the names below and never +-- by numerical literals. (The right to change numerical index assignments +-- is reserved; applications using the names will not be affected by such +-- reassignments.) +-------------------------------------------------------------------------------- +-- +--ToDo, if the interrupt controller parameterization is ever moved to +-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations +-- could be uncommented and used. +---- IPIF_INTR IDX +---------------------------------------------------------------------------- --- +constant EXCLUDE_DEV_ISC : integer := 0; + -- 1 specifies that only the global interrupt + -- enable is present in the device interrupt source + -- controller and that the only source of interrupts + -- in the device is the IP interrupt source controller. + -- 0 specifies that the full device interrupt + -- source controller structure will be included. +constant INCLUDE_DEV_PENCODER : integer := 1; + -- 1 will include the Device IID in the device interrupt + -- source controller, 0 will exclude it. + + +-- +-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX +---------------------------------------------------------------------------- --- +constant FIFO_CAPACITY_BITS : integer := 0; +constant WR_WIDTH_BITS : integer := 1; +constant RD_WIDTH_BITS : integer := 2; +constant EXCLUDE_PACKET_MODE : integer := 3; + -- 1 Don't include packet mode features + -- 0 Include packet mode features +constant EXCLUDE_VACANCY : integer := 4; + -- 1 Don't include vacancy calculation + -- 0 Include vacancy calculation + -- See also the functions + -- bits_needed_for_vac and + -- bits_needed_for_occ that are declared below. +constant INCLUDE_DRE : integer := 5; +constant INCLUDE_AUTOPUSH_POP : integer := 6; +constant AUTOPUSH_POP_CE : integer := 7; +constant INCLUDE_CSUM : integer := 8; +-------------------------------------------------------------------------------- + +-- +-- DMA_SG IDX +---------------------------------------------------------------------------- --- +-------------------------------------------------------------------------------- + +-- IPIF_CHDMA_CHANNELS IDX +---------------------------------------------------------------------------- --- +constant NUM_SUBS_FOR_PHYS_0 : integer :=0; +constant NUM_SUBS_FOR_PHYS_1 : integer :=1; +constant NUM_SUBS_FOR_PHYS_2 : integer :=2; +constant NUM_SUBS_FOR_PHYS_3 : integer :=3; +constant NUM_SUBS_FOR_PHYS_4 : integer :=4; +constant NUM_SUBS_FOR_PHYS_5 : integer :=5; +constant NUM_SUBS_FOR_PHYS_6 : integer :=6; +constant NUM_SUBS_FOR_PHYS_7 : integer :=7; +constant NUM_SUBS_FOR_PHYS_8 : integer :=8; +constant NUM_SUBS_FOR_PHYS_9 : integer :=9; +constant NUM_SUBS_FOR_PHYS_10 : integer :=10; +constant NUM_SUBS_FOR_PHYS_11 : integer :=11; +constant NUM_SUBS_FOR_PHYS_12 : integer :=12; +constant NUM_SUBS_FOR_PHYS_13 : integer :=13; +constant NUM_SUBS_FOR_PHYS_14 : integer :=14; +constant NUM_SUBS_FOR_PHYS_15 : integer :=15; + -- Gives the number of sub-channels for physical channel i. + -- + -- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see + -- below), have consecutive values starting with 0 for + -- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic + -- names for use in the dependent-properties aggregates that parameterize + -- an IPIF_CHDMA_CHANNELS address range.) + -- + -- [Users can ignore this note for developers + -- If the number of physical channels changes, both the + -- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS, + -- below, must be adjusted. + -- (Use of an array constant or a function of the form + -- NUM_SUBS_FOR_PHYS(i) to define the indices + -- runs afoul of LRM restrictions on non-locally static aggregate + -- choices. (Further, the LRM imposes perhaps unnecessarily + -- strict limits on what qualifies as a locally static primary.) + -- Note: This information is supplied for the benefit of anyone seeking + -- to improve the way that these NUM_SUBS_FOR_PHYS parameter + -- indices are defined.) + -- End of note for developers ] + -- + -- The value associated with any index NUM_SUBS_FOR_PHYS_i in the + -- dependent-properties array must be even since TX and RX channels + -- come in pairs with the TX followed immediately by + -- the corresponding RX. + -- +constant NUM_SIMPLE_DMA_CHANS : integer :=16; + -- The number of simple DMA channels. +constant NUM_SIMPLE_SG_CHANS : integer :=17; + -- The number of simple SG channels. +constant INTR_COALESCE : integer :=18; + -- 0 Interrupt coalescing is disabled + -- 1 Interrupt coalescing is enabled +constant CLK_PERIOD_PS : integer :=19; + -- The period of the OPB Bus clock in ps. + -- The default value of 0 is a special value that + -- is synonymous with 10000 ps (10 ns). + -- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1). +constant PACKET_WAIT_UNIT_NS : integer :=20; + -- Gives the unit for used for timing of pack-wait bounds. + -- The default value of 0 is a special value that + -- is synonymous with 1,000,000 ns (1 ms) and a non-default + -- value is typically only used for testing. + -- Relevant only if (INTR_COALESCE = 1). +constant BURST_SIZE : integer :=21; + -- 1, 2, 4, 8 or 16 + -- The default value of 0 is a special value that + -- is synonymous with a burst size of 16. + -- Setting the BURST_SIZE to 1 effectively disables + -- bursts. +constant REMAINDER_AS_SINGLES : integer :=22; + -- 0 Remainder handled as a short burst + -- 1 Remainder handled as a series of singles + + -------------------------------------------------------------------------------- + -- The constant below is not the index of a dependent-properties + -- parameter (and, as such, would never appear as a choice in a + -- dependent-properties aggregate). Rather, it is fixed to the maximum + -- number of physical channels that an Address Range of type + -- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with + -- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above. + -------------------------------------------------------------------------------- + constant MAX_NUM_PHYS_CHANNELS : natural := 16; + + + -------------------------------------------------------------------------- + -- EXAMPLE: Here is an example dependent-properties aggregate for an + -- address range of type IPIF_CHDMA_CHANNELS. + -- To have a compact list of all of the CHDMA parameters, all are + -- shown, however three are commented out and the unneeded + -- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association + -- gives these parameters their default values, such that, for the example + -- + -- - All physical channels above 2 have zero subchannels (effectively, + -- these physical channels are not used) + -- - There are no simple SG channels + -- - The packet-wait time unit is 1 ms + -- - Burst size is 16 + -------------------------------------------------------------------------- + -- ( + -- NUM_SUBS_FOR_PHYS_0 => 8, + -- NUM_SUBS_FOR_PHYS_1 => 4, + -- NUM_SUBS_FOR_PHYS_2 => 14, + -- NUM_SIMPLE_DMA_CHANS => 1, + -- --NUM_SIMPLE_SG_CHANS => 5, + -- INTR_COALESCE => 1, + -- CLK_PERIOD_PS => 20000, + -- --PACKET_WAIT_UNIT_NS => 50000, + -- --BURST_SIZE => 1, + -- REMAINDER_AS_SINGLES => 1, + -- OTHERS => 0 + -- ) + -- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Calculates the number of bits needed to convey the vacancy (emptiness) of +-- the fifo described by dependent_props, if fifo_present. If not fifo_present, +-- returns 0 (or the smallest value allowed by tool limitations on null arrays) +-- without making reference to dependent_props. +-------------------------------------------------------------------------------- +function bits_needed_for_vac( + fifo_present: boolean; + dependent_props : DEPENDENT_PROPS_TYPE + ) return integer; + +-------------------------------------------------------------------------------- +-- Calculates the number of bits needed to convey the occupancy (fullness) of +-- the fifo described by dependent_props, if fifo_present. If not fifo_present, +-- returns 0 (or the smallest value allowed by tool limitations on null arrays) +-- without making reference to dependent_props. +-------------------------------------------------------------------------------- +function bits_needed_for_occ( + fifo_present: boolean; + dependent_props : DEPENDENT_PROPS_TYPE + ) return integer; + +-------------------------------------------------------------------------------- +-- Function eff_dp. +-- +-- For some of the dependent properties, the default value of zero is meant +-- to imply an effective default value of other than zero (see e.g. +-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The +-- following function is used to get the (possibly default-adjusted) +-- value for a dependent property. +-- +-- Example call: +-- +-- eff_value_of_param := +-- eff_dp( +-- C_IPIF_CHDMA_CHANNELS, +-- PACKET_WAIT_UNIT_NS, +-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS) +-- ); +-- +-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type +-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of +-- type C_IPIF_CHDMA_CHANNELS. +-------------------------------------------------------------------------------- +function eff_dp(id : integer; -- The type of address range. + dep_prop : integer; -- The index of the dependent prop. + value : integer -- The value at that index. + ) return integer; -- The effective value, possibly adjusted + -- if value has the default value of 0. + +---) End of Dependent Properties declarations + + +-------------------------------------------------------------------------------- +-- Declarations for Common Properties (properties that apply regardless of the +-- type of the address range). Structurally, these work the same as +-- the dependent properties. +-------------------------------------------------------------------------------- + +constant COMMON_PROPS_SIZE : integer := 2; + +subtype COMMON_PROPS_TYPE + is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1); + +type COMMON_PROPS_ARRAY_TYPE + is array (natural range <>) of COMMON_PROPS_TYPE; + +-------------------------------------------------------------------------------- +-- Below are the indices of the common properties. +-- +-- These indices should be referenced only by the names below and never +-- by numerical literals. +-- IDX +---------------------------------------------------------------------------- --- +constant KEYHOLE_BURST : integer := 0; + -- 1 All addresses of a burst are forced to the initial + -- address of the burst. + -- 0 Burst addresses follow the bus protocol. + + + + +-- IP interrupt mode array constants +Constant INTR_PASS_THRU : integer := 1; +Constant INTR_PASS_THRU_INV : integer := 2; +Constant INTR_REG_EVENT : integer := 3; +Constant INTR_REG_EVENT_INV : integer := 4; +Constant INTR_POS_EDGE_DETECT : integer := 5; +Constant INTR_NEG_EDGE_DETECT : integer := 6; + + + + + +end ipif_pkg; + + + + +package body ipif_pkg is + +------------------------------------------------------------------------------- +-- Function log2 -- returns number of bits needed to encode x choices +-- x = 0 returns 0 +-- x = 1 returns 0 +-- x = 2 returns 1 +-- x = 4 returns 2, etc. +------------------------------------------------------------------------------- +-- +function log2(x : natural) return integer is + variable i : integer := 0; + variable val: integer := 1; +begin + if x = 0 then return 0; + else + for j in 0 to 29 loop -- for loop for XST + if val >= x then null; + else + i := i+1; + val := val*2; + end if; + end loop; + -- Fix per CR520627 XST was ignoring this anyway and printing a + -- Warning in SRP file. This will get rid of the warning and not + -- impact simulation. + -- synthesis translate_off + assert val >= x + report "Function log2 received argument larger" & + " than its capability of 2^30. " + severity failure; + -- synthesis translate_on + return i; + end if; +end function log2; + + + +-------------------------------------------------------------------------------- +-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x, +-- i.e., the least integer greater than or equal to log2(x). +-------------------------------------------------------------------------------- +function clog2(x : positive) return natural is + variable r : natural := 0; + variable rp : natural := 1; -- rp tracks the value 2**r +begin + while rp < x loop -- Termination condition T: x <= 2**r + -- Loop invariant L: 2**(r-1) < x + r := r + 1; + if rp > integer'high - rp then exit; end if; -- If doubling rp overflows + -- the integer range, the doubled value would exceed x, so safe to exit. + rp := rp + rp; + end loop; + -- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r + return r; -- +end clog2; + + +------------------------------------------------------------------------------- +-- Function Definitions +------------------------------------------------------------------------------- + + +----------------------------------------------------------------------------- +-- Function "=" +-- +-- This function can be used to overload the "=" operator when comparing +-- strings. +----------------------------------------------------------------------------- + function "=" (s1: in string; s2: in string) return boolean is + constant tc: character := ' '; -- string termination character + variable i: integer := 1; + variable v1 : string(1 to s1'length) := s1; + variable v2 : string(1 to s2'length) := s2; + begin + while (i <= v1'length) and (v1(i) /= tc) and + (i <= v2'length) and (v2(i) /= tc) and + (v1(i) = v2(i)) + loop + i := i+1; + end loop; + return ((i > v1'length) or (v1(i) = tc)) and + ((i > v2'length) or (v2(i) = tc)); + end; + + + + +---------------------------------------------------------------------------- +-- Function equaluseCase +-- +-- This function returns true if case sensitive string comparison determines +-- that str1 and str2 are the same. +----------------------------------------------------------------------------- + FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS + CONSTANT len1 : INTEGER := str1'length; + CONSTANT len2 : INTEGER := str2'length; + VARIABLE equal : BOOLEAN := TRUE; + BEGIN + IF NOT (len1=len2) THEN + equal := FALSE; + ELSE + FOR i IN str1'range LOOP + IF NOT (str1(i) = str2(i)) THEN + equal := FALSE; + END IF; + END LOOP; + END IF; + + RETURN equal; + END equaluseCase; + + +----------------------------------------------------------------------------- +-- Function calc_num_ce +-- +-- This function is used to process the array specifying the number of Chip +-- Enables required for a Base Address specification. The array is input to +-- the function and an integer is returned reflecting the total number of +-- Chip Enables required for the CE, RdCE, and WrCE Buses +----------------------------------------------------------------------------- + function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is + + Variable ce_num_sum : integer := 0; + + begin + + for i in 0 to (ce_num_array'length)-1 loop + ce_num_sum := ce_num_sum + ce_num_array(i); + End loop; + + return(ce_num_sum); + + end function calc_num_ce; + + +----------------------------------------------------------------------------- +-- Function calc_start_ce_index +-- +-- This function is used to process the array specifying the number of Chip +-- Enables required for a Base Address specification. The CE Size array is +-- input to the function and an integer index representing the index of the +-- target module in the ce_num_array. An integer is returned reflecting the +-- starting index of the assigned Chip Enables within the CE, RdCE, and +-- WrCE Buses. +----------------------------------------------------------------------------- + function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE; + index : integer) return integer is + + Variable ce_num_sum : integer := 0; + + begin + If (index = 0) Then + ce_num_sum := 0; + else + for i in 0 to index-1 loop + ce_num_sum := ce_num_sum + ce_num_array(i); + End loop; + End if; + + return(ce_num_sum); + + end function calc_start_ce_index; + + +----------------------------------------------------------------------------- +-- Function get_min_dwidth +-- +-- This function is used to process the array specifying the data bus width +-- for each of the target modules. The dwidth_array is input to the function +-- and an integer is returned that is the smallest value found of all the +-- entries in the array. +----------------------------------------------------------------------------- + function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is + + Variable temp_min : Integer := 1024; + + begin + + for i in 0 to dwidth_array'length-1 loop + + If (dwidth_array(i) < temp_min) Then + temp_min := dwidth_array(i); + else + null; + End if; + + End loop; + + return(temp_min); + + end function get_min_dwidth; + + + +----------------------------------------------------------------------------- +-- Function get_max_dwidth +-- +-- This function is used to process the array specifying the data bus width +-- for each of the target modules. The dwidth_array is input to the function +-- and an integer is returned that is the largest value found of all the +-- entries in the array. +----------------------------------------------------------------------------- + function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is + + Variable temp_max : Integer := 0; + + begin + + for i in 0 to dwidth_array'length-1 loop + + If (dwidth_array(i) > temp_max) Then + temp_max := dwidth_array(i); + else + null; + End if; + + End loop; + + return(temp_max); + + end function get_max_dwidth; + + + +----------------------------------------------------------------------------- +-- Function S32 +-- +-- This function is used to expand an input string to 32 characters by +-- padding with spaces. If the input string is larger than 32 characters, +-- it will truncate to 32 characters. +----------------------------------------------------------------------------- + function S32 (in_string : string) return string is + + constant OUTPUT_STRING_LENGTH : integer := 32; + Constant space : character := ' '; + + variable new_string : string(1 to 32); + Variable start_index : Integer := in_string'length+1; + + begin + + If (in_string'length < OUTPUT_STRING_LENGTH) Then + + for i in 1 to in_string'length loop + new_string(i) := in_string(i); + End loop; + + for j in start_index to OUTPUT_STRING_LENGTH loop + new_string(j) := space; + End loop; + + + else -- use first 32 chars of in_string (truncate the rest) + + for k in 1 to OUTPUT_STRING_LENGTH loop + new_string(k) := in_string(k); + End loop; + + End if; + + return(new_string); + + end function S32; + + +----------------------------------------------------------------------------- +-- Function get_id_index +-- +-- This function is used to process the array specifying the target function +-- assigned to a Base Address pair address range. The id_array and a +-- id number is input to the function. A integer is returned reflecting the +-- array index of the id matching the id input number. This function +-- should only be called if the id number is known to exist in the +-- name_array input. This can be detirmined by using the find_ard_id +-- function. +----------------------------------------------------------------------------- + function get_id_index (id_array :INTEGER_ARRAY_TYPE; + id : integer) return integer is + + Variable match : Boolean := false; + Variable match_index : Integer := 10000; -- a really big number! + + + begin + + for array_index in 0 to id_array'length-1 loop + + + If (match = true) Then -- match already found so do nothing + + null; + + else -- compare the numbers one by one + + match := (id_array(array_index) = id); + + If (match) Then + match_index := array_index; + else + null; + End if; + + End if; + + End loop; + + return(match_index); + + end function get_id_index; + + +-------------------------------------------------------------------------------- +-- get_id_index but return a value in bounds on error (iboe). +-- +-- This function is the same as get_id_index, except that when id does +-- not exist in id_array, the value returned is any index that is +-- within the index range of id_array. +-- +-- This function would normally only be used where function find_ard_id +-- is used to establish the existence of id but, even when non-existent, +-- an element of one of the ARD arrays will be computed from the +-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac +-- and the example call, below +-- +-- bits_needed_for_vac( +-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA), +-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY, +-- IPIF_RDFIFO_DATA)) +-- ) +-------------------------------------------------------------------------------- + function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE; + id : integer) return integer is + + Variable match : Boolean := false; + Variable match_index : Integer := id_array'left; -- any valid array index + + begin + for array_index in 0 to id_array'length-1 loop + If (match = true) Then -- match already found so do nothing + null; + else -- compare the numbers one by one + match := (id_array(array_index) = id); + If (match) Then match_index := array_index; + else null; + End if; + End if; + End loop; + return(match_index); + end function get_id_index_iboe; + + +----------------------------------------------------------------------------- +-- Function find_ard_id +-- +-- This function is used to process the array specifying the target function +-- assigned to a Base Address pair address range. The id_array and a +-- integer id is input to the function. A boolean is returned reflecting the +-- presence (or not) of a number in the array matching the id input number. +----------------------------------------------------------------------------- +function find_ard_id (id_array : INTEGER_ARRAY_TYPE; + id : integer) return boolean is + + Variable match : Boolean := false; + + begin + + for array_index in 0 to id_array'length-1 loop + + + If (match = true) Then -- match already found so do nothing + + null; + + else -- compare the numbers one by one + + match := (id_array(array_index) = id); + + End if; + + End loop; + + return(match); + + end function find_ard_id; + + +----------------------------------------------------------------------------- +-- Function find_id_dwidth +-- +-- This function is used to find the data width of a target module. If the +-- target module exists, the data width is extracted from the input dwidth +-- array. If the module is not in the ID array, the default input is +-- returned. This function is needed to assign data port size constraints on +-- unconstrained port widths. +----------------------------------------------------------------------------- +function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE; + dwidth_array: INTEGER_ARRAY_TYPE; + id : integer; + default_i : integer) return integer is + + + Variable id_present : Boolean := false; + Variable array_index : Integer := 0; + Variable dwidth : Integer := default_i; + + begin + + id_present := find_ard_id(id_array, id); + + If (id_present) Then + array_index := get_id_index (id_array, id); + dwidth := dwidth_array(array_index); + else + null; -- use default input + End if; + + + Return (dwidth); + + end function find_id_dwidth; + + + + + +----------------------------------------------------------------------------- +-- Function cnt_ipif_id_blks +-- +-- This function is used to detirmine the number of IPIF components specified +-- in the ARD ID Array. An integer is returned representing the number +-- of elements counted. User IDs are ignored in the counting process. +----------------------------------------------------------------------------- +function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) + return integer is + + Variable blk_count : integer := 0; + Variable temp_id : integer; + + begin + + for array_index in 0 to id_array'length-1 loop + + temp_id := id_array(array_index); + + If (temp_id = IPIF_WRFIFO_DATA or + temp_id = IPIF_RDFIFO_DATA or + temp_id = IPIF_RST or + temp_id = IPIF_INTR or + temp_id = IPIF_DMA_SG or + temp_id = IPIF_SESR_SEAR + ) Then -- IPIF block found + + blk_count := blk_count+1; + + else -- go to next loop iteration + + null; + + End if; + + End loop; + + return(blk_count); + +end function cnt_ipif_id_blks; + + + +----------------------------------------------------------------------------- +-- Function get_ipif_id_dbus_index +-- +-- This function is used to detirmine the IPIF relative index of a given +-- ID value. User IDs are ignored in the index detirmination. +----------------------------------------------------------------------------- +function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE; + id : integer) + return integer is + + Variable blk_index : integer := 0; + Variable temp_id : integer; + Variable id_found : Boolean := false; + +begin + + for array_index in 0 to id_array'length-1 loop + + temp_id := id_array(array_index); + + If (id_found) then + + null; + + elsif (temp_id = id) then + + id_found := true; + + elsif (temp_id = IPIF_WRFIFO_DATA or + temp_id = IPIF_RDFIFO_DATA or + temp_id = IPIF_RST or + temp_id = IPIF_INTR or + temp_id = IPIF_DMA_SG or + temp_id = IPIF_SESR_SEAR + ) Then -- IPIF block found + + blk_index := blk_index+1; + + else -- user block so do nothing + + null; + + End if; + + End loop; + + return(blk_index); + + +end function get_ipif_id_dbus_index; + + + + ------------------------------------------------------------------------------ + -- Function: rebuild_slv32_array + -- + -- Description: + -- This function takes an input slv32 array and rebuilds an output slv32 + -- array composed of the first "num_valid_entry" elements from the input + -- array. + ------------------------------------------------------------------------------ + function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE; + num_valid_pairs : integer) + return SLV32_ARRAY_TYPE is + + --Constants + constant num_elements : Integer := num_valid_pairs * 2; + + -- Variables + variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1); + + begin + + for array_index in 0 to num_elements-1 loop + + temp_baseaddr32_array(array_index) := slv32_array(array_index); + + end loop; + + + return(temp_baseaddr32_array); + + end function rebuild_slv32_array; + + + + + ------------------------------------------------------------------------------ + -- Function: rebuild_slv64_array + -- + -- Description: + -- This function takes an input slv64 array and rebuilds an output slv64 + -- array composed of the first "num_valid_entry" elements from the input + -- array. + ------------------------------------------------------------------------------ + function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE; + num_valid_pairs : integer) + return SLV64_ARRAY_TYPE is + + --Constants + constant num_elements : Integer := num_valid_pairs * 2; + + -- Variables + variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1); + + begin + + for array_index in 0 to num_elements-1 loop + + temp_baseaddr64_array(array_index) := slv64_array(array_index); + + end loop; + + + return(temp_baseaddr64_array); + + end function rebuild_slv64_array; + + + + ------------------------------------------------------------------------------ + -- Function: rebuild_int_array + -- + -- Description: + -- This function takes an input integer array and rebuilds an output integer + -- array composed of the first "num_valid_entry" elements from the input + -- array. + ------------------------------------------------------------------------------ + function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE; + num_valid_entry : integer) + return INTEGER_ARRAY_TYPE is + + -- Variables + variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1); + + begin + + for array_index in 0 to num_valid_entry-1 loop + + temp_int_array(array_index) := int_array(array_index); + + end loop; + + + return(temp_int_array); + + end function rebuild_int_array; + + + + function bits_needed_for_vac( + fifo_present: boolean; + dependent_props : DEPENDENT_PROPS_TYPE + ) return integer is + begin + if not fifo_present then + return 1; -- Zero would be better but leads to "0 to -1" null + -- ranges that are not handled by XST Flint or earlier + -- because of the negative index. + else + return + log2(1 + dependent_props(FIFO_CAPACITY_BITS) / + dependent_props(RD_WIDTH_BITS) + ); + end if; + end function bits_needed_for_vac; + + + function bits_needed_for_occ( + fifo_present: boolean; + dependent_props : DEPENDENT_PROPS_TYPE + ) return integer is + begin + if not fifo_present then + return 1; -- Zero would be better but leads to "0 to -1" null + -- ranges that are not handled by XST Flint or earlier + -- because of the negative index. + else + return + log2(1 + dependent_props(FIFO_CAPACITY_BITS) / + dependent_props(WR_WIDTH_BITS) + ); + end if; + end function bits_needed_for_occ; + + + function eff_dp(id : integer; + dep_prop : integer; + value : integer) return integer is + variable dp : integer := dep_prop; + type bo2na_type is array (boolean) of natural; + constant bo2na : bo2na_type := (0, 1); + begin + if value /= 0 then return value; end if; -- Not default + case id is + when IPIF_CHDMA_CHANNELS => + ------------------- + return( bo2na(dp = CLK_PERIOD_PS ) * 10000 + + bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000 + + bo2na(dp = BURST_SIZE ) * 16 + ); + when others => return 0; + end case; + end eff_dp; + + +function populate_intr_mode_array (num_user_intr : integer; + intr_capture_mode : integer) + return INTEGER_ARRAY_TYPE is + variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1); +begin + for i in 0 to num_user_intr-1 loop + intr_mode_array(i) := intr_capture_mode; + end loop; + + return intr_mode_array; +end function populate_intr_mode_array; + + +function add_intr_ard_id_array(include_intr : boolean; + ard_id_array : INTEGER_ARRAY_TYPE) + return INTEGER_ARRAY_TYPE is + variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length); +begin + intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array; + if include_intr then + intr_ard_id_array(ard_id_array'length) := IPIF_INTR; + return intr_ard_id_array; + else + return ard_id_array; + end if; +end function add_intr_ard_id_array; + + +function add_intr_ard_addr_range_array(include_intr : boolean; + ZERO_ADDR_PAD : std_logic_vector; + intr_baseaddr : std_logic_vector; + intr_highaddr : std_logic_vector; + ard_id_array : INTEGER_ARRAY_TYPE; + ard_addr_range_array : SLV64_ARRAY_TYPE) + return SLV64_ARRAY_TYPE is + variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1); +begin + intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array; + if include_intr then + intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)) + := ZERO_ADDR_PAD & intr_baseaddr; + intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1) + := ZERO_ADDR_PAD & intr_highaddr; + return intr_ard_addr_range_array; + else + return ard_addr_range_array; + end if; +end function add_intr_ard_addr_range_array; + +function add_intr_ard_dwidth_array(include_intr : boolean; + intr_dwidth : integer; + ard_id_array : INTEGER_ARRAY_TYPE; + ard_dwidth_array : INTEGER_ARRAY_TYPE) + return INTEGER_ARRAY_TYPE is + variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length); +begin + intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array; + if include_intr then + intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth; + return intr_ard_dwidth_array; + else + return ard_dwidth_array; + end if; +end function add_intr_ard_dwidth_array; + +function add_intr_ard_num_ce_array(include_intr : boolean; + ard_id_array : INTEGER_ARRAY_TYPE; + ard_num_ce_array : INTEGER_ARRAY_TYPE) + return INTEGER_ARRAY_TYPE is + variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length); +begin + intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array; + if include_intr then + intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16; + return intr_ard_num_ce_array; + else + return ard_num_ce_array; + end if; +end function add_intr_ard_num_ce_array; + + +end package body ipif_pkg; + + +-- pselect_f.vhd - entity/architecture pair +------------------------------------------------------------------------------- +-- +-- ************************************************************************* +-- ** ** +-- ** DISCLAIMER OF LIABILITY ** +-- ** ** +-- ** This text/file contains proprietary, confidential ** +-- ** information of Xilinx, Inc., is distributed under ** +-- ** license from Xilinx, Inc., and may be used, copied ** +-- ** and/or disclosed only pursuant to the terms of a valid ** +-- ** license agreement with Xilinx, Inc. Xilinx hereby ** +-- ** grants you a license to use this text/file solely for ** +-- ** design, simulation, implementation and creation of ** +-- ** design files limited to Xilinx devices or technologies. ** +-- ** Use with non-Xilinx devices or technologies is expressly ** +-- ** prohibited and immediately terminates your license unless ** +-- ** covered by a separate agreement. ** +-- ** ** +-- ** Xilinx is providing this design, code, or information ** +-- ** "as-is" solely for use in developing programs and ** +-- ** solutions for Xilinx devices, with no obligation on the ** +-- ** part of Xilinx to provide support. By providing this design, ** +-- ** code, or information as one possible implementation of ** +-- ** this feature, application or standard, Xilinx is making no ** +-- ** representation that this implementation is free from any ** +-- ** claims of infringement. You are responsible for obtaining ** +-- ** any rights you may require for your implementation. ** +-- ** Xilinx expressly disclaims any warranty whatsoever with ** +-- ** respect to the adequacy of the implementation, including ** +-- ** but not limited to any warranties or representations that this ** +-- ** implementation is free from claims of infringement, implied ** +-- ** warranties of merchantability or fitness for a particular ** +-- ** purpose. ** +-- ** ** +-- ** Xilinx products are not intended for use in life support ** +-- ** appliances, devices, or systems. Use in such applications is ** +-- ** expressly prohibited. ** +-- ** ** +-- ** Any modifications that are made to the Source Code are ** +-- ** done at the user抯 sole risk and will be unsupported. ** +-- ** The Xilinx Support Hotline does not have access to source ** +-- ** code and therefore cannot answer specific questions related ** +-- ** to source HDL. The Xilinx Hotline support of original source ** +-- ** code IP shall only address issues and questions related ** +-- ** to the standard Netlist version of the core (and thus ** +-- ** indirectly, the original core source). ** +-- ** ** +-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. ** +-- ** ** +-- ** This copyright and support notice must be retained as part ** +-- ** of this text at all times. ** +-- ** ** +-- ************************************************************************* +-- +------------------------------------------------------------------------------- +-- Filename: pselect_f.vhd +-- +-- Description: +-- (Note: At least as early as I.31, XST implements a carry- +-- chain structure for most decoders when these are coded in +-- inferrable VHLD. An example of such code can be seen +-- below in the "INFERRED_GEN" Generate Statement. +-- +-- -> New code should not need to instantiate pselect-type +-- components. +-- +-- -> Existing code can be ported to Virtex5 and later by +-- replacing pselect instances by pselect_f instances. +-- As long as the C_FAMILY parameter is not included +-- in the Generic Map, an inferred implementation +-- will result. +-- +-- -> If the designer wishes to force an explicit carry- +-- chain implementation, pselect_f can be used with +-- the C_FAMILY parameter set to the target +-- Xilinx FPGA family. +-- ) +-- +-- Parameterizeable peripheral select (address decode). +-- AValid qualifier comes in on Carry In at bottom +-- of carry chain. +-- +-- +-- VHDL-Standard: VHDL'93 +------------------------------------------------------------------------------- +-- Structure: pselect_f.vhd +-- family_support.vhd +-- +------------------------------------------------------------------------------- +-- History: +-- Vaibhav & FLO 05/26/06 First Version +-- +-- DET 1/17/2008 v4_0 +-- ~~~~~~ +-- - Changed proc_common library version to v4_0 +-- - Incorporated new disclaimer header +-- ^^^^^^ +-- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; + + +----------------------------------------------------------------------------- +-- Entity section +----------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Definition of Generics: +-- C_AB -- number of address bits to decode +-- C_AW -- width of address bus +-- C_BAR -- base address of peripheral (peripheral select +-- is asserted when the C_AB most significant +-- address bits match the C_AB most significant +-- C_BAR bits +-- Definition of Ports: +-- A -- address input +-- AValid -- address qualifier +-- CS -- peripheral select +------------------------------------------------------------------------------- + +entity pselect_f is + + generic ( + C_AB : integer := 9; + C_AW : integer := 32; + C_BAR : std_logic_vector; + C_FAMILY : string := "nofamily" + ); + port ( + A : in std_logic_vector(0 to C_AW-1); + AValid : in std_logic; + CS : out std_logic + ); + +end entity pselect_f; + +----------------------------------------------------------------------------- +-- Architecture section +----------------------------------------------------------------------------- + +architecture imp of pselect_f is + + + + ----------------------------------------------------------------------------- + -- C_BAR may not be indexed from 0 and may not be ascending; + -- BAR recasts C_BAR to have these properties. + ----------------------------------------------------------------------------- + constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR; + + -- type bo2sl_type is array (boolean) of std_logic; + -- constant bo2sl : bo2sl_type := (false => '0', true => '1'); + + function min(i, j: integer) return integer is + begin + if i 0 generate + CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else + '0' ; + end generate XST_WA; + + PASS_ON_GEN:if C_AB = 0 generate + CS <= AValid ; + end generate PASS_ON_GEN; + + + + +end imp; + + + +------------------------------------------------------------------- +-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +------------------------------------------------------------------- +-- ************************************************************************ +-- +------------------------------------------------------------------------------- +-- Filename: address_decoder.vhd +-- Version: v2.0 +-- Description: Address decoder utilizing unconstrained arrays for Base +-- Address specification and ce number. +------------------------------------------------------------------------------- +-- Structure: This section shows the hierarchical structure of axi_lite_ipif. +-- +-- --axi_lite_ipif.vhd +-- --slave_attachment.vhd +-- --address_decoder.vhd +------------------------------------------------------------------------------- +-- Author: BSB +-- +-- History: +-- +-- BSB 05/20/10 -- First version +-- ~~~~~~ +-- - Created the first version v1.00.a +-- ^^^^^^ +-- ~~~~~~ +-- SK 08/09/2010 -- +-- - updated the core with optimziation. Closed CR 574507 +-- - combined the CE generation logic to further optimize the code. +-- ^^^^^^ +-- ~~~~~~ +-- SK 12/16/12 -- v2.0 +-- 1. up reved to major version for 2013.1 Vivado release. No logic updates. +-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format +-- 3. updated the proc common version to proc_common_base_v5_0 +-- 4. No Logic Updates +-- ^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_cmb" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + +--library proc_common_base_v5_0; +--use proc_common_base_v5_0.proc_common_pkg.clog2; +--use proc_common_base_v5_0.pselect_f; +--use proc_common_base_v5_0.ipif_pkg.all; + +library axi_lite_ipif_v3_0_4; +use axi_lite_ipif_v3_0_4.ipif_pkg.all; + +------------------------------------------------------------------------------- +-- Definition of Generics +------------------------------------------------------------------------------- +-- C_BUS_AWIDTH -- Address bus width +-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP +-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range +-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range +-- C_FAMILY -- Target FPGA family +------------------------------------------------------------------------------- +-- Definition of Ports +------------------------------------------------------------------------------- +-- Bus_clk -- Clock +-- Bus_rst -- Reset +-- Address_In_Erly -- Adddress in +-- Address_Valid_Erly -- Address is valid +-- Bus_RNW -- Read or write registered +-- Bus_RNW_Erly -- Read or Write +-- CS_CE_ld_enable -- chip select and chip enable registered +-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear +-- RW_CE_ld_enable -- Read or Write Chip Enable +-- CS_for_gaps -- CS generation for the gaps between address ranges +-- CS_Out -- Chip select +-- RdCE_Out -- Read Chip enable +-- WrCE_Out -- Write chip enable +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Entity Declaration +------------------------------------------------------------------------------- + +entity address_decoder is + generic ( + C_BUS_AWIDTH : integer := 32; + C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF"; + C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := + ( + X"0000_0000_1000_0000", -- IP user0 base address + X"0000_0000_1000_01FF", -- IP user0 high address + X"0000_0000_1000_0200", -- IP user1 base address + X"0000_0000_1000_02FF" -- IP user1 high address + ); + C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := + ( + 8, -- User0 CE Number + 1 -- User1 CE Number + ); + C_FAMILY : string := "virtex6" + ); + port ( + Bus_clk : in std_logic; + Bus_rst : in std_logic; + + -- PLB Interface signals + Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1); + Address_Valid_Erly : in std_logic; + Bus_RNW : in std_logic; + Bus_RNW_Erly : in std_logic; + + -- Registering control signals + CS_CE_ld_enable : in std_logic; + Clear_CS_CE_Reg : in std_logic; + RW_CE_ld_enable : in std_logic; + CS_for_gaps : out std_logic; + -- Decode output signals + CS_Out : out std_logic_vector + (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); + RdCE_Out : out std_logic_vector + (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1); + WrCE_Out : out std_logic_vector + (0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) + ); +end entity address_decoder; + +------------------------------------------------------------------------------- +-- Architecture section +------------------------------------------------------------------------------- + +architecture IMP of address_decoder is +---------------------------------------------------------------------------------- +-- below attributes are added to reduce the synth warnings in Vivado tool +attribute DowngradeIPIdentifiedWarnings: string; +attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; +---------------------------------------------------------------------------------- + +-- local type declarations ---------------------------------------------------- +type decode_bit_array_type is Array(natural range 0 to ( + (C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of + integer; + +type short_addr_array_type is Array(natural range 0 to + C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of + std_logic_vector(0 to C_BUS_AWIDTH-1); +------------------------------------------------------------------------------- +-- Function Declarations +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- This function converts a 64 bit address range array to a AWIDTH bit +-- address range array. +------------------------------------------------------------------------------- +function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE; + awidth : integer) + return short_addr_array_type is + + variable temp_addr : std_logic_vector(0 to 63); + variable slv_array : short_addr_array_type; + begin + for array_index in 0 to slv64_addr_array'length-1 loop + temp_addr := slv64_addr_array(array_index); + slv_array(array_index) := temp_addr((64-awidth) to 63); + end loop; + return(slv_array); + end function slv64_2_slv_awidth; + +------------------------------------------------------------------------------- +--Function Addr_bits +--function to convert an address range (base address and an upper address) +--into the number of upper address bits needed for decoding a device +--select signal. will handle slices and big or little endian +------------------------------------------------------------------------------- +function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1)) + return integer is + variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1); + begin + addr_nor := x xor y; + for i in 0 to C_BUS_AWIDTH-1 loop + if addr_nor(i)='1' then + return i; + end if; + end loop; +--coverage off + return(C_BUS_AWIDTH); +--coverage on + end function Addr_Bits; + + +------------------------------------------------------------------------------- +--Function Get_Addr_Bits +--function calculates the array which has the decode bits for the each address +--range. +------------------------------------------------------------------------------- +function Get_Addr_Bits (baseaddrs : short_addr_array_type) + return decode_bit_array_type is + + variable num_bits : decode_bit_array_type; + begin + for i in 0 to ((baseaddrs'length)/2)-1 loop + + num_bits(i) := Addr_Bits (baseaddrs(i*2), + baseaddrs(i*2+1)); + end loop; + return(num_bits); + end function Get_Addr_Bits; + + +------------------------------------------------------------------------------- +-- NEEDED_ADDR_BITS +-- +-- Function Description: +-- This function calculates the number of address bits required +-- to support the CE generation logic. This is determined by +-- multiplying the number of CEs for an address space by the +-- data width of the address space (in bytes). Each address +-- space entry is processed and the biggest of the spaces is +-- used to set the number of address bits required to be latched +-- and used for CE decoding. A minimum value of 1 is returned by +-- this function. +-- +------------------------------------------------------------------------------- +function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE) + return integer is + + constant NUM_CE_ENTRIES : integer := CE_ARRAY'length; + variable biggest : integer := 2; + variable req_ce_addr_size : integer := 0; + variable num_addr_bits : integer := 0; + begin + + for i in 0 to NUM_CE_ENTRIES-1 loop + req_ce_addr_size := ce_array(i) * 4; + if (req_ce_addr_size > biggest) Then + biggest := req_ce_addr_size; + end if; + end loop; + num_addr_bits := clog2(biggest); + return(num_addr_bits); + end function NEEDED_ADDR_BITS; + +----------------------------------------------------------------------------- +-- Function calc_high_address +-- +-- This function is used to calculate the high address of the each address +-- range +----------------------------------------------------------------------------- + function calc_high_address (high_address : short_addr_array_type; + index : integer) return std_logic_vector is + + variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1); + + begin + If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then + calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31); + else + calc_high_addr := high_address(index*2+2); + end if; + return(calc_high_addr); + end function calc_high_address; + +---------------------------------------------------------------------------- +-- Constant Declarations +------------------------------------------------------------------------------- +constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type := + slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY, + C_BUS_AWIDTH); + +constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2; + +constant DECODE_BITS : decode_bit_array_type := + Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY); + +constant NUM_CE_SIGNALS : integer := + calc_num_ce(C_ARD_NUM_CE_ARRAY); + +constant NUM_S_H_ADDR_BITS : integer := + needed_addr_bits(C_ARD_NUM_CE_ARRAY); +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- +signal pselect_hit_i : std_logic_vector + (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); +signal cs_out_i : std_logic_vector + (0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1); +signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); +signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); +signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); + +signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); -- + +signal cs_ce_clr : std_logic; +signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1); + +signal Bus_RNW_reg : std_logic; +------------------------------------------------------------------------------- +-- Begin architecture +------------------------------------------------------------------------------- +begin -- architecture IMP + + +-- Register clears +cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg; + +addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS + to C_BUS_AWIDTH-1); +------------------------------------------------------------------------------- +-- MEM_DECODE_GEN: Universal Address Decode Block +------------------------------------------------------------------------------- +MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate +--------------- +constant CE_INDEX_START : integer + := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index); +constant CE_ADDR_SIZE : Integer range 0 to 15 + := clog2(C_ARD_NUM_CE_ARRAY(bar_index)); +constant OFFSET : integer := 2; + +constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1) + := ARD_ADDR_RANGE_ARRAY(bar_index*2+1); + +constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1) + := calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index); +--constant DECODE_BITS_0 : integer:= DECODE_BITS(0); +--------- +begin +--------- + + -- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address + -- ----------------- + GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate + -- Instantiate the basic Base Address Decoders + MEM_SELECT_I: entity axi_lite_ipif_v3_0_4.pselect_f + generic map + ( + C_AB => DECODE_BITS(bar_index), + C_AW => C_BUS_AWIDTH, + C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2), + C_FAMILY => C_FAMILY + ) + port map + ( + A => Address_In_Erly, -- [in] + AValid => Address_Valid_Erly, -- [in] + CS => pselect_hit_i(bar_index) -- [out] + ); + end generate GEN_FOR_MULTI_CS; + + -- GEN_FOR_ONE_CS: below logic decodes the CS for single address range + -- --------------- + GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate + pselect_hit_i(bar_index) <= Address_Valid_Erly; + end generate GEN_FOR_ONE_CS; + + + -- Instantate backend registers for the Chip Selects + BKEND_CS_REG : process(Bus_Clk) + begin + if(Bus_Clk'EVENT and Bus_Clk = '1')then + if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then + cs_out_i(bar_index) <= '0'; + elsif(CS_CE_ld_enable='1')then + cs_out_i(bar_index) <= pselect_hit_i(bar_index); + end if; + end if; + end process BKEND_CS_REG; + + ------------------------------------------------------------------------- + -- PER_CE_GEN: Now expand the individual CEs for each base address. + ------------------------------------------------------------------------- + PER_CE_GEN: for j in natural range 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate + ----------- + begin + ----------- + ---------------------------------------------------------------------- + -- CE decoders for multiple CE's + ---------------------------------------------------------------------- + MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate + constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) := + std_logic_vector(to_unsigned(j,CE_ADDR_SIZE)); + begin + CE_I : entity axi_lite_ipif_v3_0_4.pselect_f + generic map ( + C_AB => CE_ADDR_SIZE , + C_AW => CE_ADDR_SIZE , + C_BAR => BAR , + C_FAMILY => C_FAMILY + ) + port map ( + A => addr_out_s_h + (NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE + to NUM_S_H_ADDR_BITS - OFFSET - 1) , + AValid => pselect_hit_i(bar_index) , + CS => ce_expnd_i(CE_INDEX_START+j) + ); + end generate MULTIPLE_CES_THIS_CS_GEN; + -------------------------------------- + ---------------------------------------------------------------------- + -- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE + ---------------------------------------------------------------------- + SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate + ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index); + end generate; + ------------- + end generate PER_CE_GEN; + ------------------------ +end generate MEM_DECODE_GEN; + + -- RNW_REG_P: Register the incoming RNW signal at the time of registering the + -- address. This is need to generate the CE's separately. + + RNW_REG_P:process(Bus_Clk) + begin + if(Bus_Clk'EVENT and Bus_Clk = '1')then + if(RW_CE_ld_enable='1')then + Bus_RNW_reg <= Bus_RNW_Erly; + end if; + end if; + end process RNW_REG_P; + + --------------------------------------------------------------------------- + -- GEN_BKEND_CE_REGISTERS + -- This ForGen implements the backend registering for + -- the CE, RdCE, and WrCE output buses. + --------------------------------------------------------------------------- +GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate +signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); +signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); +------ +begin +------ + + + BKEND_RDCE_REG : process(Bus_Clk) + begin + if(Bus_Clk'EVENT and Bus_Clk = '1')then + if(cs_ce_clr='1')then + ce_out_i(ce_index) <= '0'; + elsif(RW_CE_ld_enable='1')then + ce_out_i(ce_index) <= ce_expnd_i(ce_index); + end if; + end if; + end process BKEND_RDCE_REG; + rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg; + wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg; + +------------------------------- +end generate GEN_BKEND_CE_REGISTERS; +------------------------------------------------------------------------------- + +CS_for_gaps <= '0'; -- Removed the GAP adecoder logic +--------------------------------- +CS_Out <= cs_out_i ; +RdCE_Out <= rdce_out_i ; +WrCE_Out <= wrce_out_i ; + +end architecture IMP; + + +------------------------------------------------------------------- +-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +------------------------------------------------------------------- +-- ************************************************************************ +-- +------------------------------------------------------------------------------- +-- Filename: slave_attachment.vhd +-- Version: v2.0 +-- Description: AXI slave attachment supporting single transfers +------------------------------------------------------------------------------- +-- Structure: This section shows the hierarchical structure of axi_lite_ipif. +-- +-- --axi_lite_ipif.vhd +-- --slave_attachment.vhd +-- --address_decoder.vhd +------------------------------------------------------------------------------- +-- Author: BSB +-- +-- History: +-- +-- BSB 05/20/10 -- First version +-- ~~~~~~ +-- - Created the first version v1.00.a +-- ^^^^^^ +-- ~~~~~~ +-- SK 06/09/10 -- updated to reduce the utilization +-- 1. State machine is re-designed +-- 2. R and B channels are registered and AW, AR, W channels are non-registered +-- 3. Address decoding is done only for the required address bits and not complete +-- 32 bits +-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux +-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg +-- function. +-- ^^^^^^ +-- ~~~~~~ +-- SK 12/16/12 -- v2.0 +-- 1. up reved to major version for 2013.1 Vivado release. No logic updates. +-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format +-- 3. updated the proc common version to proc_common_base_v5_0 +-- 4. No Logic Updates +-- ^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- access_cs machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_cmb" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_misc.all; + +--library proc_common_base_v5_0; +--use proc_common_base_v5_0.proc_common_pkg.clog2; +--use proc_common_base_v5_0.ipif_pkg.all; + +library axi_lite_ipif_v3_0_4; +use axi_lite_ipif_v3_0_4.ipif_pkg.all; + +------------------------------------------------------------------------------- +-- Definition of Generics +------------------------------------------------------------------------------- +-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width +-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width +-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP +-- C_USE_WSTRB -- Use write strobs or not +-- C_DPHASE_TIMEOUT -- Data phase time out counter +-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range +-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range +-- C_FAMILY -- Target FPGA family +------------------------------------------------------------------------------- +-- Definition of Ports +------------------------------------------------------------------------------- +-- S_AXI_ACLK -- AXI Clock +-- S_AXI_ARESET -- AXI Reset +-- S_AXI_AWADDR -- AXI Write address +-- S_AXI_AWVALID -- Write address valid +-- S_AXI_AWREADY -- Write address ready +-- S_AXI_WDATA -- Write data +-- S_AXI_WSTRB -- Write strobes +-- S_AXI_WVALID -- Write valid +-- S_AXI_WREADY -- Write ready +-- S_AXI_BRESP -- Write response +-- S_AXI_BVALID -- Write response valid +-- S_AXI_BREADY -- Response ready +-- S_AXI_ARADDR -- Read address +-- S_AXI_ARVALID -- Read address valid +-- S_AXI_ARREADY -- Read address ready +-- S_AXI_RDATA -- Read data +-- S_AXI_RRESP -- Read response +-- S_AXI_RVALID -- Read valid +-- S_AXI_RREADY -- Read ready +-- Bus2IP_Clk -- Synchronization clock provided to User IP +-- Bus2IP_Reset -- Active high reset for use by the User IP +-- Bus2IP_Addr -- Desired address of read or write operation +-- Bus2IP_RNW -- Read or write indicator for the transaction +-- Bus2IP_BE -- Byte enables for the data bus +-- Bus2IP_CS -- Chip select for the transcations +-- Bus2IP_RdCE -- Chip enables for the read +-- Bus2IP_WrCE -- Chip enables for the write +-- Bus2IP_Data -- Write data bus to the User IP +-- IP2Bus_Data -- Input Read Data bus from the User IP +-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP +-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP +-- IP2Bus_Error -- Error signal from the IP +------------------------------------------------------------------------------- + +entity slave_attachment is + generic ( + + C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := + ( + X"0000_0000_7000_0000", -- IP user0 base address + X"0000_0000_7000_00FF", -- IP user0 high address + X"0000_0000_7000_0100", -- IP user1 base address + X"0000_0000_7000_01FF" -- IP user1 high address + ); + C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := + ( + 1, -- User0 CE Number + 8 -- User1 CE Number + ); + C_IPIF_ABUS_WIDTH : integer := 32; + C_IPIF_DBUS_WIDTH : integer := 32; + C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; + C_USE_WSTRB : integer := 0; + C_DPHASE_TIMEOUT : integer range 0 to 512 := 16; + C_FAMILY : string := "virtex6" + ); + port( + -- AXI signals + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector + (C_IPIF_ABUS_WIDTH-1 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector + (C_IPIF_DBUS_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector + ((C_IPIF_DBUS_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector + (C_IPIF_ABUS_WIDTH-1 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector + (C_IPIF_DBUS_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + -- Controls to the IP/IPIF modules + Bus2IP_Clk : out std_logic; + Bus2IP_Resetn : out std_logic; + Bus2IP_Addr : out std_logic_vector + (C_IPIF_ABUS_WIDTH-1 downto 0); + Bus2IP_RNW : out std_logic; + Bus2IP_BE : out std_logic_vector + (((C_IPIF_DBUS_WIDTH/8) - 1) downto 0); + Bus2IP_CS : out std_logic_vector + (((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0); + Bus2IP_RdCE : out std_logic_vector + ((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); + Bus2IP_WrCE : out std_logic_vector + ((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); + Bus2IP_Data : out std_logic_vector + ((C_IPIF_DBUS_WIDTH-1) downto 0); + IP2Bus_Data : in std_logic_vector + ((C_IPIF_DBUS_WIDTH-1) downto 0); + IP2Bus_WrAck : in std_logic; + IP2Bus_RdAck : in std_logic; + IP2Bus_Error : in std_logic + ); +end entity slave_attachment; + +------------------------------------------------------------------------------- +architecture imp of slave_attachment is +---------------------------------------------------------------------------------- +-- below attributes are added to reduce the synth warnings in Vivado tool +attribute DowngradeIPIdentifiedWarnings: string; +attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; +---------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- Get_Addr_Bits: Function Declarations +------------------------------------------------------------------------------- +function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is +variable i : integer := 0; + begin + for i in 31 downto 0 loop + if y(i)='1' then + return (i); + end if; + end loop; + return -1; +end function Get_Addr_Bits; + +------------------------------------------------------------------------------- +-- Constant Declarations +------------------------------------------------------------------------------- +constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2; +constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY); + +constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE); +constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1; +constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto + (C_ADDR_DECODE_BITS+1)) := (others=>'0'); +------------------------------------------------------------------------------- +-- Signal and Type Declarations +------------------------------------------------------------------------------- +signal s_axi_bvalid_i : std_logic:= '0'; +signal s_axi_arready_i : std_logic; +signal s_axi_rvalid_i : std_logic:= '0'; +signal start : std_logic; +signal start2 : std_logic; +-- Intermediate IPIC signals +signal bus2ip_addr_i : std_logic_vector + ((C_IPIF_ABUS_WIDTH-1) downto 0); +signal timeout : std_logic; + +signal rd_done,wr_done : std_logic; +signal rd_done1,wr_done1 : std_logic; +--signal rd_done2,wr_done2 : std_logic; +signal wrack_1,rdack_1 : std_logic; +--signal wrack_2,rdack_2 : std_logic; +signal rst : std_logic; +signal temp_i : std_logic; + + type BUS_ACCESS_STATES is ( + SM_IDLE, + SM_READ, + SM_WRITE, + SM_RESP + ); +signal state : BUS_ACCESS_STATES; + +signal cs_for_gaps_i : std_logic; +signal bus2ip_rnw_i : std_logic; +signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0'); +signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0'); +signal s_axi_rdata_i : std_logic_vector + (C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0'); +signal is_read, is_write : std_logic; +------------------------------------------------------------------------------- +-- begin the architecture logic +------------------------------------------------------------------------------- +begin + +------------------------------------------------------------------------------- +-- Address registered +------------------------------------------------------------------------------- +Bus2IP_Clk <= S_AXI_ACLK; +Bus2IP_Resetn <= S_AXI_ARESETN; +--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1' +-- else +-- '0'; +BUS2IP_RNW <= bus2ip_rnw_i; +Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0')) + else + (others => '1'); +Bus2IP_Data <= S_AXI_WDATA; +Bus2IP_Addr <= bus2ip_addr_i; + +-- For AXI Lite interface, interconnect will duplicate the addresses on both the +-- read and write channel. so onlyone address is used for decoding as well as +-- passing it to IP. +--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0) +-- when (S_AXI_ARVALID='1') +-- else +-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0); + +-------------------------------------------------------------------------------- +-- start signal will be used to latch the incoming address + +--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID)) +-- when (state = SM_IDLE) +-- else +-- '0'; + +-- x_done signals are used to release the hold from AXI, it will generate "ready" +-- signal on the read and write address channels. + +rd_done <= IP2Bus_RdAck or (timeout and is_read); +wr_done <= IP2Bus_WrAck or (timeout and is_write); + +--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout; +--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout; + +temp_i <= rd_done or wr_done; +------------------------------------------------------------------------------- +-- Address Decoder Component Instance +-- +-- This component decodes the specified base address pairs and outputs the +-- specified number of chip enables and the target bus size. +------------------------------------------------------------------------------- +I_DECODER : entity axi_lite_ipif_v3_0_4.address_decoder + generic map + ( + C_BUS_AWIDTH => C_NUM_DECODE_BITS, + C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, + C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY, + C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, + C_FAMILY => "nofamily" + ) + port map + ( + Bus_clk => S_AXI_ACLK, + Bus_rst => S_AXI_ARESETN, + Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0), + Address_Valid_Erly => start2, + Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID, + Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID, + CS_CE_ld_enable => start2, + Clear_CS_CE_Reg => temp_i, + RW_CE_ld_enable => start2, + CS_for_gaps => open, + -- Decode output signals + CS_Out => Bus2IP_CS, + RdCE_Out => Bus2IP_RdCE, + WrCE_Out => Bus2IP_WrCE + ); + + + -- REGISTERING_RESET_P: Invert the reset coming from AXI + ----------------------- + REGISTERING_RESET_P : process (S_AXI_ACLK) is + begin + if S_AXI_ACLK'event and S_AXI_ACLK = '1' then + rst <= not S_AXI_ARESETN; + end if; + end process REGISTERING_RESET_P; + + + REGISTERING_RESET_P2 : process (S_AXI_ACLK) is + begin + if S_AXI_ACLK'event and S_AXI_ACLK = '1' then + if (rst = '1') then + -- wrack_1 <= '0'; + -- rdack_1 <= '0'; + -- wrack_2 <= '0'; + -- rdack_2 <= '0'; + -- wr_done2 <= '0'; + -- rd_done2 <= '0'; + bus2ip_rnw_i <= '0'; + bus2ip_addr_i <= (others => '0'); + start2 <= '0'; + else + -- wrack_1 <= IP2Bus_WrAck; + -- rdack_1 <= IP2Bus_RdAck; + -- wrack_2 <= wrack_1; + -- rdack_2 <= rdack_1; + -- wr_done2 <= wr_done1; + -- rd_done2 <= rd_done1; + + if (state = SM_IDLE and S_AXI_ARVALID='1') then + bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0); + bus2ip_rnw_i <= '1'; + start2 <= '1'; + elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then + bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0); + bus2ip_rnw_i <= '0'; + start2 <= '1'; + else + bus2ip_rnw_i <= bus2ip_rnw_i; + bus2ip_addr_i <= bus2ip_addr_i; + start2 <= '0'; + end if; + end if; + end if; + end process REGISTERING_RESET_P2; + + +------------------------------------------------------------------------------- +-- AXI Transaction Controller +------------------------------------------------------------------------------- +-- Access_Control: As per suggestion to optimize the core, the below state machine +-- is re-coded. Latches are removed from original suggestions +Access_Control : process (S_AXI_ACLK) is + begin + if S_AXI_ACLK'event and S_AXI_ACLK = '1' then + if rst = '1' then + state <= SM_IDLE; + is_read <= '0'; + is_write <= '0'; + else + case state is + when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write + state <= SM_READ; + is_read <='1'; + is_write <= '0'; + elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then + state <= SM_WRITE; + is_read <='0'; + is_write <= '1'; + else + state <= SM_IDLE; + is_read <='0'; + is_write <= '0'; + end if; + + when SM_READ => if rd_done = '1' then + state <= SM_RESP; + else + state <= SM_READ; + end if; + + when SM_WRITE=> if (wr_done = '1') then + state <= SM_RESP; + else + state <= SM_WRITE; + end if; + + when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or + (s_axi_rvalid_i and S_AXI_RREADY)) = '1' then + state <= SM_IDLE; + is_read <='0'; + is_write <= '0'; + else + state <= SM_RESP; + end if; + -- coverage off + when others => state <= SM_IDLE; + -- coverage on + end case; + end if; + end if; + end process Access_Control; + +------------------------------------------------------------------------------- + -- AXI Transaction Controller signals registered +------------------------------------------------------------------------------- +-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI +----------------------- +S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is + begin + if S_AXI_ACLK'event and S_AXI_ACLK = '1' then + if (rst = '1') then + s_axi_rresp_i <= (others => '0'); + s_axi_rdata_i <= (others => '0'); + elsif state = SM_READ then + s_axi_rresp_i <= (IP2Bus_Error) & '0'; + s_axi_rdata_i <= IP2Bus_Data; + end if; + end if; +end process S_AXI_RDATA_RESP_P; + +S_AXI_RRESP <= s_axi_rresp_i; +S_AXI_RDATA <= s_axi_rdata_i; +----------------------------- + +-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel +---------------------- +S_AXI_RVALID_I_P : process (S_AXI_ACLK) is + begin + if S_AXI_ACLK'event and S_AXI_ACLK = '1' then + if (rst = '1') then + s_axi_rvalid_i <= '0'; + elsif ((state = SM_READ) and rd_done = '1') then + s_axi_rvalid_i <= '1'; + elsif (S_AXI_RREADY = '1') then + s_axi_rvalid_i <= '0'; + end if; + end if; +end process S_AXI_RVALID_I_P; + +-- -- S_AXI_BRESP_P: Below process provides logic for write response +-- ----------------- +S_AXI_BRESP_P : process (S_AXI_ACLK) is + begin + if S_AXI_ACLK'event and S_AXI_ACLK = '1' then + if (rst = '1') then + s_axi_bresp_i <= (others => '0'); + elsif (state = SM_WRITE) then + s_axi_bresp_i <= (IP2Bus_Error) & '0'; + end if; + end if; +end process S_AXI_BRESP_P; + +S_AXI_BRESP <= s_axi_bresp_i; +--S_AXI_BVALID_I_P: below process provides logic for valid write response signal +------------------- +S_AXI_BVALID_I_P : process (S_AXI_ACLK) is + begin + if S_AXI_ACLK'event and S_AXI_ACLK = '1' then + if rst = '1' then + s_axi_bvalid_i <= '0'; + elsif ((state = SM_WRITE) and wr_done = '1') then + s_axi_bvalid_i <= '1'; + elsif (S_AXI_BREADY = '1') then + s_axi_bvalid_i <= '0'; + end if; + end if; +end process S_AXI_BVALID_I_P; +----------------------------------------------------------------------------- + +-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero. +-------------- +INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate + + constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT)); + signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0); + -- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout + -- condition to be captured as a carry into this "extra" bit. +begin + + DPTO_CNT_P : process (S_AXI_ACLK) is + begin + if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then + if ((state = SM_IDLE) or (state = SM_RESP)) then + dpto_cnt <= (others=>'0'); + else + dpto_cnt <= dpto_cnt + 1; + end if; + end if; + end process DPTO_CNT_P; + + timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0'; + +end generate INCLUDE_DPHASE_TIMER; + +EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate + timeout <= '0'; +end generate EXCLUDE_DPHASE_TIMER; + +----------------------------------------------------------------------------- +S_AXI_BVALID <= s_axi_bvalid_i; +S_AXI_RVALID <= s_axi_rvalid_i; +----------------------------------------------------------------------------- +S_AXI_ARREADY <= rd_done; +S_AXI_AWREADY <= wr_done; +S_AXI_WREADY <= wr_done; +------------------------------------------------------------------------------- +end imp; + + +------------------------------------------------------------------- +-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +------------------------------------------------------------------- +-- ************************************************************************ +-- +------------------------------------------------------------------------------- +-- Filename: axi_lite_ipif.vhd +-- Version: v2.0 +-- Description: This is the top level design file for the axi_lite_ipif +-- function. It provides a standardized slave interface +-- between the IP and the AXI. This version supports +-- single read/write transfers only. It does not provide +-- address pipelining or simultaneous read and write +-- operations. +------------------------------------------------------------------------------- +-- Structure: This section shows the hierarchical structure of axi_lite_ipif. +-- +-- --axi_lite_ipif.vhd +-- --slave_attachment.vhd +-- --address_decoder.vhd +------------------------------------------------------------------------------- +-- Author: BSB +-- +-- History: +-- +-- BSB 05/20/10 -- First version +-- ~~~~~~ +-- - Created the first version v1.00.a +-- ^^^^^^ +-- ~~~~~~ +-- SK 06/09/10 -- v1.01.a +-- 1. updated to reduce the utilization +-- Closed CR #574507 +-- 2. Optimized the state machine code +-- 3. Optimized the address decoder logic to generate the CE's with common logic +-- 4. Address GAP decoding logic is removed and timeout counter is made active +-- for all transactions. +-- ^^^^^^ +-- ~~~~~~ +-- SK 12/16/12 -- v2.0 +-- 1. up reved to major version for 2013.1 Vivado release. No logic updates. +-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format +-- 3. updated the proc common version to proc_common_base_v5_0 +-- 4. No Logic Updates +-- ^^^^^^ +------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_cmb" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port "*_i" +-- device pins: "*_pin" +-- ports: - Names begin with Uppercase +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC> +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +use ieee.std_logic_misc.all; + +--library proc_common_base_v5_0; +--use proc_common_base_v5_0.ipif_pkg.all; + +library axi_lite_ipif_v3_0_4; + use axi_lite_ipif_v3_0_4.ipif_pkg.all; + +------------------------------------------------------------------------------- +-- Definition of Generics +------------------------------------------------------------------------------- +-- C_S_AXI_DATA_WIDTH -- AXI data bus width +-- C_S_AXI_ADDR_WIDTH -- AXI address bus width +-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP +-- C_USE_WSTRB -- Use write strobs or not +-- C_DPHASE_TIMEOUT -- Data phase time out counter +-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range +-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range +-- C_FAMILY -- Target FPGA family +------------------------------------------------------------------------------- +-- Definition of Ports +------------------------------------------------------------------------------- +-- S_AXI_ACLK -- AXI Clock +-- S_AXI_ARESETN -- AXI Reset +-- S_AXI_AWADDR -- AXI Write address +-- S_AXI_AWVALID -- Write address valid +-- S_AXI_AWREADY -- Write address ready +-- S_AXI_WDATA -- Write data +-- S_AXI_WSTRB -- Write strobes +-- S_AXI_WVALID -- Write valid +-- S_AXI_WREADY -- Write ready +-- S_AXI_BRESP -- Write response +-- S_AXI_BVALID -- Write response valid +-- S_AXI_BREADY -- Response ready +-- S_AXI_ARADDR -- Read address +-- S_AXI_ARVALID -- Read address valid +-- S_AXI_ARREADY -- Read address ready +-- S_AXI_RDATA -- Read data +-- S_AXI_RRESP -- Read response +-- S_AXI_RVALID -- Read valid +-- S_AXI_RREADY -- Read ready +-- Bus2IP_Clk -- Synchronization clock provided to User IP +-- Bus2IP_Reset -- Active high reset for use by the User IP +-- Bus2IP_Addr -- Desired address of read or write operation +-- Bus2IP_RNW -- Read or write indicator for the transaction +-- Bus2IP_BE -- Byte enables for the data bus +-- Bus2IP_CS -- Chip select for the transcations +-- Bus2IP_RdCE -- Chip enables for the read +-- Bus2IP_WrCE -- Chip enables for the write +-- Bus2IP_Data -- Write data bus to the User IP +-- IP2Bus_Data -- Input Read Data bus from the User IP +-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP +-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP +-- IP2Bus_Error -- Error signal from the IP +------------------------------------------------------------------------------- + +entity axi_lite_ipif is + generic ( + + C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; + C_S_AXI_ADDR_WIDTH : integer := 32; + C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; + C_USE_WSTRB : integer := 0; + C_DPHASE_TIMEOUT : integer range 0 to 512 := 8; + C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used + ( + X"0000_0000_7000_0000", -- IP user0 base address + X"0000_0000_7000_00FF", -- IP user0 high address + X"0000_0000_7000_0100", -- IP user1 base address + X"0000_0000_7000_01FF" -- IP user1 high address + ); + + C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used + ( + 4, -- User0 CE Number + 12 -- User1 CE Number + ); + C_FAMILY : string := "virtex6" + ); + port ( + + --System signals + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector + (C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector + (C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector + ((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector + (C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector + (C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + -- Controls to the IP/IPIF modules + Bus2IP_Clk : out std_logic; + Bus2IP_Resetn : out std_logic; + Bus2IP_Addr : out std_logic_vector + ((C_S_AXI_ADDR_WIDTH-1) downto 0); + Bus2IP_RNW : out std_logic; + Bus2IP_BE : out std_logic_vector + (((C_S_AXI_DATA_WIDTH/8)-1) downto 0); + Bus2IP_CS : out std_logic_vector + (((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0); + Bus2IP_RdCE : out std_logic_vector + ((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0); + Bus2IP_WrCE : out std_logic_vector + ((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0); + Bus2IP_Data : out std_logic_vector + ((C_S_AXI_DATA_WIDTH-1) downto 0); + IP2Bus_Data : in std_logic_vector + ((C_S_AXI_DATA_WIDTH-1) downto 0); + IP2Bus_WrAck : in std_logic; + IP2Bus_RdAck : in std_logic; + IP2Bus_Error : in std_logic + + ); + +end axi_lite_ipif; + +------------------------------------------------------------------------------- +-- Architecture +------------------------------------------------------------------------------- + +architecture imp of axi_lite_ipif is +---------------------------------------------------------------------------------- +-- below attributes are added to reduce the synth warnings in Vivado tool +attribute DowngradeIPIdentifiedWarnings: string; +attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; +---------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- Begin architecture logic +------------------------------------------------------------------------------- +begin + +------------------------------------------------------------------------------- +-- Slave Attachment +------------------------------------------------------------------------------- + +I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0_4.slave_attachment + generic map( + C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, + C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, + C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH, + C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH, + C_USE_WSTRB => C_USE_WSTRB, + C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, + C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, + C_FAMILY => C_FAMILY + ) + port map( + -- AXI signals + S_AXI_ACLK => S_AXI_ACLK, + S_AXI_ARESETN => S_AXI_ARESETN, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + -- IPIC signals + Bus2IP_Clk => Bus2IP_Clk, + Bus2IP_Resetn => Bus2IP_Resetn, + Bus2IP_Addr => Bus2IP_Addr, + Bus2IP_RNW => Bus2IP_RNW, + Bus2IP_BE => Bus2IP_BE, + Bus2IP_CS => Bus2IP_CS, + Bus2IP_RdCE => Bus2IP_RdCE, + Bus2IP_WrCE => Bus2IP_WrCE, + Bus2IP_Data => Bus2IP_Data, + IP2Bus_Data => IP2Bus_Data, + IP2Bus_WrAck => IP2Bus_WrAck, + IP2Bus_RdAck => IP2Bus_RdAck, + IP2Bus_Error => IP2Bus_Error + ); + +end imp; + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd new file mode 100644 index 0000000..f7bb80c --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd @@ -0,0 +1,1263 @@ + +--Generic Help +--C_CDC_TYPE : Defines the type of CDC needed +-- 0 means pulse synchronizer. Used to transfer one clock pulse +-- from prmry domain to scndry domain. +-- 1 means level synchronizer. Used to transfer level signal. +-- 2 means level synchronizer with ack. Used to transfer level +-- signal. Input signal should change only when prmry_ack is detected +-- +--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal +-- Set to 0 when incoming signal is purely floped signal. +-- +--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases +-- it might be needed. +-- 0 means reset not needed for sync flops +-- 1 means reset needed for sync flops. i +-- In this case prmry_resetn should be in prmry clock, +-- while scndry_reset should be in scndry clock. +-- +--C_SINGLE_BIT : CDC should normally be done for single bit signals only. +-- However, based on design buses can also be CDC'ed. +-- 0 means it is a bus. In this case input be connected to prmry_vect_in. +-- Output is on scndry_vect_out. +-- 1 means it is a single bit. In this case input be connected to prmry_in. +-- Output is on scndry_out. +-- +--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 +-- +--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. +-- Value of 0, 1 is allowed only for level CDC. +-- Min value for Pulse CDC is 2 +-- +--Whenever this file is used following XDC constraint has to be added + +-- set_false_path -to [get_pins -hier *cdc_to*/D] + + +--IO Ports +-- +-- prmry_aclk : clock of originating domain (source domain) +-- prmry_resetn : sync reset of originating clock domain (source domain) +-- prmry_in : input signal bit. This should be a pure flop output without +-- any combi logic. This is source. +-- prmry_vect_in : bus signal. From Source domain. +-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. +-- Used only when C_CDC_TYPE = 2 +-- scndry_aclk : destination clock. +-- scndry_resetn : sync reset of destination domain +-- scndry_out : sync'ed output in destination domain. Single bit. +-- scndry_vect_out : sync'ed output in destination domain. bus. + + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_misc.all; +library unisim; +use unisim.vcomponents.FDR; + + + +entity cdc_sync is + generic ( + C_CDC_TYPE : integer range 0 to 2 := 1 ; + -- 0 is pulse synch + -- 1 is level synch + -- 2 is ack based level sync + C_RESET_STATE : integer range 0 to 1 := 0 ; + -- 0 is reset not needed + -- 1 is reset needed + C_SINGLE_BIT : integer range 0 to 1 := 1 ; + -- 0 is bus input + -- 1 is single bit input + C_FLOP_INPUT : integer range 0 to 1 := 0 ; + C_VECTOR_WIDTH : integer range 0 to 64 := 32 ; + C_MTBF_STAGES : integer range 0 to 6 := 2 + -- Vector Data witdth + ); + + port ( + prmry_aclk : in std_logic ; -- + prmry_resetn : in std_logic ; -- + prmry_in : in std_logic ; -- + prmry_vect_in : in std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) ; -- + prmry_ack : out std_logic ; + -- + scndry_aclk : in std_logic ; -- + scndry_resetn : in std_logic ; -- + -- + -- Primary to Secondary Clock Crossing -- + scndry_out : out std_logic ; -- + -- + scndry_vect_out : out std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) -- + + ); + +end cdc_sync; + +------------------------------------------------------------------------------- +-- Architecture +------------------------------------------------------------------------------- +architecture implementation of cdc_sync is + +attribute DowngradeIPIdentifiedWarnings : string; +attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; + +--attribute DONT_TOUCH : STRING; +--attribute KEEP : STRING; +--attribute DONT_TOUCH of implementation : architecture is "yes"; +signal prmry_resetn1 : std_logic := '0'; +signal scndry_resetn1 : std_logic := '0'; +signal prmry_reset2 : std_logic := '0'; +signal scndry_reset2 : std_logic := '0'; +--attribute KEEP of prmry_resetn1 : signal is "true"; +--attribute KEEP of scndry_resetn1 : signal is "true"; + +------------------------------------------------------------------------------- +-- Functions +------------------------------------------------------------------------------- + +-- No Functions Declared + +------------------------------------------------------------------------------- +-- Constants Declarations +------------------------------------------------------------------------------- + +-- No Constants Declared + +------------------------------------------------------------------------------- +-- Begin architecture logic +------------------------------------------------------------------------------- +begin + +HAS_RESET : if C_RESET_STATE = 1 generate +begin +prmry_resetn1 <= prmry_resetn; +scndry_resetn1 <= scndry_resetn; + +end generate HAS_RESET; + +HAS_NO_RESET : if C_RESET_STATE = 0 generate +begin + +prmry_resetn1 <= '1'; +scndry_resetn1 <= '1'; + +end generate HAS_NO_RESET; + +prmry_reset2 <= not prmry_resetn1; +scndry_reset2 <= not scndry_resetn1; + + +-- Generate PULSE clock domain crossing +GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate + +-- Primary to Secondary +signal s_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; +signal s_out_d2 : std_logic := '0'; +signal s_out_d3 : std_logic := '0'; +signal s_out_d4 : std_logic := '0'; +signal s_out_d5 : std_logic := '0'; +signal s_out_d6 : std_logic := '0'; +signal s_out_d7 : std_logic := '0'; +signal s_out_re : std_logic := '0'; +signal prmry_in_xored : std_logic := '0'; +signal p_in_d1_cdc_from : std_logic := '0'; + +signal srst_d1 : std_logic := '0'; +signal srst_d2 : std_logic := '0'; +signal srst_d3 : std_logic := '0'; +signal srst_d4 : std_logic := '0'; +signal srst_d5 : std_logic := '0'; +signal srst_d6 : std_logic := '0'; +signal srst_d7 : std_logic := '0'; + + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; + ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Pulse Clock Crossing ** + --** PRIMARY TO SECONDARY OPEN-ENDED ** + --***************************************************************************** + +scndry_vect_out <= (others => '0'); +prmry_ack <= '0'; + +prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; + +--------------------------------------REG_P_IN : process(prmry_aclk) +-------------------------------------- begin +-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +-------------------------------------- p_in_d1_cdc_from <= '0'; +-------------------------------------- else +-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; +-------------------------------------- end if; +-------------------------------------- end if; +-------------------------------------- end process REG_P_IN; + + + +REG_P_IN_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_in_d1_cdc_from, + C => prmry_aclk, + D => prmry_in_xored, + R => prmry_reset2 + ); + + + + + +REG_P_IN2_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d1_cdc_to, + C => scndry_aclk, + D => p_in_d1_cdc_from, + R => scndry_reset2 + ); + + + +------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) +------------------------------------ begin +------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then +------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------------ s_out_d2 <= '0'; +------------------------------------ s_out_d3 <= '0'; +------------------------------------ s_out_d4 <= '0'; +------------------------------------ s_out_d5 <= '0'; +------------------------------------ s_out_d6 <= '0'; +------------------------------------ s_out_d7 <= '0'; +------------------------------------ scndry_out <= '0'; +------------------------------------ else +------------------------------------ s_out_d2 <= s_out_d1_cdc_to; +------------------------------------ s_out_d3 <= s_out_d2; +------------------------------------ s_out_d4 <= s_out_d3; +------------------------------------ s_out_d5 <= s_out_d4; +------------------------------------ s_out_d6 <= s_out_d5; +------------------------------------ s_out_d7 <= s_out_d6; +------------------------------------ scndry_out <= s_out_re; +------------------------------------ end if; +------------------------------------ end if; +------------------------------------ end process P_IN_CROSS2SCNDRY; + + + + +P_IN_CROSS2SCNDRY_s_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d2, + C => scndry_aclk, + D => s_out_d1_cdc_to, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d3, + C => scndry_aclk, + D => s_out_d2, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d4, + C => scndry_aclk, + D => s_out_d3, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d5, + C => scndry_aclk, + D => s_out_d4, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_s_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d6, + C => scndry_aclk, + D => s_out_d5, + R => scndry_reset2 + ); + + + +P_IN_CROSS2SCNDRY_s_out_d7 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_out_d7, + C => scndry_aclk, + D => s_out_d6, + R => scndry_reset2 + ); + + +P_IN_CROSS2SCNDRY_scndry_out : component FDR + generic map(INIT => '0' + )port map ( + Q => scndry_out, + C => scndry_aclk, + D => s_out_re, + R => scndry_reset2 + ); + +s_rst_d1 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d1, + C => scndry_aclk, + D => '1', + R => scndry_reset2 + ); +s_rst_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d2, + C => scndry_aclk, + D => srst_d1, + R => scndry_reset2 + ); +s_rst_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d3, + C => scndry_aclk, + D => srst_d2, + R => scndry_reset2 + ); + +s_rst_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d4, + C => scndry_aclk, + D => srst_d3, + R => scndry_reset2 + ); + + +s_rst_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d5, + C => scndry_aclk, + D => srst_d4, + R => scndry_reset2 + ); + +s_rst_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d6, + C => scndry_aclk, + D => srst_d5, + R => scndry_reset2 + ); + +s_rst_d7 : component FDR + generic map(INIT => '0' + )port map ( + Q => srst_d7, + C => scndry_aclk, + D => srst_d6, + R => scndry_reset2 + ); + +MTBF_2 : if C_MTBF_STAGES = 2 generate +begin + s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3); + +end generate MTBF_2; + +MTBF_3 : if C_MTBF_STAGES = 3 generate +begin + s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4); + +end generate MTBF_3; + +MTBF_4 : if C_MTBF_STAGES = 4 generate +begin + s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5); + +end generate MTBF_4; + +MTBF_5 : if C_MTBF_STAGES = 5 generate +begin + s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6); + +end generate MTBF_5; + +MTBF_6 : if C_MTBF_STAGES = 6 generate +begin + s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7); + +end generate MTBF_6; + + -- Feed secondary pulse out + +end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; + + +-- Generate LEVEL clock domain crossing with reset state = 0 +GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate +begin +-- Primary to Secondary + +SINGLE_BIT : if C_SINGLE_BIT = 1 generate + +signal p_level_in_d1_cdc_from : std_logic := '0'; +signal p_level_in_int : std_logic := '0'; +signal s_level_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; +signal s_level_out_d2 : std_logic := '0'; +signal s_level_out_d3 : std_logic := '0'; +signal s_level_out_d4 : std_logic := '0'; +signal s_level_out_d5 : std_logic := '0'; +signal s_level_out_d6 : std_logic := '0'; + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic + +scndry_vect_out <= (others => '0'); +prmry_ack <= '0'; + + +INPUT_FLOP : if C_FLOP_INPUT = 1 generate +begin + +---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) +---------------------------------- begin +---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +---------------------------------- p_level_in_d1_cdc_from <= '0'; +---------------------------------- else +---------------------------------- p_level_in_d1_cdc_from <= prmry_in; +---------------------------------- end if; +---------------------------------- end if; +---------------------------------- end process REG_PLEVEL_IN; + + +REG_PLEVEL_IN_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_in_d1_cdc_from, + C => prmry_aclk, + D => prmry_in, + R => prmry_reset2 + ); + + + p_level_in_int <= p_level_in_d1_cdc_from; + +end generate INPUT_FLOP; + + +NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate +begin + + p_level_in_int <= prmry_in; + +end generate NO_INPUT_FLOP; + + +CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d1_cdc_to, + C => scndry_aclk, + D => p_level_in_int, + R => scndry_reset2 + ); + + +------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) +------------------------------ begin +------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then +------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------ s_level_out_d2 <= '0'; +------------------------------ s_level_out_d3 <= '0'; +------------------------------ s_level_out_d4 <= '0'; +------------------------------ s_level_out_d5 <= '0'; +------------------------------ s_level_out_d6 <= '0'; +------------------------------ else +------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; +------------------------------ s_level_out_d3 <= s_level_out_d2; +------------------------------ s_level_out_d4 <= s_level_out_d3; +------------------------------ s_level_out_d5 <= s_level_out_d4; +------------------------------ s_level_out_d6 <= s_level_out_d5; +------------------------------ end if; +------------------------------ end if; +------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; + + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d2, + C => scndry_aclk, + D => s_level_out_d1_cdc_to, + R => scndry_reset2 + ); + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d3, + C => scndry_aclk, + D => s_level_out_d2, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d4, + C => scndry_aclk, + D => s_level_out_d3, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d5, + C => scndry_aclk, + D => s_level_out_d4, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d6, + C => scndry_aclk, + D => s_level_out_d5, + R => scndry_reset2 + ); + + + + + + + +MTBF_L1 : if C_MTBF_STAGES = 1 generate +begin + scndry_out <= s_level_out_d1_cdc_to; + + +end generate MTBF_L1; + +MTBF_L2 : if C_MTBF_STAGES = 2 generate +begin + + scndry_out <= s_level_out_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_out <= s_level_out_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_out <= s_level_out_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_out <= s_level_out_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_out <= s_level_out_d6; + + +end generate MTBF_L6; + +end generate SINGLE_BIT; + + + +MULTI_BIT : if C_SINGLE_BIT = 0 generate + +signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); +signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; +signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; + -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic + +scndry_out <= '0'; +prmry_ack <= '0'; + + +INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate +begin + + + +----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) +----------------------------------- begin +----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); +----------------------------------- else +----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; +----------------------------------- end if; +----------------------------------- end if; +----------------------------------- end process REG_PLEVEL_IN; + +FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate +begin + +REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_in_bus_d1_cdc_from (i), + C => prmry_aclk, + D => prmry_vect_in (i), + R => prmry_reset2 + ); +end generate FOR_REG_PLEVEL_IN; + + + + + + p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; + +end generate INPUT_FLOP_BUS; + + +NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate +begin + +p_level_in_bus_int <= prmry_vect_in; + +end generate NO_INPUT_FLOP_BUS; + +FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d1_cdc_to (i), + C => scndry_aclk, + D => p_level_in_bus_int (i), + R => scndry_reset2 + ); +end generate FOR_IN_cdc_to; + +----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) +----------------------------------------- begin +----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then +----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +----------------------------------------- s_level_out_bus_d2 <= (others => '0'); +----------------------------------------- s_level_out_bus_d3 <= (others => '0'); +----------------------------------------- s_level_out_bus_d4 <= (others => '0'); +----------------------------------------- s_level_out_bus_d5 <= (others => '0'); +----------------------------------------- s_level_out_bus_d6 <= (others => '0'); +----------------------------------------- else +----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; +----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; +----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; +----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; +----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; +----------------------------------------- end if; +----------------------------------------- end if; +----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; + + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d2 (i), + C => scndry_aclk, + D => s_level_out_bus_d1_cdc_to (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d3 (i), + C => scndry_aclk, + D => s_level_out_bus_d2 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d4 (i), + C => scndry_aclk, + D => s_level_out_bus_d3 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; + + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d5 (i), + C => scndry_aclk, + D => s_level_out_bus_d4 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; + + +FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate + + ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; +begin + +CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_bus_d6 (i), + C => scndry_aclk, + D => s_level_out_bus_d5 (i), + R => scndry_reset2 + ); +end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; + + + +MTBF_L1 : if C_MTBF_STAGES = 1 generate +begin + + scndry_vect_out <= s_level_out_bus_d1_cdc_to; + + +end generate MTBF_L1; + +MTBF_L2 : if C_MTBF_STAGES = 2 generate +begin + + scndry_vect_out <= s_level_out_bus_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_vect_out <= s_level_out_bus_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_vect_out <= s_level_out_bus_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_vect_out <= s_level_out_bus_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_vect_out <= s_level_out_bus_d6; + + +end generate MTBF_L6; + +end generate MULTI_BIT; + + +end generate GENERATE_LEVEL_P_S_CDC; + + +GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate +-- Primary to Secondary + + +signal p_level_in_d1_cdc_from : std_logic := '0'; +signal p_level_in_int : std_logic := '0'; +signal s_level_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; +signal s_level_out_d2 : std_logic := '0'; +signal s_level_out_d3 : std_logic := '0'; +signal s_level_out_d4 : std_logic := '0'; +signal s_level_out_d5 : std_logic := '0'; +signal s_level_out_d6 : std_logic := '0'; +signal p_level_out_d1_cdc_to : std_logic := '0'; +--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; +signal p_level_out_d2 : std_logic := '0'; +signal p_level_out_d3 : std_logic := '0'; +signal p_level_out_d4 : std_logic := '0'; +signal p_level_out_d5 : std_logic := '0'; +signal p_level_out_d6 : std_logic := '0'; +signal p_level_out_d7 : std_logic := '0'; +signal scndry_out_int : std_logic := '0'; +signal prmry_pulse_ack : std_logic := '0'; + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; + + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; + ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic +scndry_vect_out <= (others => '0'); + + +INPUT_FLOP : if C_FLOP_INPUT = 1 generate +begin + +------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) +------------------------------------------ begin +------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then +------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------------------ p_level_in_d1_cdc_from <= '0'; +------------------------------------------ else +------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; +------------------------------------------ end if; +------------------------------------------ end if; +------------------------------------------ end process REG_PLEVEL_IN; + + + +REG_PLEVEL_IN_cdc_from : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_in_d1_cdc_from, + C => prmry_aclk, + D => prmry_in, + R => prmry_reset2 + ); + + + p_level_in_int <= p_level_in_d1_cdc_from; + +end generate INPUT_FLOP; + + +NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate +begin + + p_level_in_int <= prmry_in; + +end generate NO_INPUT_FLOP; + + +CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d1_cdc_to, + C => scndry_aclk, + D => p_level_in_int, + R => scndry_reset2 + ); + + +------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) +------------------------------------------------ begin +------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then +------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +------------------------------------------------ s_level_out_d2 <= '0'; +------------------------------------------------ s_level_out_d3 <= '0'; +------------------------------------------------ s_level_out_d4 <= '0'; +------------------------------------------------ s_level_out_d5 <= '0'; +------------------------------------------------ s_level_out_d6 <= '0'; +------------------------------------------------ else +------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; +------------------------------------------------ s_level_out_d3 <= s_level_out_d2; +------------------------------------------------ s_level_out_d4 <= s_level_out_d3; +------------------------------------------------ s_level_out_d5 <= s_level_out_d4; +------------------------------------------------ s_level_out_d6 <= s_level_out_d5; +------------------------------------------------ end if; +------------------------------------------------ end if; +------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; + + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d2, + C => scndry_aclk, + D => s_level_out_d1_cdc_to, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d3, + C => scndry_aclk, + D => s_level_out_d2, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d4, + C => scndry_aclk, + D => s_level_out_d3, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d5, + C => scndry_aclk, + D => s_level_out_d4, + R => scndry_reset2 + ); + + +CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => s_level_out_d6, + C => scndry_aclk, + D => s_level_out_d5, + R => scndry_reset2 + ); + + + + + + + + +--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) +--------------------------------------------------- begin +--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then +--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then +--------------------------------------------------- p_level_out_d1_cdc_to <= '0'; +--------------------------------------------------- p_level_out_d2 <= '0'; +--------------------------------------------------- p_level_out_d3 <= '0'; +--------------------------------------------------- p_level_out_d4 <= '0'; +--------------------------------------------------- p_level_out_d5 <= '0'; +--------------------------------------------------- p_level_out_d6 <= '0'; +--------------------------------------------------- p_level_out_d7 <= '0'; +--------------------------------------------------- prmry_ack <= '0'; +--------------------------------------------------- else +--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; +--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; +--------------------------------------------------- p_level_out_d3 <= p_level_out_d2; +--------------------------------------------------- p_level_out_d4 <= p_level_out_d3; +--------------------------------------------------- p_level_out_d5 <= p_level_out_d4; +--------------------------------------------------- p_level_out_d6 <= p_level_out_d5; +--------------------------------------------------- p_level_out_d7 <= p_level_out_d6; +--------------------------------------------------- prmry_ack <= prmry_pulse_ack; +--------------------------------------------------- end if; +--------------------------------------------------- end if; +--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; + + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d1_cdc_to, + C => prmry_aclk, + D => scndry_out_int, + R => prmry_reset2 + ); + + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d2, + C => prmry_aclk, + D => p_level_out_d1_cdc_to, + R => prmry_reset2 + ); + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d3, + C => prmry_aclk, + D => p_level_out_d2, + R => prmry_reset2 + ); + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d4, + C => prmry_aclk, + D => p_level_out_d3, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d5, + C => prmry_aclk, + D => p_level_out_d4, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d6, + C => prmry_aclk, + D => p_level_out_d5, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR + generic map(INIT => '0' + )port map ( + Q => p_level_out_d7, + C => prmry_aclk, + D => p_level_out_d6, + R => prmry_reset2 + ); + + +CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR + generic map(INIT => '0' + )port map ( + Q => prmry_ack, + C => prmry_aclk, + D => prmry_pulse_ack, + R => prmry_reset2 + ); + + + + + + + + + + + + + + + +MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate +begin + + scndry_out_int <= s_level_out_d2; + --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; + prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_out_int <= s_level_out_d3; + --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; + prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_out_int <= s_level_out_d4; + --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; + prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_out_int <= s_level_out_d5; + --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; + prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_out_int <= s_level_out_d6; + --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; + prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; + + +end generate MTBF_L6; + + scndry_out <= scndry_out_int; + + +end generate GENERATE_LEVEL_ACK_P_S_CDC; + + +end implementation; + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/sim/design_1.v b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/sim/design_1.v new file mode 100644 index 0000000..80e6e94 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/sim/design_1.v @@ -0,0 +1,96 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +//Date : Tue Jun 30 17:32:55 2020 +//Host : PC2018 running 64-bit Service Pack 1 (build 7601) +//Command : generate_target design_1.bd +//Design : design_1 +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}" *) (* HW_HANDOFF = "design_1.hwdef" *) +module design_1 + (clk, + gpio_in, + gpio_io_t_0, + gpio_out, + rstn); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_RESET rstn, CLK_DOMAIN design_1_m00_axi_aclk_0, FREQ_HZ 100000000, PHASE 0.000" *) input clk; + input [31:0]gpio_in; + output [31:0]gpio_io_t_0; + output [31:0]gpio_out; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RSTN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RSTN, POLARITY ACTIVE_LOW" *) input rstn; + + wire [31:0]axi_gpio_0_gpio_io_o; + wire [31:0]axi_gpio_0_gpio_io_t; + wire [31:0]gpio_io_i_0_1; + wire m00_axi_aclk_0_1; + wire m00_axi_aresetn_0_1; + wire [31:0]xjtag_axi_0_m00_axi_ARADDR; + wire xjtag_axi_0_m00_axi_ARREADY; + wire xjtag_axi_0_m00_axi_ARVALID; + wire [31:0]xjtag_axi_0_m00_axi_AWADDR; + wire xjtag_axi_0_m00_axi_AWREADY; + wire xjtag_axi_0_m00_axi_AWVALID; + wire xjtag_axi_0_m00_axi_BREADY; + wire [1:0]xjtag_axi_0_m00_axi_BRESP; + wire xjtag_axi_0_m00_axi_BVALID; + wire [31:0]xjtag_axi_0_m00_axi_RDATA; + wire xjtag_axi_0_m00_axi_RREADY; + wire [1:0]xjtag_axi_0_m00_axi_RRESP; + wire xjtag_axi_0_m00_axi_RVALID; + wire [31:0]xjtag_axi_0_m00_axi_WDATA; + wire xjtag_axi_0_m00_axi_WREADY; + wire [3:0]xjtag_axi_0_m00_axi_WSTRB; + wire xjtag_axi_0_m00_axi_WVALID; + + assign gpio_io_i_0_1 = gpio_in[31:0]; + assign gpio_io_t_0[31:0] = axi_gpio_0_gpio_io_t; + assign gpio_out[31:0] = axi_gpio_0_gpio_io_o; + assign m00_axi_aclk_0_1 = clk; + assign m00_axi_aresetn_0_1 = rstn; + design_1_axi_gpio_0_0 axi_gpio_0 + (.gpio_io_i(gpio_io_i_0_1), + .gpio_io_o(axi_gpio_0_gpio_io_o), + .gpio_io_t(axi_gpio_0_gpio_io_t), + .s_axi_aclk(m00_axi_aclk_0_1), + .s_axi_araddr(xjtag_axi_0_m00_axi_ARADDR[8:0]), + .s_axi_aresetn(m00_axi_aresetn_0_1), + .s_axi_arready(xjtag_axi_0_m00_axi_ARREADY), + .s_axi_arvalid(xjtag_axi_0_m00_axi_ARVALID), + .s_axi_awaddr(xjtag_axi_0_m00_axi_AWADDR[8:0]), + .s_axi_awready(xjtag_axi_0_m00_axi_AWREADY), + .s_axi_awvalid(xjtag_axi_0_m00_axi_AWVALID), + .s_axi_bready(xjtag_axi_0_m00_axi_BREADY), + .s_axi_bresp(xjtag_axi_0_m00_axi_BRESP), + .s_axi_bvalid(xjtag_axi_0_m00_axi_BVALID), + .s_axi_rdata(xjtag_axi_0_m00_axi_RDATA), + .s_axi_rready(xjtag_axi_0_m00_axi_RREADY), + .s_axi_rresp(xjtag_axi_0_m00_axi_RRESP), + .s_axi_rvalid(xjtag_axi_0_m00_axi_RVALID), + .s_axi_wdata(xjtag_axi_0_m00_axi_WDATA), + .s_axi_wready(xjtag_axi_0_m00_axi_WREADY), + .s_axi_wstrb(xjtag_axi_0_m00_axi_WSTRB), + .s_axi_wvalid(xjtag_axi_0_m00_axi_WVALID)); + design_1_xjtag_axi_0_0 xjtag_axi_0 + (.m00_axi_aclk(m00_axi_aclk_0_1), + .m00_axi_araddr(xjtag_axi_0_m00_axi_ARADDR), + .m00_axi_aresetn(m00_axi_aresetn_0_1), + .m00_axi_arready(xjtag_axi_0_m00_axi_ARREADY), + .m00_axi_arvalid(xjtag_axi_0_m00_axi_ARVALID), + .m00_axi_awaddr(xjtag_axi_0_m00_axi_AWADDR), + .m00_axi_awready(xjtag_axi_0_m00_axi_AWREADY), + .m00_axi_awvalid(xjtag_axi_0_m00_axi_AWVALID), + .m00_axi_bready(xjtag_axi_0_m00_axi_BREADY), + .m00_axi_bresp(xjtag_axi_0_m00_axi_BRESP), + .m00_axi_bvalid(xjtag_axi_0_m00_axi_BVALID), + .m00_axi_rdata(xjtag_axi_0_m00_axi_RDATA), + .m00_axi_rready(xjtag_axi_0_m00_axi_RREADY), + .m00_axi_rresp(xjtag_axi_0_m00_axi_RRESP), + .m00_axi_rvalid(xjtag_axi_0_m00_axi_RVALID), + .m00_axi_wdata(xjtag_axi_0_m00_axi_WDATA), + .m00_axi_wready(xjtag_axi_0_m00_axi_WREADY), + .m00_axi_wstrb(xjtag_axi_0_m00_axi_WSTRB), + .m00_axi_wvalid(xjtag_axi_0_m00_axi_WVALID)); +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.hwdef b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.hwdef new file mode 100644 index 0000000..1d236d0 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.hwdef differ diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.v b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.v new file mode 100644 index 0000000..80e6e94 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/synth/design_1.v @@ -0,0 +1,96 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +//Date : Tue Jun 30 17:32:55 2020 +//Host : PC2018 running 64-bit Service Pack 1 (build 7601) +//Command : generate_target design_1.bd +//Design : design_1 +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}" *) (* HW_HANDOFF = "design_1.hwdef" *) +module design_1 + (clk, + gpio_in, + gpio_io_t_0, + gpio_out, + rstn); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_RESET rstn, CLK_DOMAIN design_1_m00_axi_aclk_0, FREQ_HZ 100000000, PHASE 0.000" *) input clk; + input [31:0]gpio_in; + output [31:0]gpio_io_t_0; + output [31:0]gpio_out; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RSTN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RSTN, POLARITY ACTIVE_LOW" *) input rstn; + + wire [31:0]axi_gpio_0_gpio_io_o; + wire [31:0]axi_gpio_0_gpio_io_t; + wire [31:0]gpio_io_i_0_1; + wire m00_axi_aclk_0_1; + wire m00_axi_aresetn_0_1; + wire [31:0]xjtag_axi_0_m00_axi_ARADDR; + wire xjtag_axi_0_m00_axi_ARREADY; + wire xjtag_axi_0_m00_axi_ARVALID; + wire [31:0]xjtag_axi_0_m00_axi_AWADDR; + wire xjtag_axi_0_m00_axi_AWREADY; + wire xjtag_axi_0_m00_axi_AWVALID; + wire xjtag_axi_0_m00_axi_BREADY; + wire [1:0]xjtag_axi_0_m00_axi_BRESP; + wire xjtag_axi_0_m00_axi_BVALID; + wire [31:0]xjtag_axi_0_m00_axi_RDATA; + wire xjtag_axi_0_m00_axi_RREADY; + wire [1:0]xjtag_axi_0_m00_axi_RRESP; + wire xjtag_axi_0_m00_axi_RVALID; + wire [31:0]xjtag_axi_0_m00_axi_WDATA; + wire xjtag_axi_0_m00_axi_WREADY; + wire [3:0]xjtag_axi_0_m00_axi_WSTRB; + wire xjtag_axi_0_m00_axi_WVALID; + + assign gpio_io_i_0_1 = gpio_in[31:0]; + assign gpio_io_t_0[31:0] = axi_gpio_0_gpio_io_t; + assign gpio_out[31:0] = axi_gpio_0_gpio_io_o; + assign m00_axi_aclk_0_1 = clk; + assign m00_axi_aresetn_0_1 = rstn; + design_1_axi_gpio_0_0 axi_gpio_0 + (.gpio_io_i(gpio_io_i_0_1), + .gpio_io_o(axi_gpio_0_gpio_io_o), + .gpio_io_t(axi_gpio_0_gpio_io_t), + .s_axi_aclk(m00_axi_aclk_0_1), + .s_axi_araddr(xjtag_axi_0_m00_axi_ARADDR[8:0]), + .s_axi_aresetn(m00_axi_aresetn_0_1), + .s_axi_arready(xjtag_axi_0_m00_axi_ARREADY), + .s_axi_arvalid(xjtag_axi_0_m00_axi_ARVALID), + .s_axi_awaddr(xjtag_axi_0_m00_axi_AWADDR[8:0]), + .s_axi_awready(xjtag_axi_0_m00_axi_AWREADY), + .s_axi_awvalid(xjtag_axi_0_m00_axi_AWVALID), + .s_axi_bready(xjtag_axi_0_m00_axi_BREADY), + .s_axi_bresp(xjtag_axi_0_m00_axi_BRESP), + .s_axi_bvalid(xjtag_axi_0_m00_axi_BVALID), + .s_axi_rdata(xjtag_axi_0_m00_axi_RDATA), + .s_axi_rready(xjtag_axi_0_m00_axi_RREADY), + .s_axi_rresp(xjtag_axi_0_m00_axi_RRESP), + .s_axi_rvalid(xjtag_axi_0_m00_axi_RVALID), + .s_axi_wdata(xjtag_axi_0_m00_axi_WDATA), + .s_axi_wready(xjtag_axi_0_m00_axi_WREADY), + .s_axi_wstrb(xjtag_axi_0_m00_axi_WSTRB), + .s_axi_wvalid(xjtag_axi_0_m00_axi_WVALID)); + design_1_xjtag_axi_0_0 xjtag_axi_0 + (.m00_axi_aclk(m00_axi_aclk_0_1), + .m00_axi_araddr(xjtag_axi_0_m00_axi_ARADDR), + .m00_axi_aresetn(m00_axi_aresetn_0_1), + .m00_axi_arready(xjtag_axi_0_m00_axi_ARREADY), + .m00_axi_arvalid(xjtag_axi_0_m00_axi_ARVALID), + .m00_axi_awaddr(xjtag_axi_0_m00_axi_AWADDR), + .m00_axi_awready(xjtag_axi_0_m00_axi_AWREADY), + .m00_axi_awvalid(xjtag_axi_0_m00_axi_AWVALID), + .m00_axi_bready(xjtag_axi_0_m00_axi_BREADY), + .m00_axi_bresp(xjtag_axi_0_m00_axi_BRESP), + .m00_axi_bvalid(xjtag_axi_0_m00_axi_BVALID), + .m00_axi_rdata(xjtag_axi_0_m00_axi_RDATA), + .m00_axi_rready(xjtag_axi_0_m00_axi_RREADY), + .m00_axi_rresp(xjtag_axi_0_m00_axi_RRESP), + .m00_axi_rvalid(xjtag_axi_0_m00_axi_RVALID), + .m00_axi_wdata(xjtag_axi_0_m00_axi_WDATA), + .m00_axi_wready(xjtag_axi_0_m00_axi_WREADY), + .m00_axi_wstrb(xjtag_axi_0_m00_axi_WSTRB), + .m00_axi_wvalid(xjtag_axi_0_m00_axi_WVALID)); +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui new file mode 100644 index 0000000..45e0365 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui @@ -0,0 +1,21 @@ +{ + ExpandedHierarchyInLayout: "", + guistr: "# # String gsaved with Nlview 6.8.5 2018-01-30 bk=1.4354 VDI=40 GEI=35 GUI=JA:1.6 non-TLS +# -string -flagsOSRD +preplace port rstn -pg 1 -y -140 -defaultsOSRD +preplace port clk -pg 1 -y -160 -defaultsOSRD +preplace portBus gpio_io_t_0 -pg 1 -y -100 -defaultsOSRD +preplace portBus gpio_out -pg 1 -y -130 -defaultsOSRD +preplace portBus gpio_in -pg 1 -y -50 -defaultsOSRD +preplace inst xjtag_axi_0 -pg 1 -lvl 1 -y -150 -defaultsOSRD +preplace inst axi_gpio_0 -pg 1 -lvl 2 -y -130 -defaultsOSRD +preplace netloc gpio_io_i_0_1 1 0 3 30J -40 NJ -40 740 +preplace netloc xjtag_axi_0_m00_axi 1 1 1 N +preplace netloc m00_axi_aclk_0_1 1 0 2 30 -80 450 +preplace netloc axi_gpio_0_gpio_io_o 1 2 1 750 +preplace netloc m00_axi_aresetn_0_1 1 0 2 20 -70 460 +preplace netloc axi_gpio_0_gpio_io_t 1 2 1 N +levelinfo -pg 1 0 320 600 780 -top -520 -bot 140 +", +} +0 diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/imports/hdl/design_1_wrapper.v b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/imports/hdl/design_1_wrapper.v new file mode 100644 index 0000000..4bb8f94 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/imports/hdl/design_1_wrapper.v @@ -0,0 +1,36 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +//Date : Tue Jun 30 09:08:59 2020 +//Host : PC2018 running 64-bit Service Pack 1 (build 7601) +//Command : generate_target design_1_wrapper.bd +//Design : design_1_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module design_1_wrapper + (clk, + gpio_in, + gpio_io_t_0, + gpio_out, + rstn); + input clk; + input [31:0]gpio_in; + output [31:0]gpio_io_t_0; + output [31:0]gpio_out; + input rstn; + + wire clk; + wire [31:0]gpio_in; + wire [31:0]gpio_io_t_0; + wire [31:0]gpio_out; + wire rstn; + + design_1 design_1_i + (.clk(clk), + .gpio_in(gpio_in), + .gpio_io_t_0(gpio_io_t_0), + .gpio_out(gpio_out), + .rstn(rstn)); +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp new file mode 100644 index 0000000..df33166 Binary files /dev/null and b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp differ diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v new file mode 100644 index 0000000..854c268 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v @@ -0,0 +1,92 @@ + +// file: clk_wiz_0.v +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1___100.000______0.000______50.0______112.316_____89.971 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________200.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_1_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) + +module clk_wiz_0 + ( + // Clock out ports + output clk_out1, + // Status and control signals + output locked, + // Clock in ports + input clk_in1_p, + input clk_in1_n + ); + + clk_wiz_0_clk_wiz inst + ( + // Clock out ports + .clk_out1(clk_out1), + // Status and control signals + .locked(locked), + // Clock in ports + .clk_in1_p(clk_in1_p), + .clk_in1_n(clk_in1_n) + ); + +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo new file mode 100644 index 0000000..3bd2de6 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo @@ -0,0 +1,80 @@ + +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1___100.000______0.000______50.0______112.316_____89.971 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________200.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clk_wiz_0 instance_name + ( + // Clock out ports + .clk_out1(clk_out1), // output clk_out1 + // Status and control signals + .locked(locked), // output locked + // Clock in ports + .clk_in1_p(clk_in1_p), // input clk_in1_p + .clk_in1_n(clk_in1_n)); // input clk_in1_n +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci new file mode 100644 index 0000000..2530c39 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -0,0 +1,665 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_0 + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 100.0 + 0000 + 0000 + 100.000 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 1.0 + 1.0 + 1.0 + 1.0 + 1.0 + 1.0 + dout + drdy + dwe + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________200.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 5.000 + 0.000 + FALSE + 5.000 + 10.0 + 10.000 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 1 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out1___100.000______0.000______50.0______112.316_____89.971 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 200.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + clk_wiz_0 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 0.010 + 100.0 + 0.010 + BUFG + 112.316 + false + 89.971 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_0 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 5.000 + 0.000 + false + 5.000 + 10.0 + 10.000 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 1 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 200.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + false + false + false + false + kintex7 + + xc7k160t + ffg676 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2018.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc new file mode 100644 index 0000000..8593fa9 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc @@ -0,0 +1,60 @@ + +# file: clk_wiz_0.xdc +# +# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system. If required +# commented constraints can be used in the top level xdc +#---------------------------------------------------------------- +# Differential clock only needs one constraint +create_clock -period 5.000 [get_ports clk_in1_p] +set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.05 + + +set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml new file mode 100644 index 0000000..d38d8a9 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml @@ -0,0 +1,4720 @@ + + + xilinx.com + customized_ip + clk_wiz_0 + 1.0 + + + s_axi_lite + S_AXI_LITE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 1 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 0 + + + none + + + + + HAS_BRESP + 0 + + + none + + + + + HAS_RRESP + 0 + + + none + + + + + SUPPORTS_NARROW_BURST + 0 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + + false + + + + + + s_axi_aclk + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi_lite + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + + false + + + + + + ref_clk + ref_clk + + + + + + + CLK + + + ref_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + + false + + + + + + s_axi_resetn + S_AXI_RESETN + + + + + + + RST + + + s_axi_aresetn + + + + + + ASSOCIATED_RESET + aresetn + + + POLARITY + ACTIVE_LOW + + + + + + false + + + + + + intr + Intr + + + + + + + INTERRUPT + + + ip2intc_irpt + + + + + + SENSITIVITY + LEVEL_HIGH + + + none + + + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + CLK_IN1_D + CLK_IN1_D + Differential Clock input + + + + + + + CLK_N + + + clk_in1_n + + + + + CLK_P + + + clk_in1_p + + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN1_BOARD_INTERFACE + + + + required + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + true + + + + + + CLK_IN2_D + CLK_IN2_D + Differential Clock input + + + + + + + CLK_N + + + clk_in2_n + + + + + CLK_P + + + clk_in2_p + + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN2_BOARD_INTERFACE + + + + required + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_IN_D + CLKFB_IN_D + Differential Feedback Clock input + + + + + + + CLK_N + + + clkfb_in_n + + + + + CLK_P + + + clkfb_in_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_OUT_D + CLKFB_OUT_D + Differential Feeback Clock Output + + + + + + + CLK_N + + + clkfb_out_n + + + + + CLK_P + + + clkfb_out_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + reset + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_HIGH + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + + + + false + + + + + + resetn + resetn + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + + + + false + + + + + + clock_CLK_OUT1 + + + + + + + CLK_OUT1 + + + clk_out1 + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + + + + xilinx_elaborateports + Elaborate Ports + :vivado.xilinx.com:elaborate.ports + + + outputProductCRC + 8:1689d374 + + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + clk_wiz_v6_0_1 + + xilinx_veriloginstantiationtemplate_view_fileset + + + + GENtimestamp + Sun Jun 28 09:09:27 UTC 2020 + + + outputProductCRC + 8:6474a35d + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + clk_wiz_v6_0_1 + + xilinx_anylanguagesynthesis_view_fileset + + + + GENtimestamp + Sun Jun 28 09:09:29 UTC 2020 + + + outputProductCRC + 8:6474a35d + + + + + xilinx_anylanguagesynthesiswrapper + Synthesis Wrapper + :vivado.xilinx.com:synthesis.wrapper + clk_wiz_0 + + xilinx_anylanguagesynthesiswrapper_view_fileset + + + + GENtimestamp + Sun Jun 28 09:09:29 UTC 2020 + + + outputProductCRC + 8:6474a35d + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + clk_wiz_v6_0_1 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Sun Jun 28 09:09:29 UTC 2020 + + + outputProductCRC + 8:6bd797fc + + + + + xilinx_anylanguagesimulationwrapper + Simulation Wrapper + :vivado.xilinx.com:simulation.wrapper + clk_wiz_0 + + xilinx_anylanguagesimulationwrapper_view_fileset + + + + GENtimestamp + Sun Jun 28 09:09:29 UTC 2020 + + + outputProductCRC + 8:6bd797fc + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + GENtimestamp + Sun Jun 28 09:09:30 UTC 2020 + + + outputProductCRC + 8:6474a35d + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + GENtimestamp + Sun Jun 28 09:09:30 UTC 2020 + + + outputProductCRC + 8:6474a35d + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Sun Jun 28 09:10:06 UTC 2020 + + + outputProductCRC + 8:6474a35d + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awaddr + + in + + 10 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awready + + out + + + std_logic + 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C_USE_FREQ_SYNTH + 1 + + + C_USE_PHASE_ALIGNMENT + 1 + + + C_PRIM_IN_JITTER + 0.010 + + + C_SECONDARY_IN_JITTER + 0.010 + + + C_JITTER_SEL + No_Jitter + + + C_USE_MIN_POWER + 0 + + + C_USE_MIN_O_JITTER + 0 + + + C_USE_MAX_I_JITTER + 0 + + + C_USE_DYN_PHASE_SHIFT + 0 + + + C_USE_INCLK_SWITCHOVER + 0 + + + C_USE_DYN_RECONFIG + 0 + + + C_USE_SPREAD_SPECTRUM + 0 + + + C_USE_FAST_SIMULATION + 0 + + + C_PRIMTYPE_SEL + AUTO + + + C_USE_CLK_VALID + 0 + + + C_PRIM_IN_FREQ + 200.000 + + + C_PRIM_IN_TIMEPERIOD + 10.000 + + + C_IN_FREQ_UNITS + Units_MHz + + + C_SECONDARY_IN_FREQ + 100.000 + + + C_SECONDARY_IN_TIMEPERIOD + 10.000 + + + C_FEEDBACK_SOURCE + FDBK_AUTO + + + C_PRIM_SOURCE + Differential_clock_capable_pin + + + C_PHASESHIFT_MODE + WAVEFORM + + + C_SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + C_CLKFB_IN_SIGNALING + SINGLE + + + C_USE_RESET + 0 + + + C_RESET_LOW + 0 + + + C_USE_LOCKED + 1 + + + C_USE_INCLK_STOPPED + 0 + + + C_USE_CLKFB_STOPPED + 0 + + + C_USE_POWER_DOWN + 0 + + + C_USE_STATUS + 0 + + + C_USE_FREEZE + 0 + + + C_NUM_OUT_CLKS + 1 + + + C_CLKOUT1_DRIVES + BUFG + + + C_CLKOUT2_DRIVES + BUFG + + + C_CLKOUT3_DRIVES + BUFG + + + C_CLKOUT4_DRIVES + BUFG + + + C_CLKOUT5_DRIVES + BUFG + + + C_CLKOUT6_DRIVES + BUFG + + + C_CLKOUT7_DRIVES + BUFG + + + C_INCLK_SUM_ROW0 + Input Clock Freq (MHz) Input Jitter (UI) + + + C_INCLK_SUM_ROW1 + __primary_________200.000____________0.010 + + + C_INCLK_SUM_ROW2 + no_secondary_input_clock + + + C_OUTCLK_SUM_ROW0A + C Outclk Sum Row0a + Output Output Phase Duty Cycle Pk-to-Pk Phase + + + C_OUTCLK_SUM_ROW0B + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + + + C_OUTCLK_SUM_ROW1 + clk_out1___100.000______0.000______50.0______112.316_____89.971 + + + C_OUTCLK_SUM_ROW2 + no_CLK_OUT2_output + + + C_OUTCLK_SUM_ROW3 + no_CLK_OUT3_output + + + C_OUTCLK_SUM_ROW4 + no_CLK_OUT4_output + + + C_OUTCLK_SUM_ROW5 + no_CLK_OUT5_output + + + C_OUTCLK_SUM_ROW6 + no_CLK_OUT6_output + + + C_OUTCLK_SUM_ROW7 + no_CLK_OUT7_output + + + C_CLKOUT1_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT1_REQUESTED_PHASE + 0.000 + + + C_CLKOUT2_REQUESTED_PHASE + 0.000 + + + C_CLKOUT3_REQUESTED_PHASE + 0.000 + + + C_CLKOUT4_REQUESTED_PHASE + 0.000 + + + C_CLKOUT5_REQUESTED_PHASE + 0.000 + + + C_CLKOUT6_REQUESTED_PHASE + 0.000 + + + C_CLKOUT7_REQUESTED_PHASE + 0.000 + + + C_CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT1_OUT_FREQ + 100.000 + + + C_CLKOUT2_OUT_FREQ + 100.000 + + + C_CLKOUT3_OUT_FREQ + 100.000 + + + C_CLKOUT4_OUT_FREQ + 100.000 + + + C_CLKOUT5_OUT_FREQ + 100.000 + + + C_CLKOUT6_OUT_FREQ + 100.000 + + + C_CLKOUT7_OUT_FREQ + 100.000 + + + C_CLKOUT1_PHASE + 0.000 + + + C_CLKOUT2_PHASE + 0.000 + + + C_CLKOUT3_PHASE + 0.000 + + + C_CLKOUT4_PHASE + 0.000 + + + C_CLKOUT5_PHASE + 0.000 + + + C_CLKOUT6_PHASE + 0.000 + + + C_CLKOUT7_PHASE + 0.000 + + + C_CLKOUT1_DUTY_CYCLE + 50.0 + + + C_CLKOUT2_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_DUTY_CYCLE + 50.000 + + + C_USE_SAFE_CLOCK_STARTUP + 0 + + + C_USE_CLOCK_SEQUENCING + 0 + + + C_CLKOUT1_SEQUENCE_NUMBER + 1 + + + C_CLKOUT2_SEQUENCE_NUMBER + 1 + + + C_CLKOUT3_SEQUENCE_NUMBER + 1 + + + C_CLKOUT4_SEQUENCE_NUMBER + 1 + + + C_CLKOUT5_SEQUENCE_NUMBER + 1 + + + C_CLKOUT6_SEQUENCE_NUMBER + 1 + + + C_CLKOUT7_SEQUENCE_NUMBER + 1 + + + C_MMCM_NOTES + None + + + C_MMCM_BANDWIDTH + OPTIMIZED + + + C_MMCM_CLKFBOUT_MULT_F + 5.000 + + + C_MMCM_CLKIN1_PERIOD + 5.000 + + + C_MMCM_CLKIN2_PERIOD + 10.0 + + + C_MMCM_CLKOUT4_CASCADE + FALSE + + + C_MMCM_CLOCK_HOLD + FALSE + + + C_MMCM_COMPENSATION + ZHOLD + + + C_MMCM_DIVCLK_DIVIDE + 1 + + + C_MMCM_REF_JITTER1 + 0.010 + + + C_MMCM_REF_JITTER2 + 0.010 + + + C_MMCM_STARTUP_WAIT + FALSE + + + C_MMCM_CLKOUT0_DIVIDE_F + 10.000 + + + C_MMCM_CLKOUT1_DIVIDE + 1 + + + C_MMCM_CLKOUT2_DIVIDE + 1 + + + C_MMCM_CLKOUT3_DIVIDE + 1 + + + C_MMCM_CLKOUT4_DIVIDE + 1 + + + C_MMCM_CLKOUT5_DIVIDE + 1 + + + C_MMCM_CLKOUT6_DIVIDE + 1 + + + C_MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKFBOUT_PHASE + 0.000 + + + C_MMCM_CLKOUT0_PHASE + 0.000 + + + C_MMCM_CLKOUT1_PHASE + 0.000 + + + C_MMCM_CLKOUT2_PHASE + 0.000 + + + C_MMCM_CLKOUT3_PHASE + 0.000 + + + C_MMCM_CLKOUT4_PHASE + 0.000 + + + C_MMCM_CLKOUT5_PHASE + 0.000 + + + C_MMCM_CLKOUT6_PHASE + 0.000 + + + C_MMCM_CLKFBOUT_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT0_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT1_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT2_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT3_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT4_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT5_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT6_USE_FINE_PS + FALSE + + + C_PLL_NOTES + No notes + + + C_PLL_BANDWIDTH + OPTIMIZED + + + C_PLL_CLK_FEEDBACK + CLKFBOUT + + + C_PLL_CLKFBOUT_MULT + 1 + + + C_PLL_CLKIN_PERIOD + 1.000 + + + C_PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + C_PLL_DIVCLK_DIVIDE + 1 + + + C_PLL_REF_JITTER + 0.010 + + + C_PLL_CLKOUT0_DIVIDE + 1 + + + C_PLL_CLKOUT1_DIVIDE + 1 + + + C_PLL_CLKOUT2_DIVIDE + 1 + + + C_PLL_CLKOUT3_DIVIDE + 1 + + + C_PLL_CLKOUT4_DIVIDE + 1 + + + C_PLL_CLKOUT5_DIVIDE + 1 + + + C_PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_PLL_CLKFBOUT_PHASE + 0.000 + + + C_PLL_CLKOUT0_PHASE + 0.000 + + + C_PLL_CLKOUT1_PHASE + 0.000 + + + C_PLL_CLKOUT2_PHASE + 0.000 + + + C_PLL_CLKOUT3_PHASE + 0.000 + + + C_PLL_CLKOUT4_PHASE + 0.000 + + + C_PLL_CLKOUT5_PHASE + 0.000 + + + C_CLOCK_MGR_TYPE + NA + + + C_OVERRIDE_MMCM + 0 + + + C_OVERRIDE_PLL + 0 + + + C_PRIMARY_PORT + clk_in1 + + + C_SECONDARY_PORT + clk_in2 + + + C_CLK_OUT1_PORT + clk_out1 + + + C_CLK_OUT2_PORT + clk_out2 + + + C_CLK_OUT3_PORT + clk_out3 + + + C_CLK_OUT4_PORT + clk_out4 + + + C_CLK_OUT5_PORT + clk_out5 + + + C_CLK_OUT6_PORT + clk_out6 + + + C_CLK_OUT7_PORT + clk_out7 + + + C_RESET_PORT + reset + + + C_LOCKED_PORT + locked + + + C_CLKFB_IN_PORT + clkfb_in + + + C_CLKFB_IN_P_PORT + clkfb_in_p + + + C_CLKFB_IN_N_PORT + clkfb_in_n + + + C_CLKFB_OUT_PORT + clkfb_out + + + C_CLKFB_OUT_P_PORT + clkfb_out_p + + + C_CLKFB_OUT_N_PORT + clkfb_out_n + + + C_POWER_DOWN_PORT + power_down + + + C_DADDR_PORT + daddr + + + C_DCLK_PORT + dclk + + + C_DRDY_PORT + drdy + + + C_DWE_PORT + dwe + + + C_DIN_PORT + din + + + C_DOUT_PORT + dout + + + C_DEN_PORT + den + + + C_PSCLK_PORT + psclk + + + C_PSEN_PORT + psen + + + C_PSINCDEC_PORT + psincdec + + + C_PSDONE_PORT + psdone + + + C_CLK_VALID_PORT + CLK_VALID + + + C_STATUS_PORT + STATUS + + + C_CLK_IN_SEL_PORT + clk_in_sel + + + C_INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + C_CLKFB_STOPPED_PORT + clkfb_stopped + + + C_CLKIN1_JITTER_PS + 50.0 + + + C_CLKIN2_JITTER_PS + 100.0 + + + C_PRIMITIVE + MMCM + + + C_SS_MODE + CENTER_HIGH + + + C_SS_MOD_PERIOD + 4000 + + + C_SS_MOD_TIME + 0.004 + + + C_HAS_CDDC + 0 + + + C_CDDCDONE_PORT + cddcdone + + + C_CDDCREQ_PORT + cddcreq + + + C_CLKOUTPHY_MODE + VCO + + + C_ENABLE_CLKOUTPHY + 0 + + + C_INTERFACE_SELECTION + 0 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 11 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_POWER_REG + 0000 + + + C_CLKOUT0_1 + 0000 + + + C_CLKOUT0_2 + 0000 + + + C_CLKOUT1_1 + 0000 + + + C_CLKOUT1_2 + 0000 + + + C_CLKOUT2_1 + 0000 + + + C_CLKOUT2_2 + 0000 + + + C_CLKOUT3_1 + 0000 + + + C_CLKOUT3_2 + 0000 + + + C_CLKOUT4_1 + 0000 + + + C_CLKOUT4_2 + 0000 + + + C_CLKOUT5_1 + 0000 + + + C_CLKOUT5_2 + 0000 + + + C_CLKOUT6_1 + 0000 + + + C_CLKOUT6_2 + 0000 + + + C_CLKFBOUT_1 + 0000 + + + C_CLKFBOUT_2 + 0000 + + + C_DIVCLK + 0000 + + + C_LOCK_1 + 0000 + + + C_LOCK_2 + 0000 + + + C_LOCK_3 + 0000 + + + C_FILTER_1 + 0000 + + + C_FILTER_2 + 0000 + + + C_DIVIDE1_AUTO + 1 + + + C_DIVIDE2_AUTO + 1.0 + + + C_DIVIDE3_AUTO + 1.0 + + + C_DIVIDE4_AUTO + 1.0 + + + C_DIVIDE5_AUTO + 1.0 + + + C_DIVIDE6_AUTO + 1.0 + + + C_DIVIDE7_AUTO + 1.0 + + + C_PLLBUFGCEDIV + false + + + C_MMCMBUFGCEDIV + false + + + C_PLLBUFGCEDIV1 + false + + + C_PLLBUFGCEDIV2 + false + + + C_PLLBUFGCEDIV3 + false + + + C_PLLBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV1 + false + + + C_MMCMBUFGCEDIV2 + false + + + C_MMCMBUFGCEDIV3 + false + + + C_MMCMBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV5 + false + + + C_MMCMBUFGCEDIV6 + false + + + C_MMCMBUFGCEDIV7 + false + + + C_CLKOUT1_MATCHED_ROUTING + false + + + C_CLKOUT2_MATCHED_ROUTING + false + + + C_CLKOUT3_MATCHED_ROUTING + false + + + C_CLKOUT4_MATCHED_ROUTING + false + + + C_CLKOUT5_MATCHED_ROUTING + false + + + C_CLKOUT6_MATCHED_ROUTING + false + + + C_CLKOUT7_MATCHED_ROUTING + false + + + C_CLKOUT0_ACTUAL_FREQ + 100.000 + + + C_CLKOUT1_ACTUAL_FREQ + 100.000 + + + C_CLKOUT2_ACTUAL_FREQ + 100.000 + + + C_CLKOUT3_ACTUAL_FREQ + 100.000 + + + C_CLKOUT4_ACTUAL_FREQ + 100.000 + + + C_CLKOUT5_ACTUAL_FREQ + 100.000 + + + C_CLKOUT6_ACTUAL_FREQ + 100.000 + + + + + + choice_list_1d3de01d + WAVEFORM + LATENCY + + + choice_list_876bfc32 + UI + PS + + + choice_list_a9bdfce0 + LOW + HIGH + OPTIMIZED + + + choice_list_ac75ef1e + Custom + + + choice_list_b9d38208 + CLKFBOUT + CLKOUT0 + + + choice_list_e099fe6c + MMCM + PLL + + + choice_pairs_035ca1c3 + SYSTEM_SYNCHRONOUS + SOURCE_SYNCHRONOUS + INTERNAL + EXTERNAL + + + choice_pairs_0920eb1b + Custom + sys_diff_clock + + + choice_pairs_11d71346 + Single_ended_clock_capable_pin + Differential_clock_capable_pin + Global_buffer + No_buffer + + + choice_pairs_15c806d5 + FDBK_AUTO + FDBK_AUTO_OFFCHIP + FDBK_ONCHIP + FDBK_OFFCHIP + + + choice_pairs_340369e0 + Custom + sys_clock + sys_diff_clock + + + choice_pairs_3c2d3ec7 + SINGLE + DIFF + + + choice_pairs_502d9f23 + ZHOLD + EXTERNAL + INTERNAL + BUF_IN + + + choice_pairs_66e4c81f + BUFG + BUFH + BUFGCE + BUFHCE + No_buffer + + + choice_pairs_77d3d587 + MMCM + PLL + BUFGCE_DIV + + + choice_pairs_8b28f1f7 + Enable_AXI + Enable_DRP + + + choice_pairs_8eea9b32 + Units_MHz + Units_ns + + + choice_pairs_a4fbc00c + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a8642b4c + No_Jitter + Min_O_Jitter + Max_I_Jitter + + + choice_pairs_c5ef7212 + Units_UI + Units_ps + + + choice_pairs_e1c87518 + REL_PRIMARY + REL_SECONDARY + + + choice_pairs_f4e10086 + CENTER_HIGH + CENTER_LOW + DOWN_HIGH + DOWN_LOW + + + choice_pairs_f669c2f5 + frequency + Time + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + clk_wiz_0.veo + verilogTemplate + + + + xilinx_anylanguagesynthesis_view_fileset + + clk_wiz_0.xdc + xdc + + processing_order + early + + + + clk_wiz_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_7s_pll.vh + verilogSource + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_mmcm.vh + verilogSource + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_pll.vh + verilogSource + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + true + clk_wiz_v6_0_1 + + + clk_wiz_0_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesynthesiswrapper_view_fileset + + clk_wiz_0.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_7s_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + clk_wiz_0_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesimulationwrapper_view_fileset + + clk_wiz_0.v + verilogSource + + + + xilinx_implementation_view_fileset + + clk_wiz_0_board.xdc + xdc + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + xilinx_versioninformation_view_fileset + + doc/clk_wiz_v6_0_changelog.txt + text + + + + xilinx_externalfiles_view_fileset + + clk_wiz_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + clk_wiz_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + clk_wiz_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + clk_wiz_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + clk_wiz_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. + + + Component_Name + clk_wiz_0 + + + USER_CLK_FREQ0 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ1 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ2 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ3 + User Frequency(MHz) + 100.0 + + + ENABLE_CLOCK_MONITOR + Enable Clock Monitoring + false + + + ENABLE_USER_CLOCK0 + User Clock + false + + + ENABLE_USER_CLOCK1 + User Clock + false + + + ENABLE_USER_CLOCK2 + User Clock + false + + + ENABLE_USER_CLOCK3 + User Clock + false + + + Enable_PLL0 + User Clock + false + + + Enable_PLL1 + User Clock + false + + + REF_CLK_FREQ + Reference Frequency(MHz) + 100.0 + + + PRECISION + Tolerance(MHz) + 1 + + + PRIMITIVE + Primitive + MMCM + + + PRIMTYPE_SEL + Primtype Sel + mmcm_adv + + + CLOCK_MGR_TYPE + Clock Mgr Type + auto + + + USE_FREQ_SYNTH + true + + + USE_SPREAD_SPECTRUM + false + + + USE_PHASE_ALIGNMENT + true + + + USE_MIN_POWER + false + + + USE_DYN_PHASE_SHIFT + false + + + USE_DYN_RECONFIG + false + + + JITTER_SEL + No_Jitter + + + PRIM_IN_FREQ + 200.000 + + + PRIM_IN_TIMEPERIOD + 10.000 + + + IN_FREQ_UNITS + Units_MHz + + + PHASESHIFT_MODE + WAVEFORM + + + IN_JITTER_UNITS + Units_UI + + + RELATIVE_INCLK + REL_PRIMARY + + + USE_INCLK_SWITCHOVER + false + + + SECONDARY_IN_FREQ + 100.000 + + + SECONDARY_IN_TIMEPERIOD + 10.000 + + + SECONDARY_PORT + clk_in2 + + + SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + JITTER_OPTIONS + UI + + + CLKIN1_UI_JITTER + 0.010 + + + CLKIN2_UI_JITTER + 0.010 + + + PRIM_IN_JITTER + 0.010 + + + SECONDARY_IN_JITTER + 0.010 + + + CLKIN1_JITTER_PS + 50.0 + + + CLKIN2_JITTER_PS + 100.0 + + + CLKOUT1_USED + true + + + CLKOUT2_USED + false + + + CLKOUT3_USED + false + + + CLKOUT4_USED + false + + + CLKOUT5_USED + false + + + CLKOUT6_USED + false + + + CLKOUT7_USED + false + + + NUM_OUT_CLKS + 1 + + + CLK_OUT1_USE_FINE_PS_GUI + false + + + CLK_OUT2_USE_FINE_PS_GUI + false + + + CLK_OUT3_USE_FINE_PS_GUI + false + + + CLK_OUT4_USE_FINE_PS_GUI + false + + + CLK_OUT5_USE_FINE_PS_GUI + false + + + CLK_OUT6_USE_FINE_PS_GUI + false + + + CLK_OUT7_USE_FINE_PS_GUI + false + + + PRIMARY_PORT + clk_in1 + + + CLK_OUT1_PORT + clk_out1 + + + CLK_OUT2_PORT + clk_out2 + + + CLK_OUT3_PORT + clk_out3 + + + CLK_OUT4_PORT + clk_out4 + + + CLK_OUT5_PORT + clk_out5 + + + CLK_OUT6_PORT + clk_out6 + + + CLK_OUT7_PORT + clk_out7 + + + DADDR_PORT + daddr + + + DCLK_PORT + dclk + + + DRDY_PORT + drdy + + + DWE_PORT + dwe + + + DIN_PORT + din + + + DOUT_PORT + dout + + + DEN_PORT + den + + + PSCLK_PORT + psclk + + + PSEN_PORT + psen + + + PSINCDEC_PORT + psincdec + + + PSDONE_PORT + psdone + + + CLKOUT1_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT1_REQUESTED_PHASE + 0.000 + + + CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT2_REQUESTED_PHASE + 0.000 + + + CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT3_REQUESTED_PHASE + 0.000 + + + CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT4_REQUESTED_PHASE + 0.000 + + + CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT5_REQUESTED_PHASE + 0.000 + + + CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT6_REQUESTED_PHASE + 0.000 + + + CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT7_REQUESTED_PHASE + 0.000 + + + CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + USE_MAX_I_JITTER + false + + + USE_MIN_O_JITTER + false + + + CLKOUT1_MATCHED_ROUTING + false + + + CLKOUT2_MATCHED_ROUTING + false + + + CLKOUT3_MATCHED_ROUTING + false + + + CLKOUT4_MATCHED_ROUTING + false + + + CLKOUT5_MATCHED_ROUTING + false + + + CLKOUT6_MATCHED_ROUTING + false + + + CLKOUT7_MATCHED_ROUTING + false + + + PRIM_SOURCE + Differential_clock_capable_pin + + + CLKOUT1_DRIVES + BUFG + + + CLKOUT2_DRIVES + BUFG + + + CLKOUT3_DRIVES + BUFG + + + CLKOUT4_DRIVES + BUFG + + + CLKOUT5_DRIVES + BUFG + + + CLKOUT6_DRIVES + BUFG + + + CLKOUT7_DRIVES + BUFG + + + FEEDBACK_SOURCE + FDBK_AUTO + + + CLKFB_IN_SIGNALING + SINGLE + + + CLKFB_IN_PORT + clkfb_in + + + CLKFB_IN_P_PORT + clkfb_in_p + + + CLKFB_IN_N_PORT + clkfb_in_n + + + CLKFB_OUT_PORT + clkfb_out + + + CLKFB_OUT_P_PORT + clkfb_out_p + + + CLKFB_OUT_N_PORT + clkfb_out_n + + + PLATFORM + UNKNOWN + + + SUMMARY_STRINGS + empty + + + USE_LOCKED + true + + + CALC_DONE + empty + + + USE_RESET + false + + + USE_POWER_DOWN + false + + + USE_STATUS + false + + + USE_FREEZE + false + + + USE_CLK_VALID + false + + + USE_INCLK_STOPPED + false + + + USE_CLKFB_STOPPED + false + + + RESET_PORT + reset + + + LOCKED_PORT + locked + + + POWER_DOWN_PORT + power_down + + + CLK_VALID_PORT + CLK_VALID + + + STATUS_PORT + STATUS + + + CLK_IN_SEL_PORT + clk_in_sel + + + INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + CLKFB_STOPPED_PORT + clkfb_stopped + + + SS_MODE + CENTER_HIGH + + + SS_MOD_FREQ + 250 + + + SS_MOD_TIME + 0.004 + + + OVERRIDE_MMCM + false + + + MMCM_NOTES + None + + + MMCM_DIVCLK_DIVIDE + 1 + + + MMCM_BANDWIDTH + OPTIMIZED + + + MMCM_CLKFBOUT_MULT_F + 5.000 + + + MMCM_CLKFBOUT_PHASE + 0.000 + + + MMCM_CLKFBOUT_USE_FINE_PS + false + + + MMCM_CLKIN1_PERIOD + 5.000 + + + MMCM_CLKIN2_PERIOD + 10.0 + + + MMCM_CLKOUT4_CASCADE + false + + + MMCM_CLOCK_HOLD + false + + + MMCM_COMPENSATION + ZHOLD + + + MMCM_REF_JITTER1 + 0.010 + + + MMCM_REF_JITTER2 + 0.010 + + + MMCM_STARTUP_WAIT + false + + + MMCM_CLKOUT0_DIVIDE_F + 10.000 + + + MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT0_PHASE + 0.000 + + + MMCM_CLKOUT0_USE_FINE_PS + false + + + MMCM_CLKOUT1_DIVIDE + 1 + + + MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT1_PHASE + 0.000 + + + MMCM_CLKOUT1_USE_FINE_PS + false + + + MMCM_CLKOUT2_DIVIDE + 1 + + + MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT2_PHASE + 0.000 + + + MMCM_CLKOUT2_USE_FINE_PS + false + + + MMCM_CLKOUT3_DIVIDE + 1 + + + MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT3_PHASE + 0.000 + + + MMCM_CLKOUT3_USE_FINE_PS + false + + + MMCM_CLKOUT4_DIVIDE + 1 + + + MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT4_PHASE + 0.000 + + + MMCM_CLKOUT4_USE_FINE_PS + false + + + MMCM_CLKOUT5_DIVIDE + 1 + + + MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT5_PHASE + 0.000 + + + MMCM_CLKOUT5_USE_FINE_PS + false + + + MMCM_CLKOUT6_DIVIDE + 1 + + + MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT6_PHASE + 0.000 + + + MMCM_CLKOUT6_USE_FINE_PS + false + + + OVERRIDE_PLL + false + + + PLL_NOTES + None + + + PLL_BANDWIDTH + OPTIMIZED + + + PLL_CLKFBOUT_MULT + 4 + + + PLL_CLKFBOUT_PHASE + 0.000 + + + PLL_CLK_FEEDBACK + CLKFBOUT + + + PLL_DIVCLK_DIVIDE + 1 + + + PLL_CLKIN_PERIOD + 10.000 + + + PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + PLL_REF_JITTER + 0.010 + + + PLL_CLKOUT0_DIVIDE + 1 + + + PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT0_PHASE + 0.000 + + + PLL_CLKOUT1_DIVIDE + 1 + + + PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT1_PHASE + 0.000 + + + PLL_CLKOUT2_DIVIDE + 1 + + + PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT2_PHASE + 0.000 + + + PLL_CLKOUT3_DIVIDE + 1 + + + PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT3_PHASE + 0.000 + + + PLL_CLKOUT4_DIVIDE + 1 + + + PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT4_PHASE + 0.000 + + + PLL_CLKOUT5_DIVIDE + 1 + + + PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT5_PHASE + 0.000 + + + RESET_TYPE + Reset Type + ACTIVE_HIGH + + + USE_SAFE_CLOCK_STARTUP + false + + + USE_CLOCK_SEQUENCING + false + + + CLKOUT1_SEQUENCE_NUMBER + 1 + + + CLKOUT2_SEQUENCE_NUMBER + 1 + + + CLKOUT3_SEQUENCE_NUMBER + 1 + + + CLKOUT4_SEQUENCE_NUMBER + 1 + + + CLKOUT5_SEQUENCE_NUMBER + 1 + + + CLKOUT6_SEQUENCE_NUMBER + 1 + + + CLKOUT7_SEQUENCE_NUMBER + 1 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_IN1_BOARD_INTERFACE + Custom + + + CLK_IN2_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN1_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN2_BOARD_INTERFACE + Custom + + + AUTO_PRIMITIVE + MMCM + + + RESET_BOARD_INTERFACE + Custom + + + ENABLE_CDDC + false + + + CDDCDONE_PORT + cddcdone + + + CDDCREQ_PORT + cddcreq + + + ENABLE_CLKOUTPHY + false + + + CLKOUTPHY_REQUESTED_FREQ + 600.000 + + + CLKOUT1_JITTER + Clkout1 Jitter + 112.316 + + + CLKOUT1_PHASE_ERROR + Clkout1 Phase + 89.971 + + + CLKOUT2_JITTER + Clkout2 Jitter + 0.0 + + + CLKOUT2_PHASE_ERROR + Clkout2 Phase + 0.0 + + + CLKOUT3_JITTER + Clkout3 Jitter + 0.0 + + + CLKOUT3_PHASE_ERROR + Clkout3 Phase + 0.0 + + + CLKOUT4_JITTER + Clkout4 Jitter + 0.0 + + + CLKOUT4_PHASE_ERROR + Clkout4 Phase + 0.0 + + + CLKOUT5_JITTER + Clkout5 Jitter + 0.0 + + + CLKOUT5_PHASE_ERROR + Clkout5 Phase + 0.0 + + + CLKOUT6_JITTER + Clkout6 Jitter + 0.0 + + + CLKOUT6_PHASE_ERROR + Clkout6 Phase + 0.0 + + + CLKOUT7_JITTER + Clkout7 Jitter + 0.0 + + + CLKOUT7_PHASE_ERROR + Clkout7 Phase + 0.0 + + + INPUT_MODE + frequency + + + INTERFACE_SELECTION + Enable_AXI + + + AXI_DRP + Write DRP registers + false + + + PHASE_DUTY_CONFIG + Phase Duty Cycle Config + false + + + + + Clocking Wizard + + XPM_CDC + + 1 + + + + + + + + + + + + + + + 2018.2 + + + + + + + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc new file mode 100644 index 0000000..3422a8e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc @@ -0,0 +1,2 @@ +#--------------------Physical Constraints----------------- + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v new file mode 100644 index 0000000..958893e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v @@ -0,0 +1,203 @@ + +// file: clk_wiz_0.v +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1___100.000______0.000______50.0______112.316_____89.971 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________200.000____________0.010 + +`timescale 1ps/1ps + +module clk_wiz_0_clk_wiz + + (// Clock in ports + // Clock out ports + output clk_out1, + // Status and control signals + output locked, + input clk_in1_p, + input clk_in1_n + ); + // Input buffering + //------------------------------------ +wire clk_in1_clk_wiz_0; +wire clk_in2_clk_wiz_0; + IBUFDS clkin1_ibufgds + (.O (clk_in1_clk_wiz_0), + .I (clk_in1_p), + .IB (clk_in1_n)); + + + + + // Clocking PRIMITIVE + //------------------------------------ + + // Instantiation of the MMCM PRIMITIVE + // * Unused inputs are tied off + // * Unused outputs are labeled unused + + wire clk_out1_clk_wiz_0; + wire clk_out2_clk_wiz_0; + wire clk_out3_clk_wiz_0; + wire clk_out4_clk_wiz_0; + wire clk_out5_clk_wiz_0; + wire clk_out6_clk_wiz_0; + wire clk_out7_clk_wiz_0; + + wire [15:0] do_unused; + wire drdy_unused; + wire psdone_unused; + wire locked_int; + wire clkfbout_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfboutb_unused; + wire clkout0b_unused; + wire clkout1_unused; + wire clkout1b_unused; + wire clkout2_unused; + wire clkout2b_unused; + wire clkout3_unused; + wire clkout3b_unused; + wire clkout4_unused; + wire clkout5_unused; + wire clkout6_unused; + wire clkfbstopped_unused; + wire clkinstopped_unused; + + MMCME2_ADV + #(.BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (5.000), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (10.000), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (5.000)) + mmcm_adv_inst + // Output clocks + ( + .CLKFBOUT (clkfbout_clk_wiz_0), + .CLKFBOUTB (clkfboutb_unused), + .CLKOUT0 (clk_out1_clk_wiz_0), + .CLKOUT0B (clkout0b_unused), + .CLKOUT1 (clkout1_unused), + .CLKOUT1B (clkout1b_unused), + .CLKOUT2 (clkout2_unused), + .CLKOUT2B (clkout2b_unused), + .CLKOUT3 (clkout3_unused), + .CLKOUT3B (clkout3b_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + .CLKOUT6 (clkout6_unused), + // Input clock control + .CLKFBIN (clkfbout_buf_clk_wiz_0), + .CLKIN1 (clk_in1_clk_wiz_0), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (do_unused), + .DRDY (drdy_unused), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (psdone_unused), + // Other control and status signals + .LOCKED (locked_int), + .CLKINSTOPPED (clkinstopped_unused), + .CLKFBSTOPPED (clkfbstopped_unused), + .PWRDWN (1'b0), + .RST (1'b0)); + + assign locked = locked_int; +// Clock Monitor clock assigning +//-------------------------------------- + // Output buffering + //----------------------------------- + + BUFG clkf_buf + (.O (clkfbout_buf_clk_wiz_0), + .I (clkfbout_clk_wiz_0)); + + + + + + + BUFG clkout1_buf + (.O (clk_out1), + .I (clk_out1_clk_wiz_0)); + + + + +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc new file mode 100644 index 0000000..ab1ed7a --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc @@ -0,0 +1,59 @@ + +# file: clk_wiz_0_ooc.xdc +# +# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +################# +#DEFAULT CLOCK CONSTRAINTS + +############################################################ +# Clock Period Constraints # +############################################################ +# Differential clock only needs one constraint +#create_clock -period 5.000 [get_ports clk_in1_p] + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v new file mode 100644 index 0000000..5dcca9f --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v @@ -0,0 +1,246 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 17:10:06 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim +// d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +// Design : clk_wiz_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module clk_wiz_0 + (clk_out1, + locked, + clk_in1_p, + clk_in1_n); + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; + + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_n; + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_p; + wire clk_out1; + wire locked; + + clk_wiz_0_clk_wiz_0_clk_wiz inst + (.clk_in1_n(clk_in1_n), + .clk_in1_p(clk_in1_p), + .clk_out1(clk_out1), + .locked(locked)); +endmodule + +(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *) +module clk_wiz_0_clk_wiz_0_clk_wiz + (clk_out1, + locked, + clk_in1_p, + clk_in1_n); + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; + + wire clk_in1_clk_wiz_0; + wire clk_in1_n; + wire clk_in1_p; + wire clk_out1; + wire clk_out1_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfbout_clk_wiz_0; + wire locked; + wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; + wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; + wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; + wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_clk_wiz_0), + .O(clkfbout_buf_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUFDS #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufgds + (.I(clk_in1_p), + .IB(clk_in1_n), + .O(clk_in1_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(clk_out1_clk_wiz_0), + .O(clk_out1)); + (* BOX_TYPE = "PRIMITIVE" *) + MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(5.000000), + .CLKFBOUT_PHASE(0.000000), + .CLKFBOUT_USE_FINE_PS("FALSE"), + .CLKIN1_PERIOD(5.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE_F(10.000000), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT0_USE_FINE_PS("FALSE"), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT1_USE_FINE_PS("FALSE"), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT2_USE_FINE_PS("FALSE"), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT3_USE_FINE_PS("FALSE"), + .CLKOUT4_CASCADE("FALSE"), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT4_USE_FINE_PS("FALSE"), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .CLKOUT5_USE_FINE_PS("FALSE"), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.500000), + .CLKOUT6_PHASE(0.000000), + .CLKOUT6_USE_FINE_PS("FALSE"), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(1), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PSEN_INVERTED(1'b0), + .IS_PSINCDEC_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .SS_EN("FALSE"), + .SS_MODE("CENTER_HIGH"), + .SS_MOD_PERIOD(10000), + .STARTUP_WAIT("FALSE")) + mmcm_adv_inst + (.CLKFBIN(clkfbout_buf_clk_wiz_0), + .CLKFBOUT(clkfbout_clk_wiz_0), + .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), + .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), + .CLKIN1(clk_in1_clk_wiz_0), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), + .CLKOUT0(clk_out1_clk_wiz_0), + .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), + .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), + .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), + .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), + .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), + .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(locked), + .PSCLK(1'b0), + .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(1'b0), + .RST(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl new file mode 100644 index 0000000..062d0fe --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl @@ -0,0 +1,191 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 17:10:06 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim +-- d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +-- Design : clk_wiz_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_wiz_0_clk_wiz_0_clk_wiz is + port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz"; +end clk_wiz_0_clk_wiz_0_clk_wiz; + +architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is + signal clk_in1_clk_wiz_0 : STD_LOGIC; + signal clk_out1_clk_wiz_0 : STD_LOGIC; + signal clkfbout_buf_clk_wiz_0 : STD_LOGIC; + signal clkfbout_clk_wiz_0 : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkin1_ibufgds : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of clkin1_ibufgds : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of clkin1_ibufgds : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of clkin1_ibufgds : label is "AUTO"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_clk_wiz_0, + O => clkfbout_buf_clk_wiz_0 + ); +clkin1_ibufgds: unisim.vcomponents.IBUFDS + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => clk_in1_p, + IB => clk_in1_n, + O => clk_in1_clk_wiz_0 + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => clk_out1_clk_wiz_0, + O => clk_out1 + ); +mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 5.000000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 5.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 10.000000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_DIVIDE => 1, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => clkfbout_buf_clk_wiz_0, + CLKFBOUT => clkfbout_clk_wiz_0, + CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, + CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, + CLKIN1 => clk_in1_clk_wiz_0, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, + CLKOUT0 => clk_out1_clk_wiz_0, + CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, + CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, + CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, + CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, + CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, + CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, + CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => locked, + PSCLK => '0', + PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_wiz_0 is + port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of clk_wiz_0 : entity is true; +end clk_wiz_0; + +architecture STRUCTURE of clk_wiz_0 is +begin +inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz + port map ( + clk_in1_n => clk_in1_n, + clk_in1_p => clk_in1_p, + clk_out1 => clk_out1, + locked => locked + ); +end STRUCTURE; diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100644 index 0000000..9c1015a --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 17:10:06 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub +// d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module clk_wiz_0(clk_out1, locked, clk_in1_p, clk_in1_n) +/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1_p,clk_in1_n" */; + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; +endmodule diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..d31e7c5 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 17:10:06 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub +-- d:/Xilinx/xjtag/xjtag_ip/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + +end clk_wiz_0; + +architecture stub of clk_wiz_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1_p,clk_in1_n"; +begin +end; diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt new file mode 100644 index 0000000..2ce117e --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt @@ -0,0 +1,180 @@ +2018.2: + * Version 6.0 (Rev. 1) + * Bug Fix: Removed vco freq check when Primitive is None + * Other: New family support added + +2018.1: + * Version 6.0 + * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature + * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI + * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals. + * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support + * Other: DRCs added for invalid input values in Override mode + +2017.4: + * Version 5.4 (Rev. 3) + * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL + * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4 + +2017.3: + * Version 5.4 (Rev. 2) + * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices + +2017.2: + * Version 5.4 (Rev. 1) + * General: Internal GUI changes. No effect on the customer design. + +2017.1: + * Version 5.4 + * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices. + * Other: Added support for new zynq ultrascale plus devices. + +2016.4: + * Version 5.3 (Rev. 3) + * Bug Fix: Internal GUI issues are fixed. + +2016.3: + * Version 5.3 (Rev. 2) + * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs. + * Feature Enhancement: Added Matched Routing Option for better timing solutions. + * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list. + * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user + * Other: Added support for Spartan7 devices. + +2016.2: + * Version 5.3 (Rev. 1) + * Internal register bit update, no effect on customer designs. + +2016.1: + * Version 5.3 + * Added Clock Monitor Feature as part of clocking wizard + * DRP registers can be directly written through AXI without resource utilization + * Changes to HDL library management to support Vivado IP simulation library + +2015.4.2: + * Version 5.2 (Rev. 1) + * No changes + +2015.4.1: + * Version 5.2 (Rev. 1) + * No changes + +2015.4: + * Version 5.2 (Rev. 1) + * Internal device family change, no functional changes + +2015.3: + * Version 5.2 + * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances + * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported + * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature + * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format + * Example design and simulation files are delivered in verilog only + +2015.2.1: + * Version 5.1 (Rev. 6) + * No changes + +2015.2: + * Version 5.1 (Rev. 6) + * No changes + +2015.1: + * Version 5.1 (Rev. 6) + * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices + * Supported devices and production status are now determined automatically, to simplify support for future devices + +2014.4.1: + * Version 5.1 (Rev. 5) + * No changes + +2014.4: + * Version 5.1 (Rev. 5) + * Internal device family change, no functional changes + * updates related to the source selection based on board interface for zed board + +2014.3: + * Version 5.1 (Rev. 4) + * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface + +2014.2: + * Version 5.1 (Rev. 3) + * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 + +2014.1: + * Version 5.1 (Rev. 2) + * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock + * Internal device family name change, no functional changes + +2013.4: + * Version 5.1 (Rev. 1) + * Added support for Ultrascale devices + * Updated Board Flow GUI to select the clock interfaces + * Fixed issue with Stub file parameter error for BUFR output driver + +2013.3: + * Version 5.1 + * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL + * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies + * Fixed precision issues between displayed and actual frequencies + * Added tool tips to GUI + * Added Jitter and Phase error values to IP properties + * Added support for Cadence IES and Synopsys VCS simulators + * Reduced warnings in synthesis and simulation + * Enhanced support for IP Integrator + +2013.2: + * Version 5.0 (Rev. 1) + * Fixed issue with clock constraints for multiple instances of clocking wizard + * Updated Life-Cycle status of devices + +2013.1: + * Version 5.0 + * Lower case ports for Verilog + * Added Safe Clock Startup and Clock Sequencing + +(c) Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh new file mode 100644 index 0000000..b233fde --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh @@ -0,0 +1,665 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: 7 Series || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1011_00, + 10'b0010_1101_00, + 10'b0010_0011_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0100_1111_00, + 10'b0101_1011_00, + 10'b0111_0111_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_1001_00, + 10'b1101_0001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0111_0001_00, + 10'b0111_0001_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0110_0001_00, + 10'b0110_0001_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0100_1010_00, + 10'b0011_1100_00, + 10'b0011_1100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh new file mode 100644 index 0000000..53ab5ad --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh @@ -0,0 +1,527 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: PLLE2 DRP +// Module Name: plle2_drp_func.h +// Version: 2.00 +// Target Devices: 7 Series || PLL +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// Updated for CR663854. +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + +`ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); +`endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end +`ifdef DEBUG + $display("round_frac: %h", round_frac); +`endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + +`ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); +`endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + +`ifdef DEBUG + $display("temp: %h", temp); +`endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1101_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0011_0111_00, + 10'b0011_0111_00, + 10'b0101_1111_00, + 10'b0111_1111_00, + 10'b0111_1011_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_1101_00, + 10'b1111_0111_00, + 10'b1111_1011_00, + 10'b1111_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); +`endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh new file mode 100644 index 0000000..99b88ca --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh @@ -0,0 +1,665 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: UltraScale Architecture || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_0011_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_1001_11, + 10'b0010_1001_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1011_11, + 10'b0011_1111_11, + 10'b0100_1111_11, + 10'b0100_1111_11, + 10'b0101_1111_11, + 10'b0110_1111_11, + 10'b0111_1111_11, + 10'b0111_1111_11, + 10'b1100_1111_11, + 10'b1101_1111_11, + 10'b1110_1111_11, + 10'b1111_1111_11, + 10'b1111_1111_11, + 10'b1110_0111_11, + 10'b1110_1011_11, + 10'b1111_0111_11, + 10'b1111_1011_11, + 10'b1111_1011_11, + 10'b1110_1101_11, + 10'b1111_1101_11, + 10'b1111_1101_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh new file mode 100644 index 0000000..d12a6f7 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh @@ -0,0 +1,524 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 6/15/2015 +// Design Name: PLLE3 DRP +// Module Name: plle3_drp_func.h +// Version: 1.10 +// Target Devices: UltraScale Architecture +// Tool versions: 2015.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// PM_Rise bits have been removed for PLLE3 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [759:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001 //19 + + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 19 + ); + + reg [639:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0010_1111_01, //1 + 10'b0010_0011_11, //2 + 10'b0011_0011_11, //3 + 10'b0010_0001_11, //4 + 10'b0010_0110_11, //5 + 10'b0010_1010_11, //6 + 10'b0010_1010_11, //7 + 10'b0011_0110_11, //8 + 10'b0010_1100_11, //9 + 10'b0010_1100_11, //10 + 10'b0010_1100_11, //11 + 10'b0010_0010_11, //12 + 10'b0011_1100_11, //13 + 10'b0011_1100_11, //14 + 10'b0011_1100_11, //15 + 10'b0011_1100_11, //16 + 10'b0011_0010_11, //17 + 10'b0011_0010_11, //18 + 10'b0011_0010_11 //19 + }; + + mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits +// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh new file mode 100644 index 0000000..60b4560 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh @@ -0,0 +1,855 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa. Updated by Ralf Krueger +// Date: 7/30/2014 +// Design Name: MMCME4 DRP +// Module Name: mmcme4_drp_func.h +// Version: 1.31 +// Target Devices: UltraScale Plus Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for UltraScal+ MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function +// 2/28/17 - Updated for Ultrascale Plus +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages during elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_phase-divide:%d,phase:%d", divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [7:0] divide // Max M divide is 128 in UltrascalePlus + ); + + reg [5119:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) + 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 + 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 + 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 + 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 + 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 + 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 + 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup_low; + reg [1279:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0011_1111_11, // M=1 - not legal + 10'b0011_1111_11, // M=2 + 10'b0011_1101_11, // M=3 + 10'b0011_0101_11, // M=4 + 10'b0011_1001_11, // M=5 + 10'b0011_1110_11, // M=6 + 10'b0011_1110_11, // M=7 + 10'b0011_0001_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0100_0110_11, + 10'b0011_1100_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, // M=127 + 10'b1101_1000_11 // M=128 +}; + + lookup_high = { + // CP_RES_LFHF + 10'b0111_1111_11, // M=1 - not legal + 10'b0111_1111_11, // M=2 + 10'b1110_1111_11, // M=3 + 10'b1111_1111_11, // M=4 + 10'b1111_1011_11, // M=5 + 10'b1111_1101_11, // M=6 + 10'b1111_0011_11, // M=7 + 10'b1110_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1110_0110_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11 // M=128 +}; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh new file mode 100644 index 0000000..9bfa6c8 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh @@ -0,0 +1,530 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ +// Date: 6/15/2015 +// Design Name: PLLE4 DRP +// Module Name: plle4_drp_func.h +// Version: 2.0 +// Target Devices: UltraScale+ Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// M_Rise bits have been removed for PLLE3 +// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for +// Ultrascale+ and for max M of 21 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [839:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+ + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001, //19 + 40'b11111_11111_0111110100_1111101001_0000000001, //20 + 40'b11111_11111_0111011011_1111101001_0000000001 //21 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [209:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0011_0111_11, //1 not legal in Ultrascale+ + 10'b0011_0111_11, //2 + 10'b0011_0011_11, //3 + 10'b0011_1001_11, //4 + 10'b0011_0001_11, //5 + 10'b0100_1110_11, //6 + 10'b0011_0110_11, //7 + 10'b0011_1010_11, //8 + 10'b0111_1001_11, //9 + 10'b0111_1001_11, //10 + 10'b0101_0110_11, //11 + 10'b1100_0101_11, //12 + 10'b0101_1010_11, //13 + 10'b0110_0110_11, //14 + 10'b0110_1010_11, //15 + 10'b0111_0110_11, //16 + 10'b1111_0101_11, //17 + 10'b1100_0110_11, //18 + 10'b1110_0001_11, //19 + 10'b1101_0110_11, //20 + 10'b1111_0001_11 //21 + }; + + mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" +// will need to divide the doubled clock VCO clock frequency by +// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will +// need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/axi_bus_demo/prj/axi_bus_demo.xpr b/axi_bus_demo/prj/axi_bus_demo.xpr new file mode 100644 index 0000000..18f1236 --- /dev/null +++ b/axi_bus_demo/prj/axi_bus_demo.xpr @@ -0,0 +1,202 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/axi_bus_demo/prj/ip_upgrade.log b/axi_bus_demo/prj/ip_upgrade.log new file mode 100644 index 0000000..8c4e11b --- /dev/null +++ b/axi_bus_demo/prj/ip_upgrade.log @@ -0,0 +1,163 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 17:32:52 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7k160tffg676-2 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'design_1_xjtag_axi_0_0' + +1. Summary +---------- + +SUCCESS in the conversion of design_1_xjtag_axi_0_0 (xilinx.com:user:xjtag_axi:1.0 (Rev. 2)) to Vivado generation flows. + + + + + + +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 09:40:23 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7k160tffg676-2 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'design_1_xjtag_axi_0_0' + +1. Summary +---------- + +SUCCESS in the conversion of design_1_xjtag_axi_0_0 (xilinx.com:user:xjtag_axi:1.0 (Rev. 2)) to Vivado generation flows. + + + + + + +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 09:33:56 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7k160tffg676-2 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'design_1_xjtag_axi_0_0' + +1. Summary +---------- + +SUCCESS in the conversion of design_1_xjtag_axi_0_0 (xilinx.com:user:xjtag_axi:1.0 (Rev. 2)) to Vivado generation flows. + + + + + + +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 09:30:37 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7k160tffg676-2 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'design_1_xjtag_axi_0_0' + +1. Summary +---------- + +SUCCESS in the conversion of design_1_xjtag_axi_0_0 (xilinx.com:user:xjtag_axi:1.0 (Rev. 2)) to Vivado generation flows. + + + + + + +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 09:00:21 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7k160tffg676-2 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'design_1_xjtag_axi_0_0' + +1. Summary +---------- + +SUCCESS in the conversion of design_1_xjtag_axi_0_0 (xilinx.com:user:xjtag_axi:1.0 (Rev. 2)) to Vivado generation flows. + + + + + + +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Tue Jun 30 08:59:24 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7k160tffg676-2 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'design_1_xjtag_axi_0_0' + +1. Summary +---------- + +SUCCESS in the conversion of design_1_xjtag_axi_0_0 (xilinx.com:user:xjtag_axi:1.0 (Rev. 2)) to Vivado generation flows. + + + + + + +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Mon Jun 29 12:25:05 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7k160tffg676-2 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'design_1_xjtag_axi_0_0' + +1. Summary +---------- + +SUCCESS in the conversion of design_1_xjtag_axi_0_0 (xilinx.com:user:xjtag_axi:1.0 (Rev. 2)) to Vivado generation flows. + + + + + + +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Mon Jun 29 11:45:41 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : upgrade_ip +| Device : xc7k160tffg676-2 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'design_1_xjtag_axi_0_0' + +1. Summary +---------- + +SUCCESS in the conversion of design_1_xjtag_axi_0_0 (xilinx.com:user:xjtag_axi:1.0 (Rev. 2)) to Vivado generation flows. + diff --git a/axi_bus_demo/src/t160_top.v b/axi_bus_demo/src/t160_top.v new file mode 100644 index 0000000..1e599eb --- /dev/null +++ b/axi_bus_demo/src/t160_top.v @@ -0,0 +1,42 @@ +module t160_top +( + +input sys_clkp, +input sys_clkn, + +output [3:0] led + +); + + +wire locked; +wire iclk; //100-200MHz +wire rstn; +wire [31:0] Test_data; + +assign led =Test_data[3:0]; + + +clk_wiz_0 clk_uut +( +.clk_out1(iclk), +.locked(locked), +.clk_in1_p(sys_clkp), // input clk_in1_p +.clk_in1_n(sys_clkn)); // input clk_in1_n + +BUFG BUFG_inst ( + .O(rstn), // 1-bit output: Clock output + .I(locked) // 1-bit input: Clock input +); + +design_1_wrapper uut +( +.clk (iclk), +.gpio_in (32'h12345678), +.gpio_out (Test_data), +.rstn (rstn) +); + + + +endmodule \ No newline at end of file diff --git a/axi_bus_demo/src/t160_top.xdc b/axi_bus_demo/src/t160_top.xdc new file mode 100644 index 0000000..4769e37 --- /dev/null +++ b/axi_bus_demo/src/t160_top.xdc @@ -0,0 +1,16 @@ +set_property PACKAGE_PIN T20 [get_ports {led[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] + +set_property PACKAGE_PIN R20 [get_ports {led[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] + +set_property PACKAGE_PIN T22 [get_ports {led[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] + +set_property PACKAGE_PIN T23 [get_ports {led[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] + +set_property PACKAGE_PIN AA10 [get_ports sys_clkp] +set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clkp] + + diff --git a/axi_bus_ip/component.xml b/axi_bus_ip/component.xml new file mode 100644 index 0000000..48ed1cf --- /dev/null +++ b/axi_bus_ip/component.xml @@ -0,0 +1,711 @@ + + + xilinx.com + user + xjtag_axi + 1.0 + + + m00_axi + + + + + + + + + AWADDR + + + m00_axi_awaddr + + + + + AWPROT + + + m00_axi_awprot + + + + + AWVALID + + + m00_axi_awvalid + + + + + AWREADY + + + m00_axi_awready + + + + + WDATA + + + m00_axi_wdata + + + + + WSTRB + + + m00_axi_wstrb + + + + + WVALID + + + m00_axi_wvalid + + + + + WREADY + + + m00_axi_wready + + + + + BRESP + + + m00_axi_bresp + + + + + BVALID + + + m00_axi_bvalid + + + + + BREADY + + + m00_axi_bready + + + + + ARADDR + + + m00_axi_araddr + + + + + ARPROT + + + m00_axi_arprot + + + + + ARVALID + + + m00_axi_arvalid + + + + + ARREADY + + + m00_axi_arready + + + + + RDATA + + + m00_axi_rdata + + + + + RRESP + + + m00_axi_rresp + + + + + RVALID + + + m00_axi_rvalid + + + + + RREADY + + + m00_axi_rready + + + + + + m00_axi_aresetn + + + + + + + RST + + + m00_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m00_axi_aclk + + + + + + + CLK + + + m00_axi_aclk + + + + + + ASSOCIATED_BUSIF + m00_axi + + + ASSOCIATED_RESET + m00_axi_aresetn + + + + + + + m00_axi + 4294967296 + 32 + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + xjtag_axi + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 7e385292 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + xjtag_axi + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + acc3d578 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 5d90ea70 + + + + + + + m00_axi_aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awaddr + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awprot + + out + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_awready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_wdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_wstrb + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_wvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_wready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_bresp + + in + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_bvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_bready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_araddr + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_arprot + + out + + 2 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_arvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axi_arready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_rdata + + in + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_rresp + + in + + 1 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_rvalid + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m00_axi_rready + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + JTAG_SEL + Jtag Sel + 3 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_dd9ee503 + 0 + 1 + 2 + 3 + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/xjtag_axi.ngc + ngc + + + src/xjtag_axi.v + verilogSource + CHECKSUM_acc3d578 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/xjtag_axi.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/xjtag_axi_v1_0.tcl + tclSource + CHECKSUM_5d90ea70 + XGUI_VERSION_2 + + + + xjtag_axi_v1_0 + + + JTAG_SEL + Jtag Sel + 3 + + + Component_Name + xjtag_axi_v1_0 + + + + + + kintex7 + artix7 + artix7l + qartix7 + qkintex7 + qkintex7l + qzynq + kintex7l + aartix7 + azynq + zynq + + + /UserIP + + xjtag_axi_v1_0 + package_project + 2 + 2020-06-30T09:31:07Z + + + d:/Xilinx/xjtag/xjtag_ise_axi/xjtag_axi + + + + 2018.2 + + + + + + + + + diff --git a/axi_bus_ip/src/xjtag_axi.ngc b/axi_bus_ip/src/xjtag_axi.ngc new file mode 100644 index 0000000..16be3c0 --- /dev/null +++ b/axi_bus_ip/src/xjtag_axi.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/axi_bus_ip/src/xjtag_axi.v b/axi_bus_ip/src/xjtag_axi.v new file mode 100644 index 0000000..2a4ec61 --- /dev/null +++ b/axi_bus_ip/src/xjtag_axi.v @@ -0,0 +1,39 @@ + +`timescale 1 ns / 1 ps + + module xjtag_axi # + ( + parameter JTAG_SEL =3 + + ) + ( + // Users to add ports here + // Ports of Axi Master Bus Interface M00_AXI + //input wire m00_axi_init_axi_txn, + //output wire m00_axi_error, + //output wire m00_axi_txn_done, + input wire m00_axi_aclk, + input wire m00_axi_aresetn, + output wire [31 : 0] m00_axi_awaddr, + output wire [2 : 0] m00_axi_awprot, + output wire m00_axi_awvalid, + input wire m00_axi_awready, + output wire [31 : 0] m00_axi_wdata, + output wire [3 : 0] m00_axi_wstrb, + output wire m00_axi_wvalid, + input wire m00_axi_wready, + input wire [1 : 0] m00_axi_bresp, + input wire m00_axi_bvalid, + output wire m00_axi_bready, + output wire [31 : 0] m00_axi_araddr, + output wire [2 : 0] m00_axi_arprot, + output wire m00_axi_arvalid, + input wire m00_axi_arready, + input wire [31 : 0] m00_axi_rdata, + input wire [1 : 0] m00_axi_rresp, + input wire m00_axi_rvalid, + output wire m00_axi_rready + ); + + + endmodule diff --git a/axi_bus_ip/xgui/xjtag_axi_v1_0.tcl b/axi_bus_ip/xgui/xjtag_axi_v1_0.tcl new file mode 100644 index 0000000..aa9d06d --- /dev/null +++ b/axi_bus_ip/xgui/xjtag_axi_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "JTAG_SEL" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.JTAG_SEL { PARAM_VALUE.JTAG_SEL } { + # Procedure called to update JTAG_SEL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.JTAG_SEL { PARAM_VALUE.JTAG_SEL } { + # Procedure called to validate JTAG_SEL + return true +} + + +proc update_MODELPARAM_VALUE.JTAG_SEL { MODELPARAM_VALUE.JTAG_SEL PARAM_VALUE.JTAG_SEL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.JTAG_SEL}] ${MODELPARAM_VALUE.JTAG_SEL} +} + diff --git a/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7.logs/runme.log b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7.logs/runme.log new file mode 100644 index 0000000..3c288cb --- /dev/null +++ b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7.logs/runme.log @@ -0,0 +1,327 @@ + +*** Running vivado + with args -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source clk_wiz_0.tcl -notrace +Command: synth_design -top clk_wiz_0 -part xc7k160tffg676-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 6400 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 394.297 ; gain = 93.051 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] + Parameter CAPACITANCE bound to: DONT_CARE - type: string + Parameter DIFF_TERM bound to: FALSE - type: string + Parameter DQS_BIAS bound to: FALSE - type: string + Parameter IBUF_DELAY_VALUE bound to: 0 - type: string + Parameter IBUF_LOW_PWR bound to: TRUE - type: string + Parameter IFD_DELAY_VALUE bound to: AUTO - type: string + Parameter IOSTANDARD bound to: DEFAULT - type: string +INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (1#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: float + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float + Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float + Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string + Parameter COMPENSATION bound to: ZHOLD - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 + Parameter IS_PSEN_INVERTED bound to: 1'b0 + Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 + Parameter IS_PWRDWN_INVERTED bound to: 1'b0 + Parameter IS_RST_INVERTED bound to: 1'b0 + Parameter REF_JITTER1 bound to: 0.010000 - type: float + Parameter REF_JITTER2 bound to: 0.010000 - type: float + Parameter SS_EN bound to: FALSE - type: string + Parameter SS_MODE bound to: CENTER_HIGH - type: string + Parameter SS_MOD_PERIOD bound to: 10000 - type: integer + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (2#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (3#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (5#1) [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.582 ; gain = 143.336 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.582 ; gain = 143.336 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.582 ; gain = 143.336 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 714.941 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 780.641 ; gain = 479.395 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 780.641 ; gain = 479.395 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 780.641 ; gain = 479.395 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |BUFG | 2| +|2 |MMCME2_ADV | 1| +|3 |IBUFDS | 1| ++------+-----------+------+ + +Report Instance Areas: ++------+---------+------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------+------+ +|1 |top | | 4| +|2 | inst |clk_wiz_0_clk_wiz | 4| ++------+---------+------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 782.258 ; gain = 210.652 +Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.262 ; gain = 481.012 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 804.223 ; gain = 514.445 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. diff --git a/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/2fd8150145e5e4c7.xci b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/2fd8150145e5e4c7.xci new file mode 100644 index 0000000..586ffc2 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/2fd8150145e5e4c7.xci @@ -0,0 +1,294 @@ + + + xilinx.com + ipcache + 2fd8150145e5e4c7 + 0 + + + clk_wiz_0 + + + 100000000 + 100000000 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 130.958 + false + 98.575 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_0 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 10.000 + 0.000 + false + 10.000 + 10.000 + 10.000 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 1 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 100.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + false + false + false + false + kintex7 + + xc7k160t + ffg676 + VERILOG + + MIXED + -2 + + TRUE + TRUE + 2e0224e4 + 2fd8150145e5e4c7 + fa99e727 + IP_Unknown + 1 + TRUE + . + + . + 2018.2 + GLOBAL + + + + diff --git a/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0.dcp b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0.dcp new file mode 100644 index 0000000..a07124b Binary files /dev/null and b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0.dcp differ diff --git a/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_sim_netlist.v b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_sim_netlist.v new file mode 100644 index 0000000..c31c0a1 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_sim_netlist.v @@ -0,0 +1,245 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 12:07:41 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v +// Design : clk_wiz_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (clk_out1, + locked, + clk_in1_p, + clk_in1_n); + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; + + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_n; + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_p; + wire clk_out1; + wire locked; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz inst + (.clk_in1_n(clk_in1_n), + .clk_in1_p(clk_in1_p), + .clk_out1(clk_out1), + .locked(locked)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz + (clk_out1, + locked, + clk_in1_p, + clk_in1_n); + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; + + wire clk_in1_clk_wiz_0; + wire clk_in1_n; + wire clk_in1_p; + wire clk_out1; + wire clk_out1_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfbout_clk_wiz_0; + wire locked; + wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; + wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; + wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; + wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_clk_wiz_0), + .O(clkfbout_buf_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUFDS #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufgds + (.I(clk_in1_p), + .IB(clk_in1_n), + .O(clk_in1_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(clk_out1_clk_wiz_0), + .O(clk_out1)); + (* BOX_TYPE = "PRIMITIVE" *) + MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(10.000000), + .CLKFBOUT_PHASE(0.000000), + .CLKFBOUT_USE_FINE_PS("FALSE"), + .CLKIN1_PERIOD(10.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE_F(10.000000), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT0_USE_FINE_PS("FALSE"), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT1_USE_FINE_PS("FALSE"), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT2_USE_FINE_PS("FALSE"), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT3_USE_FINE_PS("FALSE"), + .CLKOUT4_CASCADE("FALSE"), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT4_USE_FINE_PS("FALSE"), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .CLKOUT5_USE_FINE_PS("FALSE"), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.500000), + .CLKOUT6_PHASE(0.000000), + .CLKOUT6_USE_FINE_PS("FALSE"), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(1), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PSEN_INVERTED(1'b0), + .IS_PSINCDEC_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .SS_EN("FALSE"), + .SS_MODE("CENTER_HIGH"), + .SS_MOD_PERIOD(10000), + .STARTUP_WAIT("FALSE")) + mmcm_adv_inst + (.CLKFBIN(clkfbout_buf_clk_wiz_0), + .CLKFBOUT(clkfbout_clk_wiz_0), + .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), + .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), + .CLKIN1(clk_in1_clk_wiz_0), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), + .CLKOUT0(clk_out1_clk_wiz_0), + .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), + .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), + .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), + .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), + .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), + .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(locked), + .PSCLK(1'b0), + .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(1'b0), + .RST(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_sim_netlist.vhdl b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_sim_netlist.vhdl new file mode 100644 index 0000000..2be1a02 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_sim_netlist.vhdl @@ -0,0 +1,189 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 12:07:41 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl +-- Design : clk_wiz_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is + port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is + signal clk_in1_clk_wiz_0 : STD_LOGIC; + signal clk_out1_clk_wiz_0 : STD_LOGIC; + signal clkfbout_buf_clk_wiz_0 : STD_LOGIC; + signal clkfbout_clk_wiz_0 : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkin1_ibufgds : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of clkin1_ibufgds : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of clkin1_ibufgds : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of clkin1_ibufgds : label is "AUTO"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_clk_wiz_0, + O => clkfbout_buf_clk_wiz_0 + ); +clkin1_ibufgds: unisim.vcomponents.IBUFDS + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => clk_in1_p, + IB => clk_in1_n, + O => clk_in1_clk_wiz_0 + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => clk_out1_clk_wiz_0, + O => clk_out1 + ); +mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 10.000000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 10.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 10.000000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_DIVIDE => 1, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => clkfbout_buf_clk_wiz_0, + CLKFBOUT => clkfbout_clk_wiz_0, + CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, + CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, + CLKIN1 => clk_in1_clk_wiz_0, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, + CLKOUT0 => clk_out1_clk_wiz_0, + CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, + CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, + CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, + CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, + CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, + CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, + CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => locked, + PSCLK => '0', + PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +begin +inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz + port map ( + clk_in1_n => clk_in1_n, + clk_in1_p => clk_in1_p, + clk_out1 => clk_out1, + locked => locked + ); +end STRUCTURE; diff --git a/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_stub.v b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_stub.v new file mode 100644 index 0000000..53cba07 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 12:07:41 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, locked, clk_in1_p, clk_in1_n) +/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1_p,clk_in1_n" */; + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; +endmodule diff --git a/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_stub.vhdl b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..72e56c3 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/clk_wiz_0_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 12:07:41 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1_p,clk_in1_n"; +begin +end; diff --git a/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/stats.txt b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/stats.txt new file mode 100644 index 0000000..f5f8e48 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.cache/ip/2018.2/2fd8150145e5e4c7/stats.txt @@ -0,0 +1,4 @@ +NumberHits:0 +Timestamp: Sun Jun 28 04:07:41 UTC 2020 +VLNV: xilinx.com:ip:clk_wiz:6.0 +SynthRuntime: 29 diff --git a/localbus_demo/prj/localbus_demo.cache/wt/gui_handlers.wdf b/localbus_demo/prj/localbus_demo.cache/wt/gui_handlers.wdf new file mode 100644 index 0000000..686ba5d --- /dev/null +++ b/localbus_demo/prj/localbus_demo.cache/wt/gui_handlers.wdf @@ -0,0 +1,62 @@ +version:1 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+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/localbus_demo/prj/localbus_demo.hw/hw_1/hw.xml b/localbus_demo/prj/localbus_demo.hw/hw_1/hw.xml new file mode 100644 index 0000000..a8b6d6d --- /dev/null +++ b/localbus_demo/prj/localbus_demo.hw/hw_1/hw.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.hw/localbus_demo.lpr b/localbus_demo/prj/localbus_demo.hw/localbus_demo.lpr new file mode 100644 index 0000000..68b7fe8 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.hw/localbus_demo.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/README.txt b/localbus_demo/prj/localbus_demo.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo b/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo new file mode 100644 index 0000000..fa730ab --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo @@ -0,0 +1,80 @@ + +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1___100.000______0.000______50.0______130.958_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clk_wiz_0 instance_name + ( + // Clock out ports + .clk_out1(clk_out1), // output clk_out1 + // Status and control signals + .locked(locked), // output locked + // Clock in ports + .clk_in1_p(clk_in1_p), // input clk_in1_p + .clk_in1_n(clk_in1_n)); // input clk_in1_n +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v b/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100644 index 0000000..087991a --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 12:07:42 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub +// d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module clk_wiz_0(clk_out1, locked, clk_in1_p, clk_in1_n) +/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1_p,clk_in1_n" */; + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; +endmodule diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..02da164 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 12:07:42 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub +-- d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + +end clk_wiz_0; + +architecture stub of clk_wiz_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1_p,clk_in1_n"; +begin +end; diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh new file mode 100644 index 0000000..b233fde --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh @@ -0,0 +1,665 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: 7 Series || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1011_00, + 10'b0010_1101_00, + 10'b0010_0011_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0100_1111_00, + 10'b0101_1011_00, + 10'b0111_0111_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_1001_00, + 10'b1101_0001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0111_0001_00, + 10'b0111_0001_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0110_0001_00, + 10'b0110_0001_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0100_1010_00, + 10'b0011_1100_00, + 10'b0011_1100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh new file mode 100644 index 0000000..53ab5ad --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh @@ -0,0 +1,527 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: PLLE2 DRP +// Module Name: plle2_drp_func.h +// Version: 2.00 +// Target Devices: 7 Series || PLL +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// Updated for CR663854. +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + +`ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); +`endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end +`ifdef DEBUG + $display("round_frac: %h", round_frac); +`endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + +`ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); +`endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + +`ifdef DEBUG + $display("temp: %h", temp); +`endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1101_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0011_0111_00, + 10'b0011_0111_00, + 10'b0101_1111_00, + 10'b0111_1111_00, + 10'b0111_1011_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_1101_00, + 10'b1111_0111_00, + 10'b1111_1011_00, + 10'b1111_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); +`endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh new file mode 100644 index 0000000..99b88ca --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh @@ -0,0 +1,665 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: UltraScale Architecture || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_0011_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_1001_11, + 10'b0010_1001_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1011_11, + 10'b0011_1111_11, + 10'b0100_1111_11, + 10'b0100_1111_11, + 10'b0101_1111_11, + 10'b0110_1111_11, + 10'b0111_1111_11, + 10'b0111_1111_11, + 10'b1100_1111_11, + 10'b1101_1111_11, + 10'b1110_1111_11, + 10'b1111_1111_11, + 10'b1111_1111_11, + 10'b1110_0111_11, + 10'b1110_1011_11, + 10'b1111_0111_11, + 10'b1111_1011_11, + 10'b1111_1011_11, + 10'b1110_1101_11, + 10'b1111_1101_11, + 10'b1111_1101_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh new file mode 100644 index 0000000..d12a6f7 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh @@ -0,0 +1,524 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 6/15/2015 +// Design Name: PLLE3 DRP +// Module Name: plle3_drp_func.h +// Version: 1.10 +// Target Devices: UltraScale Architecture +// Tool versions: 2015.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// PM_Rise bits have been removed for PLLE3 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [759:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001 //19 + + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 19 + ); + + reg [639:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0010_1111_01, //1 + 10'b0010_0011_11, //2 + 10'b0011_0011_11, //3 + 10'b0010_0001_11, //4 + 10'b0010_0110_11, //5 + 10'b0010_1010_11, //6 + 10'b0010_1010_11, //7 + 10'b0011_0110_11, //8 + 10'b0010_1100_11, //9 + 10'b0010_1100_11, //10 + 10'b0010_1100_11, //11 + 10'b0010_0010_11, //12 + 10'b0011_1100_11, //13 + 10'b0011_1100_11, //14 + 10'b0011_1100_11, //15 + 10'b0011_1100_11, //16 + 10'b0011_0010_11, //17 + 10'b0011_0010_11, //18 + 10'b0011_0010_11 //19 + }; + + mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits +// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh new file mode 100644 index 0000000..60b4560 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh @@ -0,0 +1,855 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa. Updated by Ralf Krueger +// Date: 7/30/2014 +// Design Name: MMCME4 DRP +// Module Name: mmcme4_drp_func.h +// Version: 1.31 +// Target Devices: UltraScale Plus Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for UltraScal+ MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function +// 2/28/17 - Updated for Ultrascale Plus +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages during elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_phase-divide:%d,phase:%d", divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [7:0] divide // Max M divide is 128 in UltrascalePlus + ); + + reg [5119:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) + 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 + 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 + 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 + 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 + 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 + 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 + 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup_low; + reg [1279:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0011_1111_11, // M=1 - not legal + 10'b0011_1111_11, // M=2 + 10'b0011_1101_11, // M=3 + 10'b0011_0101_11, // M=4 + 10'b0011_1001_11, // M=5 + 10'b0011_1110_11, // M=6 + 10'b0011_1110_11, // M=7 + 10'b0011_0001_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0100_0110_11, + 10'b0011_1100_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, // M=127 + 10'b1101_1000_11 // M=128 +}; + + lookup_high = { + // CP_RES_LFHF + 10'b0111_1111_11, // M=1 - not legal + 10'b0111_1111_11, // M=2 + 10'b1110_1111_11, // M=3 + 10'b1111_1111_11, // M=4 + 10'b1111_1011_11, // M=5 + 10'b1111_1101_11, // M=6 + 10'b1111_0011_11, // M=7 + 10'b1110_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1110_0110_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11 // M=128 +}; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh new file mode 100644 index 0000000..9bfa6c8 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh @@ -0,0 +1,530 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ +// Date: 6/15/2015 +// Design Name: PLLE4 DRP +// Module Name: plle4_drp_func.h +// Version: 2.0 +// Target Devices: UltraScale+ Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// M_Rise bits have been removed for PLLE3 +// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for +// Ultrascale+ and for max M of 21 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [839:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+ + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001, //19 + 40'b11111_11111_0111110100_1111101001_0000000001, //20 + 40'b11111_11111_0111011011_1111101001_0000000001 //21 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [209:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0011_0111_11, //1 not legal in Ultrascale+ + 10'b0011_0111_11, //2 + 10'b0011_0011_11, //3 + 10'b0011_1001_11, //4 + 10'b0011_0001_11, //5 + 10'b0100_1110_11, //6 + 10'b0011_0110_11, //7 + 10'b0011_1010_11, //8 + 10'b0111_1001_11, //9 + 10'b0111_1001_11, //10 + 10'b0101_0110_11, //11 + 10'b1100_0101_11, //12 + 10'b0101_1010_11, //13 + 10'b0110_0110_11, //14 + 10'b0110_1010_11, //15 + 10'b0111_0110_11, //16 + 10'b1111_0101_11, //17 + 10'b1100_0110_11, //18 + 10'b1110_0001_11, //19 + 10'b1101_0110_11, //20 + 10'b1111_0001_11 //21 + }; + + mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" +// will need to divide the doubled clock VCO clock frequency by +// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will +// need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/README.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/README.txt new file mode 100644 index 0000000..31ae1c2 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt new file mode 100644 index 0000000..e380fa4 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 12:07:07 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh new file mode 100644 index 0000000..83d0ad6 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 12:07:07 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.cache/compile_simlib/activehdl" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do new file mode 100644 index 0000000..d523a3e --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt new file mode 100644 index 0000000..381e7c9 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do new file mode 100644 index 0000000..a31d6d9 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+clk_wiz_0 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {clk_wiz_0.udo} + +run -all + +endsim + +quit -force diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt new file mode 100644 index 0000000..b8156ef --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 12:07:07 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh new file mode 100644 index 0000000..89b6ec2 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 12:07:07 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.clk_wiz_0 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic" \ + +incdir+"../../../ipstatic" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt new file mode 100644 index 0000000..5939c24 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f new file mode 100644 index 0000000..6325987 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib ies_lib/xpm \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ + "../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt new file mode 100644 index 0000000..e380fa4 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 12:07:07 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh new file mode 100644 index 0000000..9005241 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 12:07:07 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do new file mode 100644 index 0000000..b04bfb4 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do @@ -0,0 +1,22 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm + +vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt new file mode 100644 index 0000000..381e7c9 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do new file mode 100644 index 0000000..a44f519 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {clk_wiz_0.udo} + +run -all + +quit -force diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt new file mode 100644 index 0000000..e380fa4 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 12:07:07 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh new file mode 100644 index 0000000..32fe3e0 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 12:07:07 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do new file mode 100644 index 0000000..15df4eb --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do new file mode 100644 index 0000000..b2b0781 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_opt diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt new file mode 100644 index 0000000..381e7c9 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do new file mode 100644 index 0000000..77fdf30 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib clk_wiz_0_opt + +do {wave.do} + +view wave +view structure +view signals + +do {clk_wiz_0.udo} + +run -all + +quit -force diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt new file mode 100644 index 0000000..e380fa4 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 12:07:07 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh new file mode 100644 index 0000000..bd6fc48 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 12:07:07 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do new file mode 100644 index 0000000..925d9fd --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \ +"../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt new file mode 100644 index 0000000..381e7c9 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do new file mode 100644 index 0000000..a31d6d9 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+clk_wiz_0 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {clk_wiz_0.udo} + +run -all + +endsim + +quit -force diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do new file mode 100644 index 0000000..70157b0 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt new file mode 100644 index 0000000..e380fa4 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 12:07:07 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh new file mode 100644 index 0000000..ea204ab --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh @@ -0,0 +1,229 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 12:07:07 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ipstatic" \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic" \ + "$ref_dir/../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ + "$ref_dir/../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_simv +} + +# RUN_STEP: +simulate() +{ + ./clk_wiz_0_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key clk_wiz_0_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc clk_wiz_0_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt new file mode 100644 index 0000000..5939c24 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do new file mode 100644 index 0000000..58afc78 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt new file mode 100644 index 0000000..b8156ef --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 12:07:07 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh new file mode 100644 index 0000000..79f73d1 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 12:07:07 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.clk_wiz_0 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic" \ + +incdir+"../../../ipstatic" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt new file mode 100644 index 0000000..5939c24 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f new file mode 100644 index 0000000..142431e --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "E:/Xilinx/Vivado/2018.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ + "../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt new file mode 100644 index 0000000..e380fa4 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2018.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Sun Jun 28 12:07:07 +0800 2020 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh new file mode 100644 index 0000000..9e54eeb --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh @@ -0,0 +1,211 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2018.2 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Sun Jun 28 12:07:07 +0800 2020 +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xvlog_opts="--relax" + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2018.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot clk_wiz_0 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim clk_wiz_0 -key {Behavioral:sim_1:Functional:clk_wiz_0} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="E:/Xilinx/Vivado/2018.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb clk_wiz_0.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl new file mode 100644 index 0000000..eef7a0f --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/elab.opt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/elab.opt new file mode 100644 index 0000000..6114c45 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/elab.opt @@ -0,0 +1 @@ +--relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot clk_wiz_0 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -log elaborate.log diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt new file mode 100644 index 0000000..f9c19a8 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt @@ -0,0 +1,3 @@ +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj new file mode 100644 index 0000000..885b54d --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj @@ -0,0 +1,7 @@ +verilog xil_defaultlib --include "../../../ipstatic" \ +"../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/xsim.ini b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/xsim.ini new file mode 100644 index 0000000..85c72ed --- /dev/null +++ b/localbus_demo/prj/localbus_demo.ip_user_files/sim_scripts/clk_wiz_0/xsim/xsim.ini @@ -0,0 +1,349 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +v_mix_v3_0_1=$RDI_DATADIR/xsim/ip/v_mix_v3_0_1 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +etrnic_v1_1_0=$RDI_DATADIR/xsim/ip/etrnic_v1_1_0 +vfb_v1_0_11=$RDI_DATADIR/xsim/ip/vfb_v1_0_11 +tmr_manager_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_3 +xbip_bram18k_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_5 +jesd204c_v3_0_1=$RDI_DATADIR/xsim/ip/jesd204c_v3_0_1 +pc_cfr_v6_0_7=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_7 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +lte_rach_detector_v3_1_3=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_3 +axi_apb_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_14 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +v_ccm_v6_0_14=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_14 +c_gate_bit_v12_0_5=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_5 +g709_rs_encoder_v2_2_5=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_5 +g709_fec_v2_3_3=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_3 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +canfd_v1_0_10=$RDI_DATADIR/xsim/ip/canfd_v1_0_10 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +ten_gig_eth_mac_v15_1_6=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_6 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+util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +axis_clock_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_18 +axi_quad_spi_v3_2_16=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_16 +mipi_dphy_v4_1_1=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_1 +v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +axi_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_3 +axi_ethernet_buffer_v2_0_18=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_18 +ieee802d3_200g_rs_fec_v1_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_3 +dds_compiler_v6_0_16=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_16 +pc_cfr_v6_1_3=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_3 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +mult_gen_v12_0_14=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_14 +axi_fifo_mm_s_v4_1_14=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_14 +axi_epc_v2_0_20=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_20 +v_gamma_lut_v1_0_3=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_3 +tmr_comparator_v1_0_1=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_1 +can_v5_0_20=$RDI_DATADIR/xsim/ip/can_v5_0_20 +interlaken_v2_4_1=$RDI_DATADIR/xsim/ip/interlaken_v2_4_1 +axi_intc_v4_1_11=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_11 +ieee802d3_25g_rs_fec_v1_0_9=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_9 +v_csc_v1_0_11=$RDI_DATADIR/xsim/ip/v_csc_v1_0_11 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +xbip_dsp48_acc_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_5 +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +v_frmbuf_rd_v2_1_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_0 +compact_gt_v1_0_3=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_3 +c_compare_v12_0_5=$RDI_DATADIR/xsim/ip/c_compare_v12_0_5 +tri_mode_ethernet_mac_v9_0_12=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_12 +lte_ul_channel_decoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_14 +ieee802d3_50g_rs_fec_v1_0_9=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_9 +g709_rs_decoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_6 +cmac_v2_3_3=$RDI_DATADIR/xsim/ip/cmac_v2_3_3 +rs_toolbox_v9_0_5=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_5 +i2s_transmitter_v1_0_1=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_1 +floating_point_v7_0_15=$RDI_DATADIR/xsim/ip/floating_point_v7_0_15 +g975_efec_i7_v2_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_17 +axi_pcie3_v3_0_7=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_7 +axi_traffic_gen_v3_0_3=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_3 +axi_crossbar_v2_1_18=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_18 +sd_fec_v1_0_1=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_1 +xbip_dsp48_addsub_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_5 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +c_reg_fd_v12_0_5=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_5 +pc_cfr_v6_2_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_0 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +axi_vip_v1_1_3=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_3 +xlconcat_v2_1_1=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_1 +tmr_voter_v1_0_1=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_1 +xlconstant_v1_1_5=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_5 +c_shift_ram_v12_0_12=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_12 +duc_ddc_compiler_v3_0_14=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_14 +v_tc_v6_1_12=$RDI_DATADIR/xsim/ip/v_tc_v6_1_12 +ieee802d3_clause74_fec_v1_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_1 +xhmc_v1_0_7=$RDI_DATADIR/xsim/ip/xhmc_v1_0_7 +vid_phy_controller_v2_2_1=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_1 +uhdsdi_gt_v1_0_2=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_2 +lte_3gpp_mimo_decoder_v3_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_14 +axi_firewall_v1_0_5=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_5 +axi_usb2_device_v5_0_18=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_18 +xbip_dsp48_mult_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_5 +v_hscaler_v1_0_11=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_11 +axis_data_fifo_v1_1_18=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_18 +floating_point_v7_1_6=$RDI_DATADIR/xsim/ip/floating_point_v7_1_6 +axi_clock_converter_v2_1_16=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_16 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +tcc_decoder_3gppmm_v2_0_17=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_17 +v_vscaler_v1_0_11=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_11 +qdma_v2_0_0=$RDI_DATADIR/xsim/ip/qdma_v2_0_0 +axi_emc_v3_0_17=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_17 +dft_v4_0_15=$RDI_DATADIR/xsim/ip/dft_v4_0_15 +rst_vip_v1_0_1=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_1 +xxv_ethernet_v2_4_1=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_1 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +axi_dwidth_converter_v2_1_17=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_17 +sid_v8_0_12=$RDI_DATADIR/xsim/ip/sid_v8_0_12 +v_vid_in_axi4s_v4_0_8=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_8 +v_cfa_v7_0_13=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_13 +v_enhance_v8_0_14=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_14 +displayport_v8_0_1=$RDI_DATADIR/xsim/ip/displayport_v8_0_1 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +axi_sideband_util_v1_0_1=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_1 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +lib_bmg_v1_0_10=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_10 +fir_compiler_v7_2_11=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_11 +blk_mem_gen_v8_4_1=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_1 +ecc_v2_0_12=$RDI_DATADIR/xsim/ip/ecc_v2_0_12 +axi_datamover_v5_1_19=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_19 +displayport_v7_0_9=$RDI_DATADIR/xsim/ip/displayport_v7_0_9 +v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 +tmr_inject_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_2 +i2s_receiver_v1_0_1=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_1 +axis_protocol_checker_v1_2_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v1_2_3 +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +gig_ethernet_pcs_pma_v16_1_4=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_4 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +pci32_v5_0_11=$RDI_DATADIR/xsim/ip/pci32_v5_0_11 +xbip_dsp48_macro_v3_0_16=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_16 +v_smpte_uhdsdi_v1_0_5=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_5 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +axi4svideo_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_9 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 +sd_fec_v1_1_1=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_1 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +div_gen_v5_1_13=$RDI_DATADIR/xsim/ip/div_gen_v5_1_13 +high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 +sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 +axi_utils_v2_0_5=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_5 +gtwizard_ultrascale_v1_6_10=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_10 +g975_efec_i4_v1_0_15=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_15 +mii_to_rmii_v2_0_19=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_19 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +cpri_v8_9_1=$RDI_DATADIR/xsim/ip/cpri_v8_9_1 +axi_timebase_wdt_v3_0_9=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_9 +quadsgmii_v3_4_4=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_4 +tcc_encoder_3gpplte_v4_0_14=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_14 +cmpy_v6_0_15=$RDI_DATADIR/xsim/ip/cmpy_v6_0_15 +axi_cdma_v4_1_17=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_17 +axi_uartlite_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_21 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +xbip_pipe_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_5 +axis_accelerator_adapter_v2_1_13=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_13 +ieee802d3_400g_rs_fec_v1_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_3 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +v_rgb2ycrcb_v7_1_12=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_12 +ats_switch_v1_0_0=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_0 +v_gamma_v7_0_14=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_14 +lte_dl_channel_encoder_v3_0_14=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_14 +gmii_to_rgmii_v4_0_6=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_6 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +fit_timer_v2_0_8=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_8 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +convolution_v9_0_13=$RDI_DATADIR/xsim/ip/convolution_v9_0_13 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +xfft_v9_0_15=$RDI_DATADIR/xsim/ip/xfft_v9_0_15 +axi_register_slice_v2_1_17=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_17 +axi4stream_vip_v1_1_3=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_3 +xfft_v7_2_7=$RDI_DATADIR/xsim/ip/xfft_v7_2_7 +xbip_utils_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_9 +axi_tft_v2_0_20=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_20 +l_ethernet_v2_3_3=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_3 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +v_frmbuf_wr_v2_0_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_0_3 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +axi_data_fifo_v2_1_16=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_16 +audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 +usxgmii_v1_0_3=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_3 +dist_mem_gen_v8_0_12=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_12 +mailbox_v2_1_10=$RDI_DATADIR/xsim/ip/mailbox_v2_1_10 +v_demosaic_v1_0_3=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_3 +ethernet_1_10_25g_v2_1_0=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_0 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +axi_traffic_gen_v2_0_18=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_18 +axi_dma_v7_1_18=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_18 +axi_ahblite_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_14 +axi_sg_v4_1_10=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_10 +xbip_dsp48_multadd_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_5 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +rxaui_v4_4_4=$RDI_DATADIR/xsim/ip/rxaui_v4_4_4 +v_ycrcb2rgb_v7_1_12=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_12 +video_frame_crc_v1_0_0=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_0 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +pr_decoupler_v1_0_6=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_6 +tcc_encoder_3gpp_v5_0_13=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_13 +microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 +lib_fifo_v1_0_11=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_11 +v_letterbox_v1_0_11=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_11 +v_cresample_v4_0_13=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_13 +axi_msg_v1_0_3=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_3 +gtwizard_ultrascale_v1_7_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_4 +zynq_ultra_ps_e_v3_2_1=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_1 +c_mux_bit_v12_0_5=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_5 +axis_register_slice_v1_1_17=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_17 +hdcp22_cipher_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_2 +xfft_v9_1_0=$RDI_DATADIR/xsim/ip/xfft_v9_1_0 +axis_combiner_v1_1_15=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_15 +xbip_dsp48_multacc_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_5 +lmb_bram_if_cntlr_v4_0_15=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_15 +zynq_ultra_ps_e_vip_v1_0_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_3 +axi_protocol_checker_v1_1_17=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v1_1_17 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +axis_protocol_checker_v2_0_1=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_1 +ieee802d3_rs_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_13 +v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 +tsn_temac_v1_0_3=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_3 +xlslice_v1_0_1=$RDI_DATADIR/xsim/ip/xlslice_v1_0_1 +fec_5g_common_v1_0_0=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_0 +oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 +rs_decoder_v9_0_14=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_14 +v_axi4s_remap_v1_0_9=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_9 +v_frmbuf_rd_v2_0_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_0_3 +ahblite_axi_bridge_v3_0_13=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_13 +axi_protocol_converter_v2_1_17=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_17 +axi_vfifo_ctrl_v2_0_19=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_19 +iomodule_v3_1_3=$RDI_DATADIR/xsim/ip/iomodule_v3_1_3 +xbip_multadd_v3_0_12=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_12 +rs_encoder_v9_0_13=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_13 +axis_switch_v1_1_17=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_17 +cordic_v6_0_14=$RDI_DATADIR/xsim/ip/cordic_v6_0_14 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +v_osd_v6_0_15=$RDI_DATADIR/xsim/ip/v_osd_v6_0_15 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +lte_fft_v2_0_16=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_16 +axi_gpio_v2_0_19=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_19 +xaui_v12_3_4=$RDI_DATADIR/xsim/ip/xaui_v12_3_4 +axis_subset_converter_v1_1_17=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_17 +axi_uart16550_v2_0_19=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_19 +ldpc_v2_0_1=$RDI_DATADIR/xsim/ip/ldpc_v2_0_1 +tsn_endpoint_ethernet_mac_block_v1_0_2=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_2 +v_frmbuf_wr_v2_1_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_0 +pr_bitstream_monitor_v1_0_0=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_0 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +axi_interconnect_v1_7_14=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_14 +lte_3gpp_channel_estimator_v2_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_15 +vid_phy_controller_v2_1_0=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_0 +xbip_counter_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_5 +etrnic_v1_0_1=$RDI_DATADIR/xsim/ip/etrnic_v1_0_1 +axi_timer_v2_0_19=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_19 +ta_dma_v1_0_1=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_1 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +axis_broadcaster_v1_1_16=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_16 +amm_axi_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_3 +fec_5g_common_v1_1_0=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +v_uhdsdi_vidgen_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_0 +lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 +lte_3gpp_mimo_encoder_v4_0_13=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_13 +c_addsub_v12_0_12=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_12 +c_mux_bus_v12_0_5=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_5 +axi_chip2chip_v5_0_3=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_3 +axis_dwidth_converter_v1_1_16=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_16 +processing_system7_vip_v1_0_5=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_5 +spdif_v2_0_19=$RDI_DATADIR/xsim/ip/spdif_v2_0_19 +v_tpg_v7_0_11=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_11 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +fifo_generator_v13_2_2=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_2 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +pr_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_0 +in_system_ibert_v1_0_7=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_7 +axi_amm_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_7 +xbip_accum_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_5 +sem_ultra_v3_1_8=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_8 +viterbi_v9_1_9=$RDI_DATADIR/xsim/ip/viterbi_v9_1_9 +high_speed_selectio_wiz_v3_4_0=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_0 +v_axi4s_vid_out_v4_0_9=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_9 +axi_iic_v2_0_20=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_20 +axi_hwicap_v3_0_21=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_21 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +system_cache_v4_0_5=$RDI_DATADIR/xsim/ip/system_cache_v4_0_5 +ieee802d3_rs_fec_v2_0_1=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_1 +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +axis_interconnect_v1_1_15=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_15 +v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 +c_counter_binary_v12_0_12=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_12 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +fc32_rs_fec_v1_0_7=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_7 +axi_vdma_v6_3_5=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_5 +fir_compiler_v5_2_5=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_5 +xpm=$RDI_DATADIR/xsim/ip/xpm +axi_mcdma_v1_0_3=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_3 +lte_pucch_receiver_v2_0_14=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_14 +proc_sys_reset_v5_0_12=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_12 +polar_v1_0_1=$RDI_DATADIR/xsim/ip/polar_v1_0_1 +tmr_sem_v1_0_5=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_5 +cic_compiler_v4_0_13=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_13 +mdm_v3_2_14=$RDI_DATADIR/xsim/ip/mdm_v3_2_14 +prc_v1_3_1=$RDI_DATADIR/xsim/ip/prc_v1_3_1 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +jesd204_v7_2_3=$RDI_DATADIR/xsim/ip/jesd204_v7_2_3 +axi_perf_mon_v5_0_19=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_19 +av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0 +axi_ethernetlite_v3_0_15=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_15 +sem_v4_1_11=$RDI_DATADIR/xsim/ip/sem_v4_1_11 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +switch_core_top_v1_0_5=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_5 +axi_pcie_v2_8_9=$RDI_DATADIR/xsim/ip/axi_pcie_v2_8_9 +v_dual_splitter_v1_0_8=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_8 +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +xbip_addsub_v3_0_5=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_5 +ethernet_1_10_25g_v2_0_1=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_1 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +axi_mm2s_mapper_v1_1_16=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_16 +axis_protocol_checker_v1_1_16=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v1_1_16 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +c_accum_v12_0_12=$RDI_DATADIR/xsim/ip/c_accum_v12_0_12 +clk_vip_v1_0_1=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_1 +v_hcresampler_v1_0_11=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_11 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 diff --git a/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_1.xml b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..7fbc5cd --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_2.xml b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..173a554 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_3.xml b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..4d161b7 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_4.xml b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..4d161b7 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_5.xml b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..4d161b7 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_6.xml b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..4d161b7 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_7.xml b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..4d161b7 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_8.xml b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..4d161b7 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc new file mode 100644 index 0000000..eb505d6 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc @@ -0,0 +1,3 @@ +set_property SRC_FILE_INFO {cfile:d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc rfile:../../../localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc id:1 order:EARLY scoped_inst:inst} [current_design] +set_property src_info {type:SCOPED_XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.1 diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/.vivado.begin.rst b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/.vivado.begin.rst new file mode 100644 index 0000000..c202759 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/.vivado.end.rst b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/ISEWrap.js b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/ISEWrap.js new file mode 100644 index 0000000..898ddd7 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/ISEWrap.sh b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/__synthesis_is_complete__ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp new file mode 100644 index 0000000..1cdd355 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp differ diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl new file mode 100644 index 0000000..187929e --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl @@ -0,0 +1,173 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_msg_config -id {HDL-1065} -limit 10000 +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7k160tffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.cache/wt [current_project] +set_property parent.project_path D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.xpr [current_project] +set_property XPM_LIBRARIES XPM_CDC [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 0 + +set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1 -new_name clk_wiz_0 -ip [get_ips clk_wiz_0]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top clk_wiz_0 -part xc7k160tffg676-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix clk_wiz_0_ clk_wiz_0.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v + lappend ipCachedFiles clk_wiz_0_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl + lappend ipCachedFiles clk_wiz_0_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v + lappend ipCachedFiles clk_wiz_0_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl + lappend ipCachedFiles clk_wiz_0_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp clk_wiz_0.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips clk_wiz_0] +} + +rename_ref -prefix_all clk_wiz_0_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef clk_wiz_0.dcp +create_report "clk_wiz_0_synth_1_synth_report_utilization_0" "report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb" + +if { [catch { + file copy -force D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.v d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.vhdl d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.v d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.vhdl d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +}; # end if cached_ip + +if {[file isdir D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0]} { + catch { + file copy -force d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0 + } +} + +if {[file isdir D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0]} { + catch { + file copy -force d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.ip_user_files/ip/clk_wiz_0 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.vds b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.vds new file mode 100644 index 0000000..aa93014 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.vds @@ -0,0 +1,334 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun Jun 28 12:07:09 2020 +# Process ID: 6208 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1 +# Command line: vivado.exe -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl +# Log file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.vds +# Journal file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1\vivado.jou +#----------------------------------------------------------- +source clk_wiz_0.tcl -notrace +Command: synth_design -top clk_wiz_0 -part xc7k160tffg676-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 6400 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 394.297 ; gain = 93.051 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] + Parameter CAPACITANCE bound to: DONT_CARE - type: string + Parameter DIFF_TERM bound to: FALSE - type: string + Parameter DQS_BIAS bound to: FALSE - type: string + Parameter IBUF_DELAY_VALUE bound to: 0 - type: string + Parameter IBUF_LOW_PWR bound to: TRUE - type: string + Parameter IFD_DELAY_VALUE bound to: AUTO - type: string + Parameter IOSTANDARD bound to: DEFAULT - type: string +INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (1#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: float + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float + Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float + Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string + Parameter COMPENSATION bound to: ZHOLD - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 + Parameter IS_PSEN_INVERTED bound to: 1'b0 + Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 + Parameter IS_PWRDWN_INVERTED bound to: 1'b0 + Parameter IS_RST_INVERTED bound to: 1'b0 + Parameter REF_JITTER1 bound to: 0.010000 - type: float + Parameter REF_JITTER2 bound to: 0.010000 - type: float + Parameter SS_EN bound to: FALSE - type: string + Parameter SS_MODE bound to: CENTER_HIGH - type: string + Parameter SS_MOD_PERIOD bound to: 10000 - type: integer + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (2#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (3#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (5#1) [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.582 ; gain = 143.336 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.582 ; gain = 143.336 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.582 ; gain = 143.336 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 714.941 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 780.641 ; gain = 479.395 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 780.641 ; gain = 479.395 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 780.641 ; gain = 479.395 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |BUFG | 2| +|2 |MMCME2_ADV | 1| +|3 |IBUFDS | 1| ++------+-----------+------+ + +Report Instance Areas: ++------+---------+------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------+------+ +|1 |top | | 4| +|2 | inst |clk_wiz_0_clk_wiz | 4| ++------+---------+------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 782.258 ; gain = 210.652 +Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.262 ; gain = 481.012 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 804.223 ; gain = 514.445 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 808.566 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Sun Jun 28 12:07:42 2020... diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb new file mode 100644 index 0000000..c36a500 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt new file mode 100644 index 0000000..ed2a956 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt @@ -0,0 +1,175 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 12:07:42 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb +| Design : clk_wiz_0 +| Device : 7k160tffg676-2 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 0 | 0 | 101400 | 0.00 | +| LUT as Logic | 0 | 0 | 101400 | 0.00 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 0 | 0 | 202800 | 0.00 | +| Register as Flip Flop | 0 | 0 | 202800 | 0.00 | +| Register as Latch | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 2 | 0 | 400 | 0.50 | +| Bonded IPADs | 0 | 0 | 26 | 0.00 | +| Bonded OPADs | 0 | 0 | 16 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 1 | 0 | 384 | 0.26 | +| GTXE2_COMMON | 0 | 0 | 2 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 8 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 400 | 0.00 | +| OLOGIC | 0 | 0 | 400 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 2 | 0 | 32 | 6.25 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 1 | 0 | 8 | 12.50 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++------------+------+---------------------+ +| Ref Name | Used | Functional Category | ++------------+------+---------------------+ +| BUFG | 2 | Clock | +| MMCME2_ADV | 1 | Clock | +| IBUFDS | 1 | IO | ++------------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc new file mode 100644 index 0000000..a517012 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# IP: d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/gen_run.xml b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/gen_run.xml new file mode 100644 index 0000000..f536579 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/gen_run.xml @@ -0,0 +1,39 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/htr.txt b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/htr.txt new file mode 100644 index 0000000..fb945d9 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/project.wdf b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/project.wdf new file mode 100644 index 0000000..1c6ba3a --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/project.wdf @@ -0,0 +1,32 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:32:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:32:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f315c636c6b5f77697a5f30:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6633363433623662323835653438333962356339346139623438663237366563:506172656e742050412070726f6a656374204944:00 +eof:2565217521 diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/rundef.js b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/rundef.js new file mode 100644 index 0000000..c2880b8 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;"; +} else { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/runme.bat b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/runme.bat new file mode 100644 index 0000000..73c8b46 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/runme.log b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/runme.log new file mode 100644 index 0000000..8eda6da --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/runme.log @@ -0,0 +1,333 @@ + +*** Running vivado + with args -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source clk_wiz_0.tcl -notrace +Command: synth_design -top clk_wiz_0 -part xc7k160tffg676-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 6400 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 394.297 ; gain = 93.051 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] + Parameter CAPACITANCE bound to: DONT_CARE - type: string + Parameter DIFF_TERM bound to: FALSE - type: string + Parameter DQS_BIAS bound to: FALSE - type: string + Parameter IBUF_DELAY_VALUE bound to: 0 - type: string + Parameter IBUF_LOW_PWR bound to: TRUE - type: string + Parameter IFD_DELAY_VALUE bound to: AUTO - type: string + Parameter IOSTANDARD bound to: DEFAULT - type: string +INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (1#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19488] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: float + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float + Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float + Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string + Parameter COMPENSATION bound to: ZHOLD - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 + Parameter IS_PSEN_INVERTED bound to: 1'b0 + Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 + Parameter IS_PWRDWN_INVERTED bound to: 1'b0 + Parameter IS_RST_INVERTED bound to: 1'b0 + Parameter REF_JITTER1 bound to: 0.010000 - type: float + Parameter REF_JITTER2 bound to: 0.010000 - type: float + Parameter SS_EN bound to: FALSE - type: string + Parameter SS_MODE bound to: CENTER_HIGH - type: string + Parameter SS_MOD_PERIOD bound to: 10000 - type: integer + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (2#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (3#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (5#1) [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.582 ; gain = 143.336 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.582 ; gain = 143.336 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.582 ; gain = 143.336 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 714.941 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 714.941 ; gain = 413.695 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 780.641 ; gain = 479.395 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 780.641 ; gain = 479.395 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 780.641 ; gain = 479.395 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |BUFG | 2| +|2 |MMCME2_ADV | 1| +|3 |IBUFDS | 1| ++------+-----------+------+ + +Report Instance Areas: ++------+---------+------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------+------+ +|1 |top | | 4| +|2 | inst |clk_wiz_0_clk_wiz | 4| ++------+---------+------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.258 ; gain = 481.012 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 782.258 ; gain = 210.652 +Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 782.262 ; gain = 481.012 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 804.223 ; gain = 514.445 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 808.566 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Sun Jun 28 12:07:42 2020... diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/runme.sh b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/runme.sh new file mode 100644 index 0000000..e0b1834 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin +else + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/vivado.jou b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/vivado.jou new file mode 100644 index 0000000..faf7470 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun Jun 28 12:07:09 2020 +# Process ID: 6208 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1 +# Command line: vivado.exe -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl +# Log file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/clk_wiz_0.vds +# Journal file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1\vivado.jou +#----------------------------------------------------------- +source clk_wiz_0.tcl -notrace diff --git a/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/vivado.pb b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/vivado.pb new file mode 100644 index 0000000..5f09650 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/clk_wiz_0_synth_1/vivado.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.Vivado_Implementation.queue.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.init_design.begin.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..c9c1044 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.init_design.end.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.opt_design.begin.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..c9c1044 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.opt_design.end.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.place_design.begin.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..c9c1044 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.place_design.end.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.route_design.begin.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..c9c1044 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.route_design.end.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.vivado.begin.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..f80ce87 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.vivado.end.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.write_bitstream.begin.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.write_bitstream.begin.rst new file mode 100644 index 0000000..c9c1044 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/.write_bitstream.end.rst b/localbus_demo/prj/localbus_demo.runs/impl_1/.write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/ISEWrap.js b/localbus_demo/prj/localbus_demo.runs/impl_1/ISEWrap.js new file mode 100644 index 0000000..898ddd7 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/ISEWrap.sh b/localbus_demo/prj/localbus_demo.runs/impl_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/gen_run.xml b/localbus_demo/prj/localbus_demo.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..5048334 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/gen_run.xml @@ -0,0 +1,113 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/htr.txt b/localbus_demo/prj/localbus_demo.runs/impl_1/htr.txt new file mode 100644 index 0000000..5ade73f --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log t160_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/init_design.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/init_design.pb new file mode 100644 index 0000000..c4a90d2 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/init_design.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/opt_design.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..122e35a Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/opt_design.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/place_design.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/place_design.pb new file mode 100644 index 0000000..0be9a36 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/place_design.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/project.wdf b/localbus_demo/prj/localbus_demo.runs/impl_1/project.wdf new file mode 100644 index 0000000..02ea658 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/project.wdf @@ -0,0 +1,32 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6633363433623662323835653438333962356339346139623438663237366563:506172656e742050412070726f6a656374204944:00 +eof:1184151885 diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/route_design.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/route_design.pb new file mode 100644 index 0000000..038ad37 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/route_design.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/rundef.js b/localbus_demo/prj/localbus_demo.runs/impl_1/rundef.js new file mode 100644 index 0000000..59036ea --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;"; +} else { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log t160_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/runme.bat b/localbus_demo/prj/localbus_demo.runs/impl_1/runme.bat new file mode 100644 index 0000000..73c8b46 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/runme.log b/localbus_demo/prj/localbus_demo.runs/impl_1/runme.log new file mode 100644 index 0000000..f7fbdb0 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/runme.log @@ -0,0 +1,511 @@ + +*** Running vivado + with args -log t160_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source t160_top.tcl -notrace +Command: link_design -top t160_top -part xc7k160tffg676-2 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Project 1-454] Reading design checkpoint 'd:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_uut' +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.2 +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_uut/inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_uut/inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_uut/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57] +INFO: [Timing 38-2] Deriving generated clocks [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57] +get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1209.469 ; gain = 571.266 +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_uut/inst' +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.469 ; gain = 918.840 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1209.469 ; gain = 0.000 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 595f03c7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1226.684 ; gain = 17.215 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: a051a4aa + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: a051a4aa + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 7926d846 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 4 cells and removed 4 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: bb35cfad + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.071 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 166adf6af + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 14616ccb6 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.101 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1226.684 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1f236a5c2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.107 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1f236a5c2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 1f236a5c2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx +Command: report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1226.684 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 10a941337 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17841d01d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 23c507a61 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 23c507a61 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1226.684 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 23c507a61 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 259762b91 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 2.2 Physical Synthesis In Placer +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------- +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +----------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.2 Physical Synthesis In Placer | Checksum: 1a6481c74 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1226.684 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 239574972 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 239574972 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18e01976c + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 21128bd03 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 16a808333 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1dfe407d1 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 19eb30d16 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 19eb30d16 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 19eb30d16 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 14919c2a9 + +Phase 4.1.1.1 BUFG Insertion +INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. +Phase 4.1.1.1 BUFG Insertion | Checksum: 14919c2a9 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 +INFO: [Place 30-746] Post Placement Timing Summary WNS=7.318. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: 172a02f26 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 +Phase 4.1 Post Commit Optimization | Checksum: 172a02f26 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 172a02f26 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 172a02f26 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1d643fa80 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d643fa80 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 +Ending Placer Task | Checksum: 15c878133 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 +INFO: [Common 17-83] Releasing license: Implementation +49 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 1237.238 ; gain = 5.602 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file t160_top_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.068 . Memory (MB): peak = 1237.238 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file t160_top_utilization_placed.rpt -pb t160_top_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 1237.238 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file t160_top_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1237.238 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 7358067c ConstDB: 0 ShapeSum: e92f7ab7 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: d4650f61 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:18 . Memory (MB): peak = 1421.711 ; gain = 184.473 +Post Restoration Checksum: NetGraph: 2c2f3835 NumContArr: a835d72c Constraints: 0 Timing: 0 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: d4650f61 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:18 . Memory (MB): peak = 1421.711 ; gain = 184.473 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: d4650f61 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:18 . Memory (MB): peak = 1426.320 ; gain = 189.082 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: d4650f61 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:18 . Memory (MB): peak = 1426.320 ; gain = 189.082 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: 1d5345b0a + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.320 | TNS=0.000 | WHS=-0.122 | THS=-12.104| + +Phase 2 Router Initialization | Checksum: 25cc314a8 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 21b1e8b71 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 28 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.216 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 283fe09fb + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +Phase 4 Rip-up And Reroute | Checksum: 283fe09fb + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: 283fe09fb + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 283fe09fb + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +Phase 5 Delay and Skew Optimization | Checksum: 283fe09fb + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 28f70be37 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.301 | TNS=0.000 | WHS=0.086 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 28f70be37 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +Phase 6 Post Hold Fix | Checksum: 28f70be37 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0425121 % + Global Horizontal Routing Utilization = 0.0411338 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: 28f70be37 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 28f70be37 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 1c7888497 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=7.301 | TNS=0.000 | WHS=0.086 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: 1c7888497 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:20 . Memory (MB): peak = 1444.344 ; gain = 207.105 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.080 . Memory (MB): peak = 1444.344 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx +Command: report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx +Command: report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx +Command: report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +78 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file t160_top_route_status.rpt -pb t160_top_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file t160_top_timing_summary_routed.rpt -pb t160_top_timing_summary_routed.pb -rpx t160_top_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [runtcl-4] Executing : report_incremental_reuse -file t160_top_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file t160_top_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file t160_top_bus_skew_routed.rpt -pb t160_top_bus_skew_routed.pb -rpx t160_top_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force t160_top.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./t160_top.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +96 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1894.738 ; gain = 432.953 +INFO: [Common 17-206] Exiting Vivado at Sun Jun 28 17:15:57 2020... diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/runme.sh b/localbus_demo/prj/localbus_demo.runs/impl_1/runme.sh new file mode 100644 index 0000000..99721fc --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/runme.sh @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin +else + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log t160_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top.bit b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top.bit new file mode 100644 index 0000000..dd3c753 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top.bit differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top.tcl b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top.tcl new file mode 100644 index 0000000..5838540 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top.tcl @@ -0,0 +1,173 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + create_project -in_memory -part xc7k160tffg676-2 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.cache/wt [current_project] + set_property parent.project_path D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.xpr [current_project] + set_property ip_output_repo D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + set_property XPM_LIBRARIES XPM_CDC [current_project] + add_files -quiet D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.dcp + read_ip -quiet D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci + read_edif D:/Xilinx/xjtag/xjtag_ip/localbus_ip/xjtag_bus.ngc + read_xdc D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc + link_design -top t160_top -part xc7k160tffg676-2 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force t160_top_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force t160_top_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file t160_top_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file t160_top_utilization_placed.rpt -pb t160_top_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file t160_top_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force t160_top_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file t160_top_route_status.rpt -pb t160_top_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file t160_top_timing_summary_routed.rpt -pb t160_top_timing_summary_routed.pb -rpx t160_top_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file t160_top_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file t160_top_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file t160_top_bus_skew_routed.rpt -pb t160_top_bus_skew_routed.pb -rpx t160_top_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force t160_top_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_property XPM_LIBRARIES XPM_CDC [current_project] + catch { write_mem_info -force t160_top.mmi } + write_bitstream -force t160_top.bit + catch {write_debug_probes -quiet -force t160_top} + catch {file copy -force t160_top.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top.vdi b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top.vdi new file mode 100644 index 0000000..5cdc43f --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top.vdi @@ -0,0 +1,512 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun Jun 28 17:14:33 2020 +# Process ID: 8172 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1 +# Command line: vivado.exe -log t160_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace +# Log file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top.vdi +# Journal file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source t160_top.tcl -notrace +Command: link_design -top t160_top -part xc7k160tffg676-2 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Project 1-454] Reading design checkpoint 'd:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_uut' +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.2 +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_uut/inst' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_uut/inst' +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_uut/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57] +INFO: [Timing 38-2] Deriving generated clocks [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57] +get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1209.469 ; gain = 571.266 +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_uut/inst' +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.469 ; gain = 918.840 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1209.469 ; gain = 0.000 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 595f03c7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1226.684 ; gain = 17.215 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: a051a4aa + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: a051a4aa + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 7926d846 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 4 cells and removed 4 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: bb35cfad + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.071 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 166adf6af + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 14616ccb6 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.101 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1226.684 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1f236a5c2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.107 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1f236a5c2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 1f236a5c2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx +Command: report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1226.684 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 10a941337 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1226.684 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17841d01d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 23c507a61 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 23c507a61 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1226.684 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 23c507a61 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 259762b91 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 2.2 Physical Synthesis In Placer +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------- +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +----------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.2 Physical Synthesis In Placer | Checksum: 1a6481c74 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1226.684 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 239574972 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 239574972 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18e01976c + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 21128bd03 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 16a808333 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1dfe407d1 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 19eb30d16 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 19eb30d16 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 19eb30d16 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1226.684 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 14919c2a9 + +Phase 4.1.1.1 BUFG Insertion +INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. +Phase 4.1.1.1 BUFG Insertion | Checksum: 14919c2a9 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 +INFO: [Place 30-746] Post Placement Timing Summary WNS=7.318. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: 172a02f26 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 +Phase 4.1 Post Commit Optimization | Checksum: 172a02f26 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 172a02f26 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 172a02f26 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1d643fa80 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d643fa80 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 +Ending Placer Task | Checksum: 15c878133 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1231.637 ; gain = 4.953 +INFO: [Common 17-83] Releasing license: Implementation +49 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 1237.238 ; gain = 5.602 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file t160_top_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.068 . Memory (MB): peak = 1237.238 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file t160_top_utilization_placed.rpt -pb t160_top_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 1237.238 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file t160_top_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1237.238 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 7358067c ConstDB: 0 ShapeSum: e92f7ab7 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: d4650f61 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:18 . Memory (MB): peak = 1421.711 ; gain = 184.473 +Post Restoration Checksum: NetGraph: 2c2f3835 NumContArr: a835d72c Constraints: 0 Timing: 0 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: d4650f61 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:18 . Memory (MB): peak = 1421.711 ; gain = 184.473 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: d4650f61 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:18 . Memory (MB): peak = 1426.320 ; gain = 189.082 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: d4650f61 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:18 . Memory (MB): peak = 1426.320 ; gain = 189.082 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: 1d5345b0a + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.320 | TNS=0.000 | WHS=-0.122 | THS=-12.104| + +Phase 2 Router Initialization | Checksum: 25cc314a8 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 21b1e8b71 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 28 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.216 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 283fe09fb + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +Phase 4 Rip-up And Reroute | Checksum: 283fe09fb + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: 283fe09fb + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 283fe09fb + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +Phase 5 Delay and Skew Optimization | Checksum: 283fe09fb + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 28f70be37 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.301 | TNS=0.000 | WHS=0.086 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 28f70be37 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +Phase 6 Post Hold Fix | Checksum: 28f70be37 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0425121 % + Global Horizontal Routing Utilization = 0.0411338 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: 28f70be37 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 28f70be37 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 1c7888497 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=7.301 | TNS=0.000 | WHS=0.086 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: 1c7888497 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1444.344 ; gain = 207.105 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:20 . Memory (MB): peak = 1444.344 ; gain = 207.105 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.080 . Memory (MB): peak = 1444.344 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx +Command: report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx +Command: report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx +Command: report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +78 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file t160_top_route_status.rpt -pb t160_top_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file t160_top_timing_summary_routed.rpt -pb t160_top_timing_summary_routed.pb -rpx t160_top_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [runtcl-4] Executing : report_incremental_reuse -file t160_top_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file t160_top_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file t160_top_bus_skew_routed.rpt -pb t160_top_bus_skew_routed.pb -rpx t160_top_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force t160_top.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./t160_top.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +96 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1894.738 ; gain = 432.953 +INFO: [Common 17-206] Exiting Vivado at Sun Jun 28 17:15:57 2020... diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_bus_skew_routed.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_bus_skew_routed.pb new file mode 100644 index 0000000..3390588 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_bus_skew_routed.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_bus_skew_routed.rpt b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_bus_skew_routed.rpt new file mode 100644 index 0000000..8cac298 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_bus_skew_routed.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:15:36 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_bus_skew -warn_on_violation -file t160_top_bus_skew_routed.rpt -pb t160_top_bus_skew_routed.pb -rpx t160_top_bus_skew_routed.rpx +| Design : t160_top +| Device : 7k160t-ffg676 +| Speed File : -2 PRODUCTION 1.12 2017-02-17 +--------------------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_bus_skew_routed.rpx b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_bus_skew_routed.rpx new file mode 100644 index 0000000..7f274f1 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_bus_skew_routed.rpx differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_clock_utilization_routed.rpt b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_clock_utilization_routed.rpt new file mode 100644 index 0000000..3628fbc --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_clock_utilization_routed.rpt @@ -0,0 +1,234 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:15:36 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_clock_utilization -file t160_top_clock_utilization_routed.rpt +| Design : t160_top +| Device : 7k160t-ffg676 +| Speed File : -2 PRODUCTION 1.12 2017-02-17 +-------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Device Cell Placement Summary for Global Clock g1 +8. Device Cell Placement Summary for Global Clock g2 +9. Clock Region Cell Placement per Global Clock: Region X1Y1 +10. Clock Region Cell Placement per Global Clock: Region X0Y2 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 3 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 120 | 0 | 0 | 0 | +| BUFIO | 0 | 32 | 0 | 0 | 0 | +| BUFMR | 0 | 16 | 0 | 0 | 0 | +| BUFR | 0 | 32 | 0 | 0 | 0 | +| MMCM | 1 | 8 | 0 | 0 | 0 | +| PLL | 0 | 8 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+----------------------------+-------------------------------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+----------------------------+-------------------------------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 391 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_uut/inst/clkout1_buf/O | clk_uut/inst/clk_out1 | +| g1 | src0 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | 1 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | clk_uut/inst/clkf_buf/O | clk_uut/inst/clkfbout_buf_clk_wiz_0 | +| g2 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 0 | 389 | n/a | n/a | BUFG_inst/O | rst | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+----------------------------+-------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-------------------------------------+---------------------------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-------------------------------------+---------------------------------+ +| src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X1Y1 | X1Y1 | 1 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_uut/inst/mmcm_adv_inst/CLKOUT0 | clk_uut/inst/clk_out1_clk_wiz_0 | +| src0 | g1 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X1Y1 | X1Y1 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | clk_uut/inst/mmcm_adv_inst/CLKFBOUT | clk_uut/inst/clkfbout_clk_wiz_0 | +| src1 | g2 | LUT1/O | None | SLICE_X56Y139 | X1Y2 | 1 | 0 | | | BUFG_inst_i_1_lopt_replica/O | O_replN | ++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-------------------------------------+---------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y2 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 391 | 2200 | 191 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 | +| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y4 | 0 | 0 | +| Y3 | 0 | 0 | +| Y2 | 2 | 0 | +| Y1 | 0 | 1 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+ +| g0 | BUFG/O | n/a | clk_out1_clk_wiz_0 | 10.000 | {0.000 5.000} | 391 | 0 | 0 | 0 | clk_uut/inst/clk_out1 | ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+------+----+ +| | X0 | X1 | ++----+------+----+ +| Y4 | 0 | 0 | +| Y3 | 0 | 0 | +| Y2 | 391 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+------+----+ + + +7. Device Cell Placement Summary for Global Clock g1 +---------------------------------------------------- + ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------+ +| g1 | BUFG/O | n/a | clkfbout_clk_wiz_0 | 10.000 | {0.000 5.000} | 0 | 0 | 1 | 0 | clk_uut/inst/clkfbout_buf_clk_wiz_0 | ++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y4 | 0 | 0 | +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 0 | 1 | +| Y0 | 0 | 0 | ++----+----+----+ + + +8. Device Cell Placement Summary for Global Clock g2 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----+ +| g2 | BUFG/O | n/a | | | | 389 | 0 | 0 | 0 | rst | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+------+----+ +| | X0 | X1 | ++----+------+----+ +| Y4 | 0 | 0 | +| Y3 | 0 | 0 | +| Y2 | 389 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+------+----+ + + +9. Clock Region Cell Placement per Global Clock: Region X1Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------------+ +| g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | clk_uut/inst/clkfbout_buf_clk_wiz_0 | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +10. Clock Region Cell Placement per Global Clock: Region X0Y2 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------+ +| g0 | n/a | BUFG/O | None | 391 | 0 | 391 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_uut/inst/clk_out1 | +| g2 | n/a | BUFG/O | None | 0 | 389 | 389 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | rst | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y1 [get_cells BUFG_inst] +set_property LOC BUFGCTRL_X0Y2 [get_cells clk_uut/inst/clkf_buf] +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_uut/inst/clkout1_buf] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y71 [get_ports sys_clkn] +set_property LOC IOB_X1Y72 [get_ports sys_clkp] + +# Clock net "rst" driven by instance "BUFG_inst" located at site "BUFGCTRL_X0Y1" +#startgroup +create_pblock {CLKAG_rst} +add_cells_to_pblock [get_pblocks {CLKAG_rst}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="rst"}]]] +resize_pblock [get_pblocks {CLKAG_rst}] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2} +#endgroup + +# Clock net "clk_uut/inst/clk_out1" driven by instance "clk_uut/inst/clkout1_buf" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_uut/inst/clk_out1} +add_cells_to_pblock [get_pblocks {CLKAG_clk_uut/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_uut/inst/clk_out1"}]]] +resize_pblock [get_pblocks {CLKAG_clk_uut/inst/clk_out1}] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2} +#endgroup diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_control_sets_placed.rpt b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_control_sets_placed.rpt new file mode 100644 index 0000000..1bc5d9f --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_control_sets_placed.rpt @@ -0,0 +1,77 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:15:08 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_control_sets -verbose -file t160_top_control_sets_placed.rpt +| Design : t160_top +| Device : xc7k160t +------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 12 | +| Unused register locations in slices containing registers | 10 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 4 | 1 | +| 16+ | 11 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 98 | 30 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 4 | 1 | +| Yes | No | Yes | 680 | 87 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++------------------------+-------------------------------------------------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++------------------------+-------------------------------------------------------+------------------+------------------+----------------+ +| clk_uut/inst/clk_out1 | xjtag_bus_uut/Mmux_GND_1_o_ishift_data[71]_MUX_49_o11 | | 1 | 4 | +| clk_uut/inst/clk_out1 | xjtag_bus_uut/_n0186_inv | rst | 2 | 16 | +| clk_uut/inst/clk_out1 | xjtag_bus_uut/_n0173_inv | rst | 14 | 64 | +| clk_uut/inst/clk_out1 | xjtag_bus_uut/_n0177_inv | rst | 9 | 64 | +| clk_uut/inst/clk_out1 | xjtag_bus_uut/ird_valid_icmd_rd[1]_AND_11_o | rst | 12 | 64 | +| clk_uut/inst/clk_out1 | xjtag_bus_uut/localbus_rvalid | rst | 13 | 64 | +| clk_uut/inst/clk_out1 | xjtag_bus_uut/_n0181_inv | rst | 5 | 64 | +| clk_uut/inst/clk_out1 | UUT/ram0_1 | rst | 5 | 64 | +| clk_uut/inst/clk_out1 | UUT/ram1_0 | rst | 6 | 64 | +| clk_uut/inst/clk_out1 | UUT/gpio0[31]_i_1_n_0 | rst | 6 | 72 | +| clk_uut/inst/clk_out1 | | rst | 30 | 98 | +| clk_uut/inst/clk_out1 | xjtag_bus_uut/dop_clk_r[2]_dop_clk_r[1]_AND_3_o | rst | 15 | 144 | ++------------------------+-------------------------------------------------------+------------------+------------------+----------------+ + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_opted.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_opted.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_opted.rpt b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_opted.rpt new file mode 100644 index 0000000..9960427 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:15:03 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_drc -file t160_top_drc_opted.rpt -pb t160_top_drc_opted.pb -rpx t160_top_drc_opted.rpx +| Design : t160_top +| Device : xc7k160tffg676-2 +| Speed File : -2 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_opted.rpx b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_opted.rpx new file mode 100644 index 0000000..32ed0fe Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_opted.rpx differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_routed.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_routed.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_routed.rpt b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_routed.rpt new file mode 100644 index 0000000..aa055c5 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:15:30 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_drc -file t160_top_drc_routed.rpt -pb t160_top_drc_routed.pb -rpx t160_top_drc_routed.rpx +| Design : t160_top +| Device : xc7k160tffg676-2 +| Speed File : -2 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_routed.rpx b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_routed.rpx new file mode 100644 index 0000000..d208473 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_drc_routed.rpx differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_io_placed.rpt b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_io_placed.rpt new file mode 100644 index 0000000..d47393b --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_io_placed.rpt @@ -0,0 +1,718 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:15:08 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_io -file t160_top_io_placed.rpt +| Design : t160_top +| Device : xc7k160t +| Speed File : -2 +| Package : ffg676 +| Package Version : FINAL 2012-06-26 +| Package Pin Delay Version : VERS. 2.0 2012-06-26 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 6 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | | MGTXTXN3_116 | Gigabit | | | | | | | | | | | | | | | | +| A4 | | | MGTXTXP3_116 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| A12 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A13 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A17 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A18 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A19 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A20 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| A21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| A22 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| A23 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| A24 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| A25 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| A26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AA2 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA5 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA7 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA8 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA9 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA10 | sys_clkp | High Performance | IO_L14P_T2_SRCC_33 | INPUT | DIFF_SSTL15 | 33 | | | | NONE | | FIXED | | | | NONE | | | | +| AA11 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AA12 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA13 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA14 | | High Performance | IO_L7P_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA15 | | High Performance | IO_L7N_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA17 | | High Performance | IO_L11P_T1_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA18 | | High Performance | IO_L11N_T1_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA19 | | High Performance | IO_L16P_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA20 | | High Performance | IO_L16N_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AA21 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| AA22 | | High Range | IO_L13N_T2_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA23 | | High Range | IO_L11P_T1_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA24 | | High Range | IO_L12N_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA25 | | High Range | IO_L7P_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| AA26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB2 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB4 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB5 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB6 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB8 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AB9 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB10 | sys_clkn | High Performance | IO_L14N_T2_SRCC_33 | INPUT | DIFF_SSTL15 | 33 | | | | NONE | | FIXED | | | | NONE | | | | +| AB11 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB12 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB14 | | High Performance | IO_L10P_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB15 | | High Performance | IO_L10N_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB16 | | High Performance | IO_L12P_T1_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB17 | | High Performance | IO_L14P_T2_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB18 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AB19 | | High Performance | IO_L18P_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB20 | | High Performance | IO_L18N_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AB21 | | High Range | IO_L18P_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB22 | | High Range | IO_L17P_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB24 | | High Range | IO_L11N_T1_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB25 | | High Range | IO_L7N_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| AB26 | | High Range | IO_L9P_T1_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC1 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC2 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC3 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AC6 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AC7 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC9 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AC11 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC12 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC13 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AC14 | | High Performance | IO_L8P_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC15 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AC16 | | High Performance | IO_L12N_T1_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC17 | | High Performance | IO_L14N_T2_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC18 | | High Performance | IO_L13P_T2_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC19 | | High Performance | IO_L17P_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AC20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AC21 | | High Range | IO_L18N_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC22 | | High Range | IO_L17N_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC23 | | High Range | IO_L14P_T2_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC24 | | High Range | IO_L14N_T2_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| AC25 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| AC26 | | High Range | IO_L9N_T1_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AD3 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD4 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD6 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AD7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AD8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD9 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD10 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD11 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AD13 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| AD14 | | High Performance | IO_L8N_T1_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD15 | | High Performance | IO_L4P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD16 | | High Performance | IO_L6P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AD18 | | High Performance | IO_L13N_T2_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD19 | | High Performance | IO_L17N_T2_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD20 | | High Performance | IO_L15P_T2_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AD21 | | High Range | IO_L19P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD22 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| AD23 | | High Range | IO_L16P_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD24 | | High Range | IO_L16N_T2_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD25 | | High Range | IO_L23P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AD26 | | High Range | IO_L21P_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE2 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE3 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AE5 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE6 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AE7 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE8 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AE10 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE11 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE12 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AE14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AE15 | | High Performance | IO_L4N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE16 | | High Performance | IO_L6N_T0_VREF_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE17 | | High Performance | IO_L1P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE18 | | High Performance | IO_L3P_T0_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE19 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AE20 | | High Performance | IO_L15N_T2_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AE21 | | High Range | IO_L19N_T3_VREF_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE22 | | High Range | IO_L24P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE23 | | High Range | IO_L22P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AE25 | | High Range | IO_L23N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AE26 | | High Range | IO_L21N_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AF2 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF3 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF4 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF5 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AF6 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AF7 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF8 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF9 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF10 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AF12 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF13 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AF14 | | High Performance | IO_L2P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF15 | | High Performance | IO_L2N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF16 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| AF17 | | High Performance | IO_L1N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF18 | | High Performance | IO_L3N_T0_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF19 | | High Performance | IO_L5P_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF20 | | High Performance | IO_L5N_T0_32 | User IO | | 32 | | | | | | | | | | | | | | +| AF21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AF22 | | High Range | IO_L24N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF23 | | High Range | IO_L22N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF24 | | High Range | IO_L20P_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF25 | | High Range | IO_L20N_T3_12 | User IO | | 12 | | | | | | | | | | | | | | +| AF26 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| B1 | | | MGTXTXN2_116 | Gigabit | | | | | | | | | | | | | | | | +| B2 | | | MGTXTXP2_116 | Gigabit | | | | | | | | | | | | | | | | +| B3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B5 | | | MGTXRXN3_116 | Gigabit | | | | | | | | | | | | | | | | +| B6 | | | MGTXRXP3_116 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B9 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B11 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B14 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| B15 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| B19 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B20 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| B21 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| B22 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| B23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B24 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| B25 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| B26 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C3 | | | MGTXRXN2_116 | Gigabit | | | | | | | | | | | | | | | | +| C4 | | | MGTXRXP2_116 | Gigabit | | | | | | | | | | | | | | | | +| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C8 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| C9 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C13 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| C14 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| C15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C16 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C19 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| C22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| C23 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| C24 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| C25 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| C26 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| D1 | | | MGTXTXN1_116 | Gigabit | | | | | | | | | | | | | | | | +| D2 | | | MGTXTXP1_116 | Gigabit | | | | | | | | | | | | | | | | +| D3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTREFCLK0N_116 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTREFCLK0P_116 | Gigabit | | | | | | | | | | | | | | | | +| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D8 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| D13 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D19 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| D21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| D22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| D23 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| D24 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| D25 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| D26 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E3 | | | MGTXRXN1_116 | Gigabit | | | | | | | | | | | | | | | | +| E4 | | | MGTXRXP1_116 | Gigabit | | | | | | | | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| E10 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E11 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E12 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| E20 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| E21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| E22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| E23 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| E24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E25 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| E26 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| F1 | | | MGTXTXN0_116 | Gigabit | | | | | | | | | | | | | | | | +| F2 | | | MGTXTXP0_116 | Gigabit | | | | | | | | | | | | | | | | +| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F5 | | | MGTREFCLK1N_116 | Gigabit | | | | | | | | | | | | | | | | +| F6 | | | MGTREFCLK1P_116 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| F9 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F13 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| F17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F18 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F19 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| F21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F22 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| F23 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| F24 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| F25 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| F26 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| G3 | | | MGTXRXN0_116 | Gigabit | | | | | | | | | | | | | | | | +| G4 | | | MGTXRXP0_116 | Gigabit | | | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| G7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| G10 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| G11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| G12 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G14 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| G15 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G16 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G19 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| G20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G21 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| G22 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| G23 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| G24 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| G25 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| G26 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| H1 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| H2 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| H3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | | +| H6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H9 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| H11 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| H12 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H13 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| H15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H16 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| H21 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| H22 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| H23 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| H24 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| H25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H26 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J3 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| J4 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| J5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| J7 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| J8 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| J11 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| J14 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| J17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| J19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| J21 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| J22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J23 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| J24 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| J25 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| J26 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| K1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| K2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| K3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | | +| K6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K15 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| K19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K20 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| K21 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| K22 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| K23 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| K24 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| K25 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| K26 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| L1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| L3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| L4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| L5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| L7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| L8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L17 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| L18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| L19 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| L21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L22 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| L23 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| L24 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| L25 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| L26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| M2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| M3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| M4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M5 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | | +| M6 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| M12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| M18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| M19 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| M20 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M21 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M22 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M24 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| M25 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| M26 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| N1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| N4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| N5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N6 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | | +| N7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N8 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| N12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N16 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| N20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N21 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| N22 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| N23 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| N24 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| N25 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| N26 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| P1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| P2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P16 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P18 | | High Range | IO_L24N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| P19 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| P20 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| P21 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| P22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| P23 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| P24 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| P25 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| P26 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| R1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| R4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| R5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| R7 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| R12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R16 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| R17 | led[0] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R18 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| R19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| R20 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| R21 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| R22 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| R23 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| R24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R25 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| R26 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| T1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T2 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T5 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| T6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| T7 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | | +| T8 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | | +| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T12 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| T17 | led[1] | High Range | IO_L23N_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T18 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| T19 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| T20 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T22 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T23 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T24 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T25 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T26 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | | +| U1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| U4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U9 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| U12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| U16 | led[2] | High Range | IO_25_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U17 | led[3] | High Range | IO_L23P_T3_13 | OUTPUT | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U19 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| U20 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| U21 | | High Range | IO_0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U22 | | High Range | IO_L1P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U23 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| U24 | | High Range | IO_L2P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U25 | | High Range | IO_L2N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| U26 | | High Range | IO_L4P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| V1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V6 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V9 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| V11 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| V12 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | | +| V13 | | High Performance | IO_0_VRN_32 | User IO | | 32 | | | | | | | | | | | | | | +| V14 | | High Performance | IO_L24P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V16 | | High Performance | IO_L20P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V17 | | High Performance | IO_L20N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V18 | | High Performance | IO_L23P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V19 | | High Performance | IO_L23N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| V20 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| V21 | | High Range | IO_L6P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| V22 | | High Range | IO_L1N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| V23 | | High Range | IO_L3P_T0_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| V24 | | High Range | IO_L3N_T0_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| V25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V26 | | High Range | IO_L4N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| W1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W3 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| W8 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | +| W9 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| W10 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| W11 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W13 | | High Performance | IO_25_VRP_32 | User IO | | 32 | | | | | | | | | | | | | | +| W14 | | High Performance | IO_L24N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| W15 | | High Performance | IO_L22P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| W16 | | High Performance | IO_L22N_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| W17 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| W18 | | High Performance | IO_L21P_T3_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| W19 | | High Performance | IO_L21N_T3_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L15P_T2_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| W21 | | High Range | IO_L6N_T0_VREF_12 | User IO | | 12 | | | | | | | | | | | | | | +| W22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W23 | | High Range | IO_L8P_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| W24 | | High Range | IO_L8N_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| W25 | | High Range | IO_L5P_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| W26 | | High Range | IO_L5N_T0_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y3 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| Y5 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y6 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y7 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y8 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y10 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y11 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y12 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y13 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y14 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | | +| Y15 | | High Performance | IO_L9P_T1_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y16 | | High Performance | IO_L9N_T1_DQS_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y17 | | High Performance | IO_L19P_T3_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y18 | | High Performance | IO_L19N_T3_VREF_32 | User IO | | 32 | | | | | | | | | | | | | | +| Y19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y20 | | High Range | IO_25_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y21 | | High Range | IO_L15N_T2_DQS_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y22 | | High Range | IO_L13P_T2_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y23 | | High Range | IO_L12P_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y24 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | | +| Y25 | | High Range | IO_L10P_T1_12 | User IO | | 12 | | | | | | | | | | | | | | +| Y26 | | High Range | IO_L10N_T1_12 | User IO | | 12 | | | | | | | | | | | | | | ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_methodology_drc_routed.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_methodology_drc_routed.pb new file mode 100644 index 0000000..0d6626b Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_methodology_drc_routed.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpt b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpt new file mode 100644 index 0000000..1232c3d --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpt @@ -0,0 +1,55 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:15:31 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_methodology -file t160_top_methodology_drc_routed.rpt -pb t160_top_methodology_drc_routed.pb -rpx t160_top_methodology_drc_routed.rpx +| Design : t160_top +| Device : xc7k160tffg676-2 +| Speed File : -2 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 4 ++-----------+----------+-------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-------------------------------+------------+ +| TIMING-18 | Warning | Missing input or output delay | 4 | ++-----------+----------+-------------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-18#1 Warning +Missing input or output delay +An output delay is missing on led[0] relative to clock(s) sys_clkp +Related violations: + +TIMING-18#2 Warning +Missing input or output delay +An output delay is missing on led[1] relative to clock(s) sys_clkp +Related violations: + +TIMING-18#3 Warning +Missing input or output delay +An output delay is missing on led[2] relative to clock(s) sys_clkp +Related violations: + +TIMING-18#4 Warning +Missing input or output delay +An output delay is missing on led[3] relative to clock(s) sys_clkp +Related violations: + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpx b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpx new file mode 100644 index 0000000..f94d078 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_methodology_drc_routed.rpx differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_opt.dcp b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_opt.dcp new file mode 100644 index 0000000..defc86d Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_opt.dcp differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_placed.dcp b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_placed.dcp new file mode 100644 index 0000000..04a0599 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_placed.dcp differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_power_routed.rpt b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_power_routed.rpt new file mode 100644 index 0000000..04973e5 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_power_routed.rpt @@ -0,0 +1,155 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:15:32 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_power -file t160_top_power_routed.rpt -pb t160_top_power_summary_routed.pb -rpx t160_top_power_routed.rpx +| Design : t160_top +| Device : xc7k160tffg676-2 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.226 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.112 | +| Device Static (W) | 0.113 | +| Effective TJA (C/W) | 1.9 | +| Max Ambient (C) | 84.6 | +| Junction Temperature (C) | 25.4 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.002 | 5 | --- | --- | +| Slice Logic | <0.001 | 713 | --- | --- | +| LUT as Logic | <0.001 | 295 | 101400 | 0.29 | +| Register | <0.001 | 391 | 202800 | 0.19 | +| CARRY4 | <0.001 | 2 | 25350 | <0.01 | +| BUFG | 0.000 | 1 | 32 | 3.13 | +| Others | 0.000 | 8 | --- | --- | +| Signals | <0.001 | 531 | --- | --- | +| MMCM | 0.106 | 1 | 8 | 12.50 | +| I/O | 0.004 | 6 | 400 | 1.50 | +| Static Power | 0.113 | | | | +| Total | 0.226 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.044 | 0.004 | 0.041 | +| Vccaux | 1.800 | 0.078 | 0.060 | 0.018 | +| Vcco33 | 3.300 | 0.001 | 0.000 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | High | User specified more than 95% of inputs | | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 1.9 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 3.4 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++--------------------+---------------------------------+-----------------+ +| Clock | Domain | Constraint (ns) | ++--------------------+---------------------------------+-----------------+ +| clk_out1_clk_wiz_0 | clk_uut/inst/clk_out1_clk_wiz_0 | 10.0 | +| clkfbout_clk_wiz_0 | clk_uut/inst/clkfbout_clk_wiz_0 | 10.0 | +| sys_clkp | sys_clkp | 10.0 | ++--------------------+---------------------------------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-----------------+-----------+ +| Name | Power (W) | ++-----------------+-----------+ +| t160_top | 0.112 | +| UUT | <0.001 | +| clk_uut | 0.110 | +| inst | 0.110 | +| xjtag_bus_uut | 0.001 | ++-----------------+-----------+ + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_power_routed.rpx b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_power_routed.rpx new file mode 100644 index 0000000..97bf6d2 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_power_routed.rpx differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_power_summary_routed.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_power_summary_routed.pb new file mode 100644 index 0000000..5ba39b7 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_power_summary_routed.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_route_status.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_route_status.pb new file mode 100644 index 0000000..bbe196d Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_route_status.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_route_status.rpt b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_route_status.rpt new file mode 100644 index 0000000..ed9caed --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 741 : + # of nets not needing routing.......... : 202 : + # of internally routed nets........ : 202 : + # of routable nets..................... : 539 : + # of fully routed nets............. : 539 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_routed.dcp b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_routed.dcp new file mode 100644 index 0000000..7cb7354 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_routed.dcp differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_timing_summary_routed.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_timing_summary_routed.pb new file mode 100644 index 0000000..adb32d6 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_timing_summary_routed.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_timing_summary_routed.rpt b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_timing_summary_routed.rpt new file mode 100644 index 0000000..636742a --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_timing_summary_routed.rpt @@ -0,0 +1,1515 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:15:32 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_timing_summary -max_paths 10 -file t160_top_timing_summary_routed.rpt -pb t160_top_timing_summary_routed.pb -rpx t160_top_timing_summary_routed.rpx -warn_on_violation +| Design : t160_top +| Device : 7k160t-ffg676 +| Speed File : -2 PRODUCTION 1.12 2017-02-17 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 4 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 7.304 0.000 0 730 0.092 0.000 0 730 3.000 0.000 0 397 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +sys_clkp {0.000 5.000} 10.000 100.000 + clk_out1_clk_wiz_0 {0.000 5.000} 10.000 100.000 + clkfbout_clk_wiz_0 {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +sys_clkp 3.000 0.000 0 1 + clk_out1_clk_wiz_0 7.304 0.000 0 730 0.092 0.000 0 730 4.600 0.000 0 393 + clkfbout_clk_wiz_0 8.592 0.000 0 3 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_clkp + To Clock: sys_clkp + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_clkp +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { sys_clkp } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.071 10.000 8.929 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 +Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 +High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_out1_clk_wiz_0 + To Clock: clk_out1_clk_wiz_0 + +Setup : 0 Failing Endpoints, Worst Slack 7.304ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.092ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 4.600ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 7.304ns (required time - arrival time) + Source: xjtag_bus_uut/icmd_rd_1/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/oshift_14/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.643ns (logic 0.309ns (11.692%) route 2.334ns (88.308%)) + Logic Levels: 2 (LUT5=1 LUT6=1) + Clock Path Skew: -0.044ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.630ns = ( 8.370 - 10.000 ) + Source Clock Delay (SCD): -2.199ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.131ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.231 -2.199 xjtag_bus_uut/clk + SLICE_X39Y137 FDRE r xjtag_bus_uut/icmd_rd_1/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y137 FDRE (Prop_fdre_C_Q) 0.223 -1.976 r xjtag_bus_uut/icmd_rd_1/Q + net (fo=36, routed) 1.909 -0.066 xjtag_bus_uut/icmd_rd[1] + SLICE_X43Y145 LUT5 (Prop_lut5_I4_O) 0.043 -0.023 r xjtag_bus_uut/oshift_14_rstpot_SW1/O + net (fo=1, routed) 0.424 0.401 xjtag_bus_uut/N53 + SLICE_X46Y145 LUT6 (Prop_lut6_I3_O) 0.043 0.444 r xjtag_bus_uut/oshift_14_rstpot/O + net (fo=1, routed) 0.000 0.444 xjtag_bus_uut/oshift_14_rstpot + SLICE_X46Y145 FDCE r xjtag_bus_uut/oshift_14/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.101 8.370 xjtag_bus_uut/clk + SLICE_X46Y145 FDCE r xjtag_bus_uut/oshift_14/C + clock pessimism -0.612 7.757 + clock uncertainty -0.074 7.683 + SLICE_X46Y145 FDCE (Setup_fdce_C_D) 0.065 7.748 xjtag_bus_uut/oshift_14 + ------------------------------------------------------------------- + required time 7.748 + arrival time -0.444 + ------------------------------------------------------------------- + slack 7.304 + +Slack (MET) : 7.357ns (required time - arrival time) + Source: xjtag_bus_uut/dop_clk_r_1/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/oshift_18/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.558ns (logic 0.345ns (13.488%) route 2.213ns (86.512%)) + Logic Levels: 2 (LUT3=1 LUT6=1) + Clock Path Skew: -0.044ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.631ns = ( 8.369 - 10.000 ) + Source Clock Delay (SCD): -2.200ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.131ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.230 -2.200 xjtag_bus_uut/clk + SLICE_X38Y136 FDCE r xjtag_bus_uut/dop_clk_r_1/C + ------------------------------------------------------------------- ------------------- + SLICE_X38Y136 FDCE (Prop_fdce_C_Q) 0.259 -1.941 r xjtag_bus_uut/dop_clk_r_1/Q + net (fo=38, routed) 1.584 -0.357 xjtag_bus_uut/dop_clk_r[1] + SLICE_X46Y142 LUT3 (Prop_lut3_I2_O) 0.043 -0.314 r xjtag_bus_uut/oshift_18_rstpot_SW0/O + net (fo=1, routed) 0.629 0.315 xjtag_bus_uut/N64 + SLICE_X45Y142 LUT6 (Prop_lut6_I2_O) 0.043 0.358 r xjtag_bus_uut/oshift_18_rstpot/O + net (fo=1, routed) 0.000 0.358 xjtag_bus_uut/oshift_18_rstpot + SLICE_X45Y142 FDCE r xjtag_bus_uut/oshift_18/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.100 8.369 xjtag_bus_uut/clk + SLICE_X45Y142 FDCE r xjtag_bus_uut/oshift_18/C + clock pessimism -0.612 7.756 + clock uncertainty -0.074 7.682 + SLICE_X45Y142 FDCE (Setup_fdce_C_D) 0.033 7.715 xjtag_bus_uut/oshift_18 + ------------------------------------------------------------------- + required time 7.715 + arrival time -0.358 + ------------------------------------------------------------------- + slack 7.357 + +Slack (MET) : 7.366ns (required time - arrival time) + Source: xjtag_bus_uut/localbus_waddr_10/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: UUT/ram1_reg[1]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.313ns (logic 0.388ns (16.775%) route 1.925ns (83.225%)) + Logic Levels: 3 (LUT4=1 LUT6=2) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.629ns = ( 8.371 - 10.000 ) + Source Clock Delay (SCD): -2.196ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.131ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.234 -2.196 xjtag_bus_uut/clk + SLICE_X42Y147 FDCE r xjtag_bus_uut/localbus_waddr_10/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y147 FDCE (Prop_fdce_C_Q) 0.259 -1.937 f xjtag_bus_uut/localbus_waddr_10/Q + net (fo=1, routed) 0.466 -1.471 UUT/localbus_waddr[10] + SLICE_X42Y147 LUT4 (Prop_lut4_I1_O) 0.043 -1.428 f UUT/gpio0[31]_i_4/O + net (fo=1, routed) 0.380 -1.048 UUT/gpio0[31]_i_4_n_0 + SLICE_X43Y139 LUT6 (Prop_lut6_I0_O) 0.043 -1.005 f UUT/gpio0[31]_i_2/O + net (fo=3, routed) 0.607 -0.398 UUT/gpio0[31]_i_2_n_0 + SLICE_X40Y146 LUT6 (Prop_lut6_I4_O) 0.043 -0.355 r UUT/ram1[31]_i_1/O + net (fo=32, routed) 0.472 0.117 UUT/ram1_0 + SLICE_X39Y141 FDCE r UUT/ram1_reg[1]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.102 8.371 UUT/CLK + SLICE_X39Y141 FDCE r UUT/ram1_reg[1]/C + clock pessimism -0.612 7.758 + clock uncertainty -0.074 7.684 + SLICE_X39Y141 FDCE (Setup_fdce_C_CE) -0.201 7.483 UUT/ram1_reg[1] + ------------------------------------------------------------------- + required time 7.483 + arrival time -0.117 + ------------------------------------------------------------------- + slack 7.366 + +Slack (MET) : 7.366ns (required time - arrival time) + Source: xjtag_bus_uut/localbus_waddr_10/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: UUT/ram1_reg[27]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.313ns (logic 0.388ns (16.775%) route 1.925ns (83.225%)) + Logic Levels: 3 (LUT4=1 LUT6=2) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.629ns = ( 8.371 - 10.000 ) + Source Clock Delay (SCD): -2.196ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.131ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.234 -2.196 xjtag_bus_uut/clk + SLICE_X42Y147 FDCE r xjtag_bus_uut/localbus_waddr_10/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y147 FDCE (Prop_fdce_C_Q) 0.259 -1.937 f xjtag_bus_uut/localbus_waddr_10/Q + net (fo=1, routed) 0.466 -1.471 UUT/localbus_waddr[10] + SLICE_X42Y147 LUT4 (Prop_lut4_I1_O) 0.043 -1.428 f UUT/gpio0[31]_i_4/O + net (fo=1, routed) 0.380 -1.048 UUT/gpio0[31]_i_4_n_0 + SLICE_X43Y139 LUT6 (Prop_lut6_I0_O) 0.043 -1.005 f UUT/gpio0[31]_i_2/O + net (fo=3, routed) 0.607 -0.398 UUT/gpio0[31]_i_2_n_0 + SLICE_X40Y146 LUT6 (Prop_lut6_I4_O) 0.043 -0.355 r UUT/ram1[31]_i_1/O + net (fo=32, routed) 0.472 0.117 UUT/ram1_0 + SLICE_X39Y141 FDCE r UUT/ram1_reg[27]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.102 8.371 UUT/CLK + SLICE_X39Y141 FDCE r UUT/ram1_reg[27]/C + clock pessimism -0.612 7.758 + clock uncertainty -0.074 7.684 + SLICE_X39Y141 FDCE (Setup_fdce_C_CE) -0.201 7.483 UUT/ram1_reg[27] + ------------------------------------------------------------------- + required time 7.483 + arrival time -0.117 + ------------------------------------------------------------------- + slack 7.366 + +Slack (MET) : 7.366ns (required time - arrival time) + Source: xjtag_bus_uut/localbus_waddr_10/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: UUT/ram1_reg[28]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.313ns (logic 0.388ns (16.775%) route 1.925ns (83.225%)) + Logic Levels: 3 (LUT4=1 LUT6=2) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.629ns = ( 8.371 - 10.000 ) + Source Clock Delay (SCD): -2.196ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.131ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.234 -2.196 xjtag_bus_uut/clk + SLICE_X42Y147 FDCE r xjtag_bus_uut/localbus_waddr_10/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y147 FDCE (Prop_fdce_C_Q) 0.259 -1.937 f xjtag_bus_uut/localbus_waddr_10/Q + net (fo=1, routed) 0.466 -1.471 UUT/localbus_waddr[10] + SLICE_X42Y147 LUT4 (Prop_lut4_I1_O) 0.043 -1.428 f UUT/gpio0[31]_i_4/O + net (fo=1, routed) 0.380 -1.048 UUT/gpio0[31]_i_4_n_0 + SLICE_X43Y139 LUT6 (Prop_lut6_I0_O) 0.043 -1.005 f UUT/gpio0[31]_i_2/O + net (fo=3, routed) 0.607 -0.398 UUT/gpio0[31]_i_2_n_0 + SLICE_X40Y146 LUT6 (Prop_lut6_I4_O) 0.043 -0.355 r UUT/ram1[31]_i_1/O + net (fo=32, routed) 0.472 0.117 UUT/ram1_0 + SLICE_X39Y141 FDCE r UUT/ram1_reg[28]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.102 8.371 UUT/CLK + SLICE_X39Y141 FDCE r UUT/ram1_reg[28]/C + clock pessimism -0.612 7.758 + clock uncertainty -0.074 7.684 + SLICE_X39Y141 FDCE (Setup_fdce_C_CE) -0.201 7.483 UUT/ram1_reg[28] + ------------------------------------------------------------------- + required time 7.483 + arrival time -0.117 + ------------------------------------------------------------------- + slack 7.366 + +Slack (MET) : 7.366ns (required time - arrival time) + Source: xjtag_bus_uut/localbus_waddr_10/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: UUT/ram1_reg[2]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.313ns (logic 0.388ns (16.775%) route 1.925ns (83.225%)) + Logic Levels: 3 (LUT4=1 LUT6=2) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.629ns = ( 8.371 - 10.000 ) + Source Clock Delay (SCD): -2.196ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.131ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.234 -2.196 xjtag_bus_uut/clk + SLICE_X42Y147 FDCE r xjtag_bus_uut/localbus_waddr_10/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y147 FDCE (Prop_fdce_C_Q) 0.259 -1.937 f xjtag_bus_uut/localbus_waddr_10/Q + net (fo=1, routed) 0.466 -1.471 UUT/localbus_waddr[10] + SLICE_X42Y147 LUT4 (Prop_lut4_I1_O) 0.043 -1.428 f UUT/gpio0[31]_i_4/O + net (fo=1, routed) 0.380 -1.048 UUT/gpio0[31]_i_4_n_0 + SLICE_X43Y139 LUT6 (Prop_lut6_I0_O) 0.043 -1.005 f UUT/gpio0[31]_i_2/O + net (fo=3, routed) 0.607 -0.398 UUT/gpio0[31]_i_2_n_0 + SLICE_X40Y146 LUT6 (Prop_lut6_I4_O) 0.043 -0.355 r UUT/ram1[31]_i_1/O + net (fo=32, routed) 0.472 0.117 UUT/ram1_0 + SLICE_X39Y141 FDCE r UUT/ram1_reg[2]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.102 8.371 UUT/CLK + SLICE_X39Y141 FDCE r UUT/ram1_reg[2]/C + clock pessimism -0.612 7.758 + clock uncertainty -0.074 7.684 + SLICE_X39Y141 FDCE (Setup_fdce_C_CE) -0.201 7.483 UUT/ram1_reg[2] + ------------------------------------------------------------------- + required time 7.483 + arrival time -0.117 + ------------------------------------------------------------------- + slack 7.366 + +Slack (MET) : 7.366ns (required time - arrival time) + Source: xjtag_bus_uut/localbus_waddr_10/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: UUT/ram1_reg[30]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.313ns (logic 0.388ns (16.775%) route 1.925ns (83.225%)) + Logic Levels: 3 (LUT4=1 LUT6=2) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.629ns = ( 8.371 - 10.000 ) + Source Clock Delay (SCD): -2.196ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.131ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.234 -2.196 xjtag_bus_uut/clk + SLICE_X42Y147 FDCE r xjtag_bus_uut/localbus_waddr_10/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y147 FDCE (Prop_fdce_C_Q) 0.259 -1.937 f xjtag_bus_uut/localbus_waddr_10/Q + net (fo=1, routed) 0.466 -1.471 UUT/localbus_waddr[10] + SLICE_X42Y147 LUT4 (Prop_lut4_I1_O) 0.043 -1.428 f UUT/gpio0[31]_i_4/O + net (fo=1, routed) 0.380 -1.048 UUT/gpio0[31]_i_4_n_0 + SLICE_X43Y139 LUT6 (Prop_lut6_I0_O) 0.043 -1.005 f UUT/gpio0[31]_i_2/O + net (fo=3, routed) 0.607 -0.398 UUT/gpio0[31]_i_2_n_0 + SLICE_X40Y146 LUT6 (Prop_lut6_I4_O) 0.043 -0.355 r UUT/ram1[31]_i_1/O + net (fo=32, routed) 0.472 0.117 UUT/ram1_0 + SLICE_X39Y141 FDCE r UUT/ram1_reg[30]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.102 8.371 UUT/CLK + SLICE_X39Y141 FDCE r UUT/ram1_reg[30]/C + clock pessimism -0.612 7.758 + clock uncertainty -0.074 7.684 + SLICE_X39Y141 FDCE (Setup_fdce_C_CE) -0.201 7.483 UUT/ram1_reg[30] + ------------------------------------------------------------------- + required time 7.483 + arrival time -0.117 + ------------------------------------------------------------------- + slack 7.366 + +Slack (MET) : 7.366ns (required time - arrival time) + Source: xjtag_bus_uut/localbus_waddr_10/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: UUT/ram1_reg[31]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.313ns (logic 0.388ns (16.775%) route 1.925ns (83.225%)) + Logic Levels: 3 (LUT4=1 LUT6=2) + Clock Path Skew: -0.046ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.629ns = ( 8.371 - 10.000 ) + Source Clock Delay (SCD): -2.196ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.131ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.234 -2.196 xjtag_bus_uut/clk + SLICE_X42Y147 FDCE r xjtag_bus_uut/localbus_waddr_10/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y147 FDCE (Prop_fdce_C_Q) 0.259 -1.937 f xjtag_bus_uut/localbus_waddr_10/Q + net (fo=1, routed) 0.466 -1.471 UUT/localbus_waddr[10] + SLICE_X42Y147 LUT4 (Prop_lut4_I1_O) 0.043 -1.428 f UUT/gpio0[31]_i_4/O + net (fo=1, routed) 0.380 -1.048 UUT/gpio0[31]_i_4_n_0 + SLICE_X43Y139 LUT6 (Prop_lut6_I0_O) 0.043 -1.005 f UUT/gpio0[31]_i_2/O + net (fo=3, routed) 0.607 -0.398 UUT/gpio0[31]_i_2_n_0 + SLICE_X40Y146 LUT6 (Prop_lut6_I4_O) 0.043 -0.355 r UUT/ram1[31]_i_1/O + net (fo=32, routed) 0.472 0.117 UUT/ram1_0 + SLICE_X39Y141 FDCE r UUT/ram1_reg[31]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.102 8.371 UUT/CLK + SLICE_X39Y141 FDCE r UUT/ram1_reg[31]/C + clock pessimism -0.612 7.758 + clock uncertainty -0.074 7.684 + SLICE_X39Y141 FDCE (Setup_fdce_C_CE) -0.201 7.483 UUT/ram1_reg[31] + ------------------------------------------------------------------- + required time 7.483 + arrival time -0.117 + ------------------------------------------------------------------- + slack 7.366 + +Slack (MET) : 7.370ns (required time - arrival time) + Source: xjtag_bus_uut/dop_clk_r_2/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/oshift_7/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.547ns (logic 0.445ns (17.473%) route 2.102ns (82.527%)) + Logic Levels: 3 (LUT4=1 LUT6=2) + Clock Path Skew: -0.043ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.627ns = ( 8.373 - 10.000 ) + Source Clock Delay (SCD): -2.197ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.131ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.233 -2.197 xjtag_bus_uut/clk + SLICE_X38Y140 FDCE r xjtag_bus_uut/dop_clk_r_2/C + ------------------------------------------------------------------- ------------------- + SLICE_X38Y140 FDCE (Prop_fdce_C_Q) 0.236 -1.961 r xjtag_bus_uut/dop_clk_r_2/Q + net (fo=41, routed) 0.514 -1.446 xjtag_bus_uut/dop_clk_r[2] + SLICE_X38Y136 LUT4 (Prop_lut4_I3_O) 0.123 -1.323 f xjtag_bus_uut/Mmux_GND_1_o_ishift_data[71]_MUX_49_o11_SW1/O + net (fo=1, routed) 0.351 -0.973 xjtag_bus_uut/N8 + SLICE_X39Y136 LUT6 (Prop_lut6_I5_O) 0.043 -0.930 r xjtag_bus_uut/dop_clk_r[2]_ishift_cnt[7]_AND_13_o1/O + net (fo=35, routed) 1.237 0.307 xjtag_bus_uut/dop_clk_r[2]_ishift_cnt[7]_AND_13_o + SLICE_X36Y144 LUT6 (Prop_lut6_I4_O) 0.043 0.350 r xjtag_bus_uut/oshift_7_rstpot/O + net (fo=1, routed) 0.000 0.350 xjtag_bus_uut/oshift_7_rstpot + SLICE_X36Y144 FDCE r xjtag_bus_uut/oshift_7/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.104 8.373 xjtag_bus_uut/clk + SLICE_X36Y144 FDCE r xjtag_bus_uut/oshift_7/C + clock pessimism -0.612 7.760 + clock uncertainty -0.074 7.686 + SLICE_X36Y144 FDCE (Setup_fdce_C_D) 0.034 7.720 xjtag_bus_uut/oshift_7 + ------------------------------------------------------------------- + required time 7.720 + arrival time -0.350 + ------------------------------------------------------------------- + slack 7.370 + +Slack (MET) : 7.378ns (required time - arrival time) + Source: xjtag_bus_uut/icmd_rd_1/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/oshift_12/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 2.539ns (logic 0.309ns (12.169%) route 2.230ns (87.831%)) + Logic Levels: 2 (LUT5=1 LUT6=1) + Clock Path Skew: -0.042ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.628ns = ( 8.372 - 10.000 ) + Source Clock Delay (SCD): -2.199ns + Clock Pessimism Removal (CPR): -0.612ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.131ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.863 0.863 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 1.081 1.944 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.242 -5.298 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.775 -3.523 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.430 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.231 -2.199 xjtag_bus_uut/clk + SLICE_X39Y137 FDRE r xjtag_bus_uut/icmd_rd_1/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y137 FDRE (Prop_fdre_C_Q) 0.223 -1.976 r xjtag_bus_uut/icmd_rd_1/Q + net (fo=36, routed) 1.998 0.023 xjtag_bus_uut/icmd_rd[1] + SLICE_X43Y145 LUT5 (Prop_lut5_I4_O) 0.043 0.066 r xjtag_bus_uut/oshift_12_rstpot_SW1/O + net (fo=1, routed) 0.232 0.297 xjtag_bus_uut/N47 + SLICE_X43Y145 LUT6 (Prop_lut6_I3_O) 0.043 0.340 r xjtag_bus_uut/oshift_12_rstpot/O + net (fo=1, routed) 0.000 0.340 xjtag_bus_uut/oshift_12_rstpot + SLICE_X43Y145 FDCE r xjtag_bus_uut/oshift_12/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 10.000 10.000 r + AA10 0.000 10.000 r sys_clkp (IN) + net (fo=0) 0.000 10.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.767 10.767 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.986 11.753 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.227 5.526 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.660 7.186 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.269 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 1.103 8.372 xjtag_bus_uut/clk + SLICE_X43Y145 FDCE r xjtag_bus_uut/oshift_12/C + clock pessimism -0.612 7.759 + clock uncertainty -0.074 7.685 + SLICE_X43Y145 FDCE (Setup_fdce_C_D) 0.034 7.719 xjtag_bus_uut/oshift_12 + ------------------------------------------------------------------- + required time 7.719 + arrival time -0.340 + ------------------------------------------------------------------- + slack 7.378 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.092ns (arrival time - required time) + Source: xjtag_bus_uut/addr_7/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/localbus_waddr_7/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.190ns (logic 0.128ns (67.430%) route 0.062ns (32.570%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.593ns + Source Clock Delay (SCD): -0.558ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.550 -0.558 xjtag_bus_uut/clk + SLICE_X43Y146 FDCE r xjtag_bus_uut/addr_7/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y146 FDCE (Prop_fdce_C_Q) 0.100 -0.458 r xjtag_bus_uut/addr_7/Q + net (fo=2, routed) 0.062 -0.397 xjtag_bus_uut/addr[7] + SLICE_X42Y146 LUT2 (Prop_lut2_I0_O) 0.028 -0.369 r xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_28_OUT_7_xo<0>1/O + net (fo=1, routed) 0.000 -0.369 xjtag_bus_uut/addr[31]_icrab_data[31]_xor_28_OUT[7] + SLICE_X42Y146 FDCE r xjtag_bus_uut/localbus_waddr_7/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.749 -0.593 xjtag_bus_uut/clk + SLICE_X42Y146 FDCE r xjtag_bus_uut/localbus_waddr_7/C + clock pessimism 0.045 -0.547 + SLICE_X42Y146 FDCE (Hold_fdce_C_D) 0.087 -0.460 xjtag_bus_uut/localbus_waddr_7 + ------------------------------------------------------------------- + required time 0.460 + arrival time -0.369 + ------------------------------------------------------------------- + slack 0.092 + +Slack (MET) : 0.092ns (arrival time - required time) + Source: xjtag_bus_uut/wdata_5/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/icrab_data_5/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.162ns (logic 0.100ns (61.678%) route 0.062ns (38.322%)) + Logic Levels: 0 + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.593ns + Source Clock Delay (SCD): -0.558ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.550 -0.558 xjtag_bus_uut/clk + SLICE_X43Y144 FDCE r xjtag_bus_uut/wdata_5/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y144 FDCE (Prop_fdce_C_Q) 0.100 -0.458 r xjtag_bus_uut/wdata_5/Q + net (fo=4, routed) 0.062 -0.396 xjtag_bus_uut/wdata[5] + SLICE_X42Y144 FDCE r xjtag_bus_uut/icrab_data_5/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.749 -0.593 xjtag_bus_uut/clk + SLICE_X42Y144 FDCE r xjtag_bus_uut/icrab_data_5/C + clock pessimism 0.045 -0.547 + SLICE_X42Y144 FDCE (Hold_fdce_C_D) 0.059 -0.488 xjtag_bus_uut/icrab_data_5 + ------------------------------------------------------------------- + required time 0.488 + arrival time -0.396 + ------------------------------------------------------------------- + slack 0.092 + +Slack (MET) : 0.118ns (arrival time - required time) + Source: xjtag_bus_uut/addr_10/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/localbus_waddr_10/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.216ns (logic 0.128ns (59.307%) route 0.088ns (40.693%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.592ns + Source Clock Delay (SCD): -0.557ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.551 -0.557 xjtag_bus_uut/clk + SLICE_X43Y147 FDCE r xjtag_bus_uut/addr_10/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y147 FDCE (Prop_fdce_C_Q) 0.100 -0.457 r xjtag_bus_uut/addr_10/Q + net (fo=2, routed) 0.088 -0.370 xjtag_bus_uut/addr[10] + SLICE_X42Y147 LUT2 (Prop_lut2_I0_O) 0.028 -0.342 r xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_28_OUT_10_xo<0>1/O + net (fo=1, routed) 0.000 -0.342 xjtag_bus_uut/addr[31]_icrab_data[31]_xor_28_OUT[10] + SLICE_X42Y147 FDCE r xjtag_bus_uut/localbus_waddr_10/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.750 -0.592 xjtag_bus_uut/clk + SLICE_X42Y147 FDCE r xjtag_bus_uut/localbus_waddr_10/C + clock pessimism 0.045 -0.546 + SLICE_X42Y147 FDCE (Hold_fdce_C_D) 0.087 -0.459 xjtag_bus_uut/localbus_waddr_10 + ------------------------------------------------------------------- + required time 0.459 + arrival time -0.342 + ------------------------------------------------------------------- + slack 0.118 + +Slack (MET) : 0.118ns (arrival time - required time) + Source: xjtag_bus_uut/addr_24/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/localbus_waddr_24/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.216ns (logic 0.128ns (59.223%) route 0.088ns (40.777%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.595ns + Source Clock Delay (SCD): -0.560ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.548 -0.560 xjtag_bus_uut/clk + SLICE_X43Y138 FDCE r xjtag_bus_uut/addr_24/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y138 FDCE (Prop_fdce_C_Q) 0.100 -0.460 r xjtag_bus_uut/addr_24/Q + net (fo=2, routed) 0.088 -0.372 xjtag_bus_uut/addr[24] + SLICE_X42Y138 LUT2 (Prop_lut2_I0_O) 0.028 -0.344 r xjtag_bus_uut/Mxor_addr[31]_icrab_data[31]_xor_28_OUT_24_xo<0>1/O + net (fo=1, routed) 0.000 -0.344 xjtag_bus_uut/addr[31]_icrab_data[31]_xor_28_OUT[24] + SLICE_X42Y138 FDCE r xjtag_bus_uut/localbus_waddr_24/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.747 -0.595 xjtag_bus_uut/clk + SLICE_X42Y138 FDCE r xjtag_bus_uut/localbus_waddr_24/C + clock pessimism 0.045 -0.549 + SLICE_X42Y138 FDCE (Hold_fdce_C_D) 0.087 -0.462 xjtag_bus_uut/localbus_waddr_24 + ------------------------------------------------------------------- + required time 0.462 + arrival time -0.344 + ------------------------------------------------------------------- + slack 0.118 + +Slack (MET) : 0.127ns (arrival time - required time) + Source: xjtag_bus_uut/localbus_wdata_4/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: UUT/ram1_reg[4]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.200ns (logic 0.100ns (50.065%) route 0.100ns (49.935%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.592ns + Source Clock Delay (SCD): -0.557ns + Clock Pessimism Removal (CPR): -0.048ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.551 -0.557 xjtag_bus_uut/clk + SLICE_X41Y145 FDCE r xjtag_bus_uut/localbus_wdata_4/C + ------------------------------------------------------------------- ------------------- + SLICE_X41Y145 FDCE (Prop_fdce_C_Q) 0.100 -0.457 r xjtag_bus_uut/localbus_wdata_4/Q + net (fo=3, routed) 0.100 -0.358 UUT/D[4] + SLICE_X40Y144 FDCE r UUT/ram1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.750 -0.592 UUT/CLK + SLICE_X40Y144 FDCE r UUT/ram1_reg[4]/C + clock pessimism 0.048 -0.543 + SLICE_X40Y144 FDCE (Hold_fdce_C_D) 0.059 -0.484 UUT/ram1_reg[4] + ------------------------------------------------------------------- + required time 0.484 + arrival time -0.358 + ------------------------------------------------------------------- + slack 0.127 + +Slack (MET) : 0.131ns (arrival time - required time) + Source: xjtag_bus_uut/addr_27/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/addr_26/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.204ns (logic 0.100ns (48.951%) route 0.104ns (51.049%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.594ns + Source Clock Delay (SCD): -0.559ns + Clock Pessimism Removal (CPR): -0.048ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.549 -0.559 xjtag_bus_uut/clk + SLICE_X41Y139 FDCE r xjtag_bus_uut/addr_27/C + ------------------------------------------------------------------- ------------------- + SLICE_X41Y139 FDCE (Prop_fdce_C_Q) 0.100 -0.459 r xjtag_bus_uut/addr_27/Q + net (fo=2, routed) 0.104 -0.355 xjtag_bus_uut/addr[27] + SLICE_X40Y138 FDCE r xjtag_bus_uut/addr_26/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.748 -0.594 xjtag_bus_uut/clk + SLICE_X40Y138 FDCE r xjtag_bus_uut/addr_26/C + clock pessimism 0.048 -0.545 + SLICE_X40Y138 FDCE (Hold_fdce_C_D) 0.059 -0.486 xjtag_bus_uut/addr_26 + ------------------------------------------------------------------- + required time 0.486 + arrival time -0.355 + ------------------------------------------------------------------- + slack 0.131 + +Slack (MET) : 0.136ns (arrival time - required time) + Source: xjtag_bus_uut/wdata_22/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/localbus_raddr_24/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.238ns (logic 0.128ns (53.805%) route 0.110ns (46.195%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.594ns + Source Clock Delay (SCD): -0.560ns + Clock Pessimism Removal (CPR): -0.048ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.548 -0.560 xjtag_bus_uut/clk + SLICE_X43Y138 FDCE r xjtag_bus_uut/wdata_22/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y138 FDCE (Prop_fdce_C_Q) 0.100 -0.460 r xjtag_bus_uut/wdata_22/Q + net (fo=4, routed) 0.110 -0.351 xjtag_bus_uut/wdata[22] + SLICE_X42Y140 LUT2 (Prop_lut2_I1_O) 0.028 -0.323 r xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_24_xo<0>1/O + net (fo=1, routed) 0.000 -0.323 xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_54_OUT[24] + SLICE_X42Y140 FDCE r xjtag_bus_uut/localbus_raddr_24/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.748 -0.594 xjtag_bus_uut/clk + SLICE_X42Y140 FDCE r xjtag_bus_uut/localbus_raddr_24/C + clock pessimism 0.048 -0.545 + SLICE_X42Y140 FDCE (Hold_fdce_C_D) 0.087 -0.458 xjtag_bus_uut/localbus_raddr_24 + ------------------------------------------------------------------- + required time 0.458 + arrival time -0.323 + ------------------------------------------------------------------- + slack 0.136 + +Slack (MET) : 0.138ns (arrival time - required time) + Source: xjtag_bus_uut/wdata_17/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/localbus_raddr_19/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.240ns (logic 0.128ns (53.272%) route 0.112ns (46.728%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.596ns + Source Clock Delay (SCD): -0.561ns + Clock Pessimism Removal (CPR): -0.049ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.547 -0.561 xjtag_bus_uut/clk + SLICE_X45Y139 FDCE r xjtag_bus_uut/wdata_17/C + ------------------------------------------------------------------- ------------------- + SLICE_X45Y139 FDCE (Prop_fdce_C_Q) 0.100 -0.461 r xjtag_bus_uut/wdata_17/Q + net (fo=4, routed) 0.112 -0.349 xjtag_bus_uut/wdata[17] + SLICE_X44Y140 LUT2 (Prop_lut2_I1_O) 0.028 -0.321 r xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_19_xo<0>1/O + net (fo=1, routed) 0.000 -0.321 xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_54_OUT[19] + SLICE_X44Y140 FDCE r xjtag_bus_uut/localbus_raddr_19/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.746 -0.596 xjtag_bus_uut/clk + SLICE_X44Y140 FDCE r xjtag_bus_uut/localbus_raddr_19/C + clock pessimism 0.049 -0.546 + SLICE_X44Y140 FDCE (Hold_fdce_C_D) 0.087 -0.459 xjtag_bus_uut/localbus_raddr_19 + ------------------------------------------------------------------- + required time 0.459 + arrival time -0.321 + ------------------------------------------------------------------- + slack 0.138 + +Slack (MET) : 0.141ns (arrival time - required time) + Source: xjtag_bus_uut/icrab_data_2/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: xjtag_bus_uut/localbus_raddr_2/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.212ns (logic 0.146ns (68.729%) route 0.066ns (31.271%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.592ns + Source Clock Delay (SCD): -0.557ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.551 -0.557 xjtag_bus_uut/clk + SLICE_X38Y144 FDCE r xjtag_bus_uut/icrab_data_2/C + ------------------------------------------------------------------- ------------------- + SLICE_X38Y144 FDCE (Prop_fdce_C_Q) 0.118 -0.439 r xjtag_bus_uut/icrab_data_2/Q + net (fo=4, routed) 0.066 -0.373 xjtag_bus_uut/icrab_data[2] + SLICE_X39Y144 LUT2 (Prop_lut2_I0_O) 0.028 -0.345 r xjtag_bus_uut/Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_2_xo<0>1/O + net (fo=1, routed) 0.000 -0.345 xjtag_bus_uut/ishift_data[69]_icrab_data[31]_xor_54_OUT[2] + SLICE_X39Y144 FDCE r xjtag_bus_uut/localbus_raddr_2/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.750 -0.592 xjtag_bus_uut/clk + SLICE_X39Y144 FDCE r xjtag_bus_uut/localbus_raddr_2/C + clock pessimism 0.045 -0.546 + SLICE_X39Y144 FDCE (Hold_fdce_C_D) 0.060 -0.486 xjtag_bus_uut/localbus_raddr_2 + ------------------------------------------------------------------- + required time 0.486 + arrival time -0.345 + ------------------------------------------------------------------- + slack 0.141 + +Slack (MET) : 0.141ns (arrival time - required time) + Source: xjtag_bus_uut/localbus_wdata_7/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: UUT/gpio0_reg[7]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk_out1_clk_wiz_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) + Data Path Delay: 0.212ns (logic 0.100ns (47.059%) route 0.112ns (52.941%)) + Logic Levels: 0 + Clock Path Skew: 0.033ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.592ns + Source Clock Delay (SCD): -0.559ns + Clock Pessimism Removal (CPR): -0.065ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.399 0.399 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.503 0.902 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.780 -1.878 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.744 -1.134 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.108 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.549 -0.559 xjtag_bus_uut/clk + SLICE_X43Y142 FDCE r xjtag_bus_uut/localbus_wdata_7/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y142 FDCE (Prop_fdce_C_Q) 0.100 -0.459 r xjtag_bus_uut/localbus_wdata_7/Q + net (fo=3, routed) 0.112 -0.347 UUT/D[7] + SLICE_X40Y143 FDCE r UUT/gpio0_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_0 rise edge) + 0.000 0.000 r + AA10 0.000 0.000 r sys_clkp (IN) + net (fo=0) 0.000 0.000 clk_uut/inst/clk_in1_p + AA10 IBUFDS (Prop_ibufds_I_O) 0.477 0.477 r clk_uut/inst/clkin1_ibufgds/O + net (fo=1, routed) 0.553 1.030 clk_uut/inst/clk_in1_clk_wiz_0 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.209 -2.179 r clk_uut/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.807 -1.372 clk_uut/inst/clk_out1_clk_wiz_0 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.342 r clk_uut/inst/clkout1_buf/O + net (fo=391, routed) 0.750 -0.592 UUT/CLK + SLICE_X40Y143 FDCE r UUT/gpio0_reg[7]/C + clock pessimism 0.065 -0.526 + SLICE_X40Y143 FDCE (Hold_fdce_C_D) 0.038 -0.488 UUT/gpio0_reg[7] + ------------------------------------------------------------------- + required time 0.488 + arrival time -0.347 + ------------------------------------------------------------------- + slack 0.141 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_out1_clk_wiz_0 +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk_uut/inst/mmcm_adv_inst/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 1.409 10.000 8.592 BUFGCTRL_X0Y0 clk_uut/inst/clkout1_buf/I +Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.071 10.000 8.929 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKOUT0 +Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X45Y144 UUT/gpio0_reg[14]/C +Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X45Y144 UUT/gpio0_reg[15]/C +Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X45Y144 UUT/gpio0_reg[17]/C +Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X40Y143 UUT/gpio0_reg[6]/C +Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X40Y143 UUT/gpio0_reg[7]/C +Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X40Y143 UUT/gpio0_reg[8]/C +Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X46Y142 UUT/gpio0_reg[9]/C +Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X41Y142 UUT/localbus_rdata_reg[3]/C +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKOUT0 +Low Pulse Width Fast FDCE/C n/a 0.400 5.000 4.600 SLICE_X45Y144 UUT/gpio0_reg[14]/C +Low Pulse Width Fast FDCE/C n/a 0.400 5.000 4.600 SLICE_X45Y144 UUT/gpio0_reg[15]/C +Low Pulse Width Fast FDCE/C n/a 0.400 5.000 4.600 SLICE_X45Y144 UUT/gpio0_reg[17]/C +Low Pulse Width Slow FDCE/C n/a 0.400 5.000 4.600 SLICE_X40Y143 UUT/gpio0_reg[6]/C +Low Pulse Width Slow FDCE/C n/a 0.400 5.000 4.600 SLICE_X40Y143 UUT/gpio0_reg[7]/C +Low Pulse Width Slow FDCE/C n/a 0.400 5.000 4.600 SLICE_X40Y143 UUT/gpio0_reg[8]/C +Low Pulse Width Fast FDCE/C n/a 0.400 5.000 4.600 SLICE_X46Y142 UUT/gpio0_reg[9]/C +Low Pulse Width Slow FDCE/C n/a 0.400 5.000 4.600 SLICE_X41Y142 UUT/localbus_rdata_reg[3]/C +Low Pulse Width Fast FDCE/C n/a 0.400 5.000 4.600 SLICE_X41Y142 UUT/localbus_rdata_reg[3]/C +Low Pulse Width Slow FDCE/C n/a 0.400 5.000 4.600 SLICE_X40Y142 UUT/localbus_rdata_reg[4]/C +High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 SLICE_X36Y141 UUT/gpio0_reg[0]/C +High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 SLICE_X36Y141 UUT/gpio0_reg[0]_lopt_replica/C +High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 SLICE_X45Y144 UUT/gpio0_reg[10]/C +High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 SLICE_X45Y144 UUT/gpio0_reg[11]/C +High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 SLICE_X45Y144 UUT/gpio0_reg[12]/C +High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 SLICE_X45Y144 UUT/gpio0_reg[13]/C +High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 SLICE_X45Y144 UUT/gpio0_reg[14]/C +High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 SLICE_X45Y144 UUT/gpio0_reg[15]/C +High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 SLICE_X46Y142 UUT/gpio0_reg[16]/C +High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 SLICE_X45Y144 UUT/gpio0_reg[17]/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: clkfbout_clk_wiz_0 + To Clock: clkfbout_clk_wiz_0 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 8.592ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clkfbout_clk_wiz_0 +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk_uut/inst/mmcm_adv_inst/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 1.409 10.000 8.592 BUFGCTRL_X0Y2 clk_uut/inst/clkf_buf/I +Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.071 10.000 8.929 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKFBOUT +Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.071 10.000 8.929 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKFBIN +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKFBIN +Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y1 clk_uut/inst/mmcm_adv_inst/CLKFBOUT + + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_timing_summary_routed.rpx b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_timing_summary_routed.rpx new file mode 100644 index 0000000..c8f19a7 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_timing_summary_routed.rpx differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_utilization_placed.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_utilization_placed.pb new file mode 100644 index 0000000..be9868d Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_utilization_placed.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_utilization_placed.rpt b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_utilization_placed.rpt new file mode 100644 index 0000000..f5737e3 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top_utilization_placed.rpt @@ -0,0 +1,216 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:15:08 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_utilization -file t160_top_utilization_placed.rpt -pb t160_top_utilization_placed.pb +| Design : t160_top +| Device : 7k160tffg676-2 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 295 | 0 | 101400 | 0.29 | +| LUT as Logic | 295 | 0 | 101400 | 0.29 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 391 | 0 | 202800 | 0.19 | +| Register as Flip Flop | 391 | 0 | 202800 | 0.19 | +| Register as Latch | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 389 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 2 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 121 | 0 | 25350 | 0.48 | +| SLICEL | 69 | 0 | | | +| SLICEM | 52 | 0 | | | +| LUT as Logic | 295 | 0 | 101400 | 0.29 | +| using O5 output only | 0 | | | | +| using O6 output only | 279 | | | | +| using O5 and O6 | 16 | | | | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 164 | 0 | 101400 | 0.16 | +| fully used LUT-FF pairs | 16 | | | | +| LUT-FF pairs with one unused LUT output | 148 | | | | +| LUT-FF pairs with one unused Flip Flop | 144 | | | | +| Unique Control Sets | 12 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 6 | 6 | 400 | 1.50 | +| IOB Master Pads | 2 | | | | +| IOB Slave Pads | 3 | | | | +| Bonded IPADs | 0 | 0 | 26 | 0.00 | +| Bonded OPADs | 0 | 0 | 16 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 1 | 1 | 384 | 0.26 | +| GTXE2_COMMON | 0 | 0 | 2 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 8 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 400 | 0.00 | +| OLOGIC | 0 | 0 | 400 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 3 | 0 | 32 | 9.38 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 1 | 0 | 8 | 12.50 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 1 | 0 | 4 | 25.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++------------+------+---------------------+ +| Ref Name | Used | Functional Category | ++------------+------+---------------------+ +| FDCE | 389 | Flop & Latch | +| LUT2 | 110 | LUT | +| LUT6 | 78 | LUT | +| LUT4 | 42 | LUT | +| LUT3 | 41 | LUT | +| LUT5 | 38 | LUT | +| OBUF | 4 | IO | +| BUFG | 3 | Clock | +| LUT1 | 2 | LUT | +| FDRE | 2 | Flop & Latch | +| CARRY4 | 2 | CarryLogic | +| MMCME2_ADV | 1 | Clock | +| IBUFDS | 1 | IO | +| BSCANE2 | 1 | Others | ++------------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++-----------+------+ +| Ref Name | Used | ++-----------+------+ +| xjtag_bus | 1 | +| clk_wiz_0 | 1 | ++-----------+------+ + + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/usage_statistics_webtalk.html b/localbus_demo/prj/localbus_demo.runs/impl_1/usage_statistics_webtalk.html new file mode 100644 index 0000000..889c85d --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,775 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

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software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedSun Jun 28 17:15:52 2020os_platformWIN64
product_versionVivado v2018.2 (64-bit)project_idf3643b6b285e4839b5c94a9b48f276ec
project_iteration3random_idfb024045cda053fdb075e8f3e6f51813
registration_idfb024045cda053fdb075e8f3e6f51813route_designTRUE
target_devicexc7k160ttarget_familykintex7
target_packageffg676target_speed-2
tool_flowVivado

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user_environment
cpu_nameIntel(R) Core(TM) i5-6500 CPU @ 3.20GHzcpu_speed3192 MHz
os_nameMicrosoft Windows 7 , 64-bitos_releaseService Pack 1 (build 7601)
system_ram16.000 GBtotal_processors1

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vivado_usage
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gui_handlers
abstractfileview_reload=1addsrcwizard_specify_hdl_netlist_block_design=1addsrcwizard_specify_or_create_constraint_files=1addsrcwizard_specify_simulation_specific_hdl_files=1
basedialog_apply=1basedialog_cancel=1basedialog_ok=15basedialog_yes=7
confirmsavetexteditsdialog_no=1constraintschooserpanel_add_files=1coretreetablepanel_core_tree_table=53customizecoredialog_choose_ip_location=1
customizecoredialog_ip_location=1expruntreepanel_exp_run_tree_table=5filesetpanel_file_set_panel_tree=22flownavigatortreepanel_flow_navigator_tree=13
fpgachooser_fpga_table=1fpgachooser_package=1fpgachooser_speed=1gettingstartedview_create_new_project=1
mainmenumgr_edit=2mainmenumgr_file=6mainmenumgr_flow=4mainmenumgr_project=3
mainmenumgr_reports=2mainmenumgr_tools=4msgtreepanel_discard_user_created_messages=1msgtreepanel_message_severity=1
msgtreepanel_message_view_tree=10msgview_clear_messages_resulting_from_user_executed=2openfileaction_cancel=1pacommandnames_close_project=2
paviews_code=5paviews_ip_catalog=2projectnamechooser_choose_project_location=2projectnamechooser_project_name=1
rdicommands_copy=2rdicommands_line_comment=2rdicommands_paste=1rdicommands_save_file=4
rungadget_show_error=2settingsdialog_options_tree=4settingseditorpage_use_this_drop_down_list_box_to_select=1simpleoutputproductdialog_generate_output_products_immediately=1
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=2syntheticagettingstartedview_recent_projects=2tclconsoleview_tcl_console_code_editor=1
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java_command_handlers
addsources=3closeproject=2coreview=2customizecore=2
newproject=1runbitgen=7showview=6toolssettings=1
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other_data
guimode=3
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project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=1export_simulation_ies=1
export_simulation_modelsim=1export_simulation_questa=1export_simulation_riviera=1export_simulation_vcs=1
export_simulation_xsim=1implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=4synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilogtarget_simulator=XSimtotalimplruns=2totalsynthesisruns=2
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unisim_transformation
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post_unisim_transformation
bscane2=1bufg=3carry4=2fdce=389
fdre=2gnd=5ibufds=1lut1=2
lut2=102lut3=49lut4=42lut5=38
lut6=78mmcme2_adv=1obuf=4vcc=2
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pre_unisim_transformation
bscane2=1bufg=3carry4=2fdce=389
fdre=2gnd=5ibufds=1lut1=2
lut2=102lut3=49lut4=42lut5=38
lut6=78mmcme2_adv=1obuf=4vcc=2
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ip_statistics
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clk_wiz_v6_0_1_0_0/1
clkin1_period=10.000clkin2_period=10.000clock_mgr_type=NAcomponent_name=clk_wiz_0
core_container=NAenable_axi=0feedback_source=FDBK_AUTOfeedback_type=SINGLE
iptotal=1manual_override=falsenum_out_clk=1primitive=MMCM
use_dyn_phase_shift=falseuse_dyn_reconfig=falseuse_inclk_stopped=falseuse_inclk_switchover=false
use_locked=trueuse_max_i_jitter=falseuse_min_o_jitter=falseuse_phase_alignment=true
use_power_down=falseuse_reset=false
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report_drc
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command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-internal=default::[not_specified]-internal_only=default::[not_specified]-messages=default::[not_specified]
-name=default::[not_specified]-no_waivers=default::[not_specified]-return_string=default::[not_specified]-ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
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results
cfgbvs-1=1
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report_methodology
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command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-waived=default::[not_specified]
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results
timing-18=4
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report_power
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command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-l=default::[not_specified]-name=default::[not_specified]-no_propagation=default::[not_specified]
-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]-vid=default::[not_specified]
-xpe=default::[not_specified]
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")clocks=0.002219confidence_level_clock_activity=High
confidence_level_design_state=Highconfidence_level_device_models=Highconfidence_level_internal_activity=Mediumconfidence_level_io_activity=High
confidence_level_overall=Mediumcustomer=TBDcustomer_class=TBDdevstatic=0.113488
die=xc7k160tffg676-2dsp_output_toggle=12.500000dynamic=0.112259effective_thetaja=1.9
enable_probability=0.990000family=kintex7ff_toggle=12.500000flow_state=routed
heatsink=medium (Medium Profile)i/o=0.003768input_toggle=12.500000junction_temp=25.4 (C)
logic=0.000202mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000mgtvccaux_dynamic_current=0.000000mgtvccaux_static_current=0.000000mgtvccaux_total_current=0.000000
mgtvccaux_voltage=1.800000mmcm=0.105861netlist_net_matched=NAoff-chip_power=0.000000
on-chip_power=0.225747output_enable=1.000000output_load=5.000000output_toggle=12.500000
package=ffg676pct_clock_constrained=2.000000pct_inputs_defined=100platform=nt64
process=typicalram_enable=50.000000ram_write=50.000000read_saif=False
set/reset_probability=0.000000signal_rate=Falsesignals=0.000208simulation_file=None
speedgrade=-2static_prob=Falsetemp_grade=commercialthetajb=4.0 (C/W)
thetasa=3.4 (C/W)toggle_rate=Falseuser_board_temp=25.0 (C)user_effective_thetaja=1.9
user_junc_temp=25.4 (C)user_thetajb=4.0 (C/W)user_thetasa=3.4 (C/W)vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000vccadc_total_current=0.020000vccadc_voltage=1.800000vccaux_dynamic_current=0.060187
vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000
vccaux_static_current=0.018197vccaux_total_current=0.078384vccaux_voltage=1.800000vccbram_dynamic_current=0.000000
vccbram_static_current=0.000919vccbram_total_current=0.000919vccbram_voltage=1.000000vccint_dynamic_current=0.003922
vccint_static_current=0.040515vccint_total_current=0.044437vccint_voltage=1.000000vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000vcco12_total_current=0.000000vcco12_voltage=1.200000vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000vcco135_total_current=0.000000vcco135_voltage=1.350000vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000vcco15_total_current=0.000000vcco15_voltage=1.500000vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000vcco18_total_current=0.000000vcco18_voltage=1.800000vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000vcco25_total_current=0.000000vcco25_voltage=2.500000vcco33_dynamic_current=0.000000
vcco33_static_current=0.001000vcco33_total_current=0.001000vcco33_voltage=3.300000version=2018.2
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=3bufgctrl_util_percentage=9.38
bufhce_available=120bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=32bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=16bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=32bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=8mmcme2_adv_fixed=0mmcme2_adv_used=1mmcme2_adv_util_percentage=12.50
plle2_adv_available=8plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=600dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_i_dci=0
diff_hstl_i_dci_18=0diff_hstl_ii=0diff_hstl_ii_18=0diff_hstl_ii_dci=0
diff_hstl_ii_dci_18=0diff_hstl_ii_t_dci=0diff_hstl_ii_t_dci_18=0diff_hsul_12=0
diff_hsul_12_dci=0diff_mobile_ddr=0diff_sstl12=0diff_sstl12_dci=0
diff_sstl12_t_dci=0diff_sstl135=0diff_sstl135_dci=0diff_sstl135_r=0
diff_sstl135_t_dci=0diff_sstl15=1diff_sstl15_dci=0diff_sstl15_r=0
diff_sstl15_t_dci=0diff_sstl18_i=0diff_sstl18_i_dci=0diff_sstl18_ii=0
diff_sstl18_ii_dci=0diff_sstl18_ii_t_dci=0hslvdci_15=0hslvdci_18=0
hstl_i=0hstl_i_12=0hstl_i_18=0hstl_i_dci=0
hstl_i_dci_18=0hstl_ii=0hstl_ii_18=0hstl_ii_dci=0
hstl_ii_dci_18=0hstl_ii_t_dci=0hstl_ii_t_dci_18=0hsul_12=0
hsul_12_dci=0lvcmos12=0lvcmos15=0lvcmos18=0
lvcmos25=0lvcmos33=1lvdci_15=0lvdci_18=0
lvdci_dv2_15=0lvdci_dv2_18=0lvds=0lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl12=0sstl12_dci=0
sstl12_t_dci=0sstl135=0sstl135_dci=0sstl135_r=0
sstl135_t_dci=0sstl15=0sstl15_dci=0sstl15_r=0
sstl15_t_dci=0sstl18_i=0sstl18_i_dci=0sstl18_ii=0
sstl18_ii_dci=0sstl18_ii_t_dci=0tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=325block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=650ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=325ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
primitives
bscane2_functional_category=Othersbscane2_used=1bufg_functional_category=Clockbufg_used=3
carry4_functional_category=CarryLogiccarry4_used=2fdce_functional_category=Flop & Latchfdce_used=389
fdre_functional_category=Flop & Latchfdre_used=2ibufds_functional_category=IOibufds_used=1
lut1_functional_category=LUTlut1_used=2lut2_functional_category=LUTlut2_used=110
lut3_functional_category=LUTlut3_used=41lut4_functional_category=LUTlut4_used=42
lut5_functional_category=LUTlut5_used=38lut6_functional_category=LUTlut6_used=78
mmcme2_adv_functional_category=Clockmmcme2_adv_used=1obuf_functional_category=IOobuf_used=4
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=50700f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=25350f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=101400lut_as_logic_fixed=0lut_as_logic_used=295lut_as_logic_util_percentage=0.29
lut_as_memory_available=35000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=202800register_as_flip_flop_fixed=0register_as_flip_flop_used=391register_as_flip_flop_util_percentage=0.19
register_as_latch_available=202800register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=101400slice_luts_fixed=0slice_luts_used=295slice_luts_util_percentage=0.29
slice_registers_available=202800slice_registers_fixed=0slice_registers_used=391slice_registers_util_percentage=0.19
fully_used_lut_ff_pairs_fixed=0.19fully_used_lut_ff_pairs_used=16lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0
lut_as_logic_available=101400lut_as_logic_fixed=0lut_as_logic_used=295lut_as_logic_util_percentage=0.29
lut_as_memory_available=35000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0lut_as_shift_register_used=0lut_ff_pairs_with_one_unused_flip_flop_fixed=0lut_ff_pairs_with_one_unused_flip_flop_used=144
lut_ff_pairs_with_one_unused_lut_output_fixed=144lut_ff_pairs_with_one_unused_lut_output_used=148lut_flip_flop_pairs_available=101400lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=164lut_flip_flop_pairs_util_percentage=0.16slice_available=25350slice_fixed=0
slice_used=121slice_util_percentage=0.48slicel_fixed=0slicel_used=69
slicem_fixed=0slicem_used=52unique_control_sets_used=12using_o5_and_o6_fixed=12
using_o5_and_o6_used=16using_o5_output_only_fixed=16using_o5_output_only_used=0using_o6_output_only_fixed=0
using_o6_output_only_used=279
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=1bscane2_util_percentage=25.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + +
router
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
actual_expansions=903791bogomips=0bram18=0bram36=0
bufg=0bufr=0congestion_level=0ctrls=12
dsp=0effort=2estimated_expansions=355674ff=391
global_clocks=3high_fanout_nets=0iob=6lut=295
movable_instances=721nets=746pins=3577pll=0
router_runtime=0.000000router_timing_driven=1threads=2timing_constraints_exist=1
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7k160tffg676-2
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=t160_top-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:26shls_ip=0memory_gain=524.953MBmemory_peak=814.613MB
+

+ + diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/usage_statistics_webtalk.xml b/localbus_demo/prj/localbus_demo.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..a56236d --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,704 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + +
+
+ +
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+
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+
+ +
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+
+
+ + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
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+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
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+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
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+
+ + + + + + + + +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/vivado.jou b/localbus_demo/prj/localbus_demo.runs/impl_1/vivado.jou new file mode 100644 index 0000000..149e6c2 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun Jun 28 17:14:33 2020 +# Process ID: 8172 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1 +# Command line: vivado.exe -log t160_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source t160_top.tcl -notrace +# Log file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1/t160_top.vdi +# Journal file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source t160_top.tcl -notrace diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/vivado.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/vivado.pb new file mode 100644 index 0000000..e283382 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/vivado.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/impl_1/write_bitstream.pb b/localbus_demo/prj/localbus_demo.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..525cfe5 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/impl_1/write_bitstream.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/.Vivado_Synthesis.queue.rst b/localbus_demo/prj/localbus_demo.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/.Xil/t160_top_propImpl.xdc b/localbus_demo/prj/localbus_demo.runs/synth_1/.Xil/t160_top_propImpl.xdc new file mode 100644 index 0000000..e3491fc --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/.Xil/t160_top_propImpl.xdc @@ -0,0 +1,11 @@ +set_property SRC_FILE_INFO {cfile:D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc rfile:../../../../src/t160_top.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R17 [get_ports {led[0]}] +set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN T17 [get_ports {led[1]}] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U16 [get_ports {led[2]}] +set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U17 [get_ports {led[3]}] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN AA10 [get_ports sys_clkp] diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/.ngc2edfcache/xjtag_bus_ngc_697f0a13.edif b/localbus_demo/prj/localbus_demo.runs/synth_1/.ngc2edfcache/xjtag_bus_ngc_697f0a13.edif new file mode 100644 index 0000000..60ef912 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/.ngc2edfcache/xjtag_bus_ngc_697f0a13.edif @@ -0,0 +1,7320 @@ +(edif xjtag_bus + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2020 6 28 17 14 24) + (program "Xilinx ngc2edif" (version "P_INT.20180321")) + (author "Xilinx. Inc ") + (comment "This EDIF netlist is to be used within supported synthesis tools") + (comment "for determining resource/timing estimates of the design component") + (comment "represented by this netlist.") + (comment "Command line: -mdp2sp -w -secure xjtag_bus.ngc xjtag_bus.edif "))) + (external UNISIMS + (edifLevel 0) + (technology (numberDefinition)) + (cell GND + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell FDC + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CLR + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDCE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port CLR + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell XORCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port LI + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell BSCAN_SPARTAN6 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port TDO + (direction INPUT) + ) + (port CAPTURE + (direction OUTPUT) + ) + (port DRCK + (direction OUTPUT) + ) + (port RESET + (direction OUTPUT) + ) + (port RUNTEST + (direction OUTPUT) + ) + (port SEL + (direction OUTPUT) + ) + (port SHIFT + (direction OUTPUT) + ) + (port TCK + (direction OUTPUT) + ) + (port TDI + (direction OUTPUT) + ) + (port TMS + (direction OUTPUT) + ) + (port UPDATE + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT6 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port I5 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT5 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell INV + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + ) + + (library xjtag_bus_lib + (edifLevel 0) + (technology (numberDefinition)) + (cell xjtag_bus + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port clk + (direction INPUT) + ) + (port rst + (direction INPUT) + ) + (port localbus_wvalid + (direction OUTPUT) + ) + (port localbus_rvalid + (direction OUTPUT) + ) + (port (array (rename localbus_rdata "localbus_rdata<31:0>") 32) + (direction INPUT)) + (port (array (rename localbus_waddr "localbus_waddr<31:0>") 32) + (direction OUTPUT)) + (port (array (rename localbus_wdata "localbus_wdata<31:0>") 32) + (direction OUTPUT)) + (port (array (rename localbus_wmask "localbus_wmask<3:0>") 4) + (direction OUTPUT)) + (port (array (rename localbus_raddr "localbus_raddr<31:0>") 32) + (direction OUTPUT)) + (designator "xc7k70t-2-fbg676") + (property TYPE (string "xjtag_bus") (owner "Xilinx")) + (property BUS_INFO (string "32:INPUT:localbus_rdata<31:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:OUTPUT:localbus_waddr<31:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:OUTPUT:localbus_wdata<31:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:localbus_wmask<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:OUTPUT:localbus_raddr<31:0>") (owner "Xilinx")) + (property SHREG_MIN_SIZE (string "2") (owner "Xilinx")) + (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 0) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "xjtag_bus_xjtag_bus") (owner "Xilinx")) + ) + (contents + (instance XST_GND + (viewRef view_1 (cellRef GND (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename localbus_wvalid_renamed_0 "localbus_wvalid") + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename localbus_rvalid_renamed_1 "localbus_rvalid") + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_0 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_1 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_2 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_3 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_4 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_5 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_6 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_7 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_8 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_9 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_10 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_11 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_12 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_13 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_14 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_15 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_16 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_17 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_18 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_19 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_20 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_21 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_22 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_23 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_24 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_25 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_26 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_27 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_28 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_29 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_30 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance wdata_31 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename iwr_valid_renamed_2 "iwr_valid") + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename ird_valid_renamed_3 "ird_valid") + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance cmd_0 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance cmd_1 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance cmd_2 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance cmd_3 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance cmd_4 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance cmd_5 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance cmd_6 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance cmd_7 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_0 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_1 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_2 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_3 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_4 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_5 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_6 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_7 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_8 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_9 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_10 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_11 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_12 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_13 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_14 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_15 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_16 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_17 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_18 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_19 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_20 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_21 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_22 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_23 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_24 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_25 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_26 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_27 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_28 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_29 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_30 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icrab_data_31 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icmd_rd_0 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance icmd_rd_1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wmask_0 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wmask_1 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wmask_2 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wmask_3 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_0 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_1 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_2 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_3 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_4 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_5 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_6 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_7 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_8 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_9 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_10 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_11 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_12 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_13 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_14 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_15 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_16 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_17 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_18 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_19 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_20 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_21 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_22 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_23 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_24 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_25 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_26 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_27 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_28 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_29 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_30 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance addr_31 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_0 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_1 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_2 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_3 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_4 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_5 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_6 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_7 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_8 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_9 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_10 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_11 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_12 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_13 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_14 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_15 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_16 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_17 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_18 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_19 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_20 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_21 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_22 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_23 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_24 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_25 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_26 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_27 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_28 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_29 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_30 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_wdata_31 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_0 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_1 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_2 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_3 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_4 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_5 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_6 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_7 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_8 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_9 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_10 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_11 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_12 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_13 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_14 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_15 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_16 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_17 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_18 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_19 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_20 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_21 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_22 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_23 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_24 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_25 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_26 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_27 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_28 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_29 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_30 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_raddr_31 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_0 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_1 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_2 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_3 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_4 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_5 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_6 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_7 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_8 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_9 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_10 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_11 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_12 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_13 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_14 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_15 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_16 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_17 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_18 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_19 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_20 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_21 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_22 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_23 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_24 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_25 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_26 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_27 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_28 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_29 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_30 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance localbus_waddr_31 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance dop1949_r_0 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance dop1949_r_1 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance dop_clk_r_0 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance dop_clk_r_1 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance dop_clk_r_2 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance dop_clk_r_3 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance chip_r_0 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance chip_r_1 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance chip_r_2 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_lut_0__ "Mcount_ishift_cnt_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_cy_0__ "Mcount_ishift_cnt_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_xor_0__ "Mcount_ishift_cnt_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_lut_1__ "Mcount_ishift_cnt_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_cy_1__ "Mcount_ishift_cnt_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_xor_1__ "Mcount_ishift_cnt_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_lut_2__ "Mcount_ishift_cnt_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_cy_2__ "Mcount_ishift_cnt_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_xor_2__ "Mcount_ishift_cnt_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_lut_3__ "Mcount_ishift_cnt_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_cy_3__ "Mcount_ishift_cnt_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_xor_3__ "Mcount_ishift_cnt_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_lut_4__ "Mcount_ishift_cnt_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_cy_4__ "Mcount_ishift_cnt_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_xor_4__ "Mcount_ishift_cnt_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_lut_5__ "Mcount_ishift_cnt_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_cy_5__ "Mcount_ishift_cnt_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_xor_5__ "Mcount_ishift_cnt_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_lut_6__ "Mcount_ishift_cnt_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_cy_6__ "Mcount_ishift_cnt_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_xor_6__ "Mcount_ishift_cnt_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_lut_7__ "Mcount_ishift_cnt_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename Mcount_ishift_cnt_xor_7__ "Mcount_ishift_cnt_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance ishift_cnt_0 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance ishift_cnt_1 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance ishift_cnt_2 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance ishift_cnt_3 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance ishift_cnt_4 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance ishift_cnt_5 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance ishift_cnt_6 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance ishift_cnt_7 + (viewRef view_1 (cellRef FDCE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename bscan_xjtag_uut_BSCAN_SPARTAN6_inst "bscan_xjtag_uut/BSCAN_SPARTAN6_inst") + (viewRef view_1 (cellRef BSCAN_SPARTAN6 (libraryRef UNISIMS))) + (property JTAG_CHAIN (integer 3) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance (rename ird_valid_icmd_rd_1__AND_11_o1 "ird_valid_icmd_rd[1]_AND_11_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___18___ird_valid_icmd_rd[1]_AND_11_o1") (owner "Xilinx")) + (property INIT (string "08") (owner "Xilinx")) + ) + (instance (rename dop_clk_r_2__dop_clk_r_1__AND_3_o1 "dop_clk_r[2]_dop_clk_r[1]_AND_3_o1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___22___dop_clk_r[2]_dop_clk_r[1]_AND_3_o1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename &_n0173_inv1 "_n0173_inv1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___1____n0173_inv1") (owner "Xilinx")) + (property INIT (string "08") (owner "Xilinx")) + ) + (instance (rename bscan_xjtag_uut_Mmux_CS11 "bscan_xjtag_uut/Mmux_CS11") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___24____n0202_inv_SW1") (owner "Xilinx")) + (property INIT (string "B") (owner "Xilinx")) + ) + (instance (rename bscan_xjtag_uut_CLK1 "bscan_xjtag_uut/CLK1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___23___bscan_xjtag_uut/CLK1") (owner "Xilinx")) + (property INIT (string "8") (owner "Xilinx")) + ) + (instance (rename bscan_xjtag_uut_DOP19491 "bscan_xjtag_uut/DOP19491") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___23___bscan_xjtag_uut/CLK1") (owner "Xilinx")) + (property INIT (string "8") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_31_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_31_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___20___Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_31_xo<0>1") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_30_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_30_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_29_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_29_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_28_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_28_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_27_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_27_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_26_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_26_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_25_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_25_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_24_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_24_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_23_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_23_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_22_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_22_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_21_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_21_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_20_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_20_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_19_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_19_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_18_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_18_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_17_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_17_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_16_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_16_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_15_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_15_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_14_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_14_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_13_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_13_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_12_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_12_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_11_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_11_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_10_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_10_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_9_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_9_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_8_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_8_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_7_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_7_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_6_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_6_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_5_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_5_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_4_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_4_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_3_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_3_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_2_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_2_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_1_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_1_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_wdata_31__icrab_data_31__xor_31_OUT_0_xo_0_1 "Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_0_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_31_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_31_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_30_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_30_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_29_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_29_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_28_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_28_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_27_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_27_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_26_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_26_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_25_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_25_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_24_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_24_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_23_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_23_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_22_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_22_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_21_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_21_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_20_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_20_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_19_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_19_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_18_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_18_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_17_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_17_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_16_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_16_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_15_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_15_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_14_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_14_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_13_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_13_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_12_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_12_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_11_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_11_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_10_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_10_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_9_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_9_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_8_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_8_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_7_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_7_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_6_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_6_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_5_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_5_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_4_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_4_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_3_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_3_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_2_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_2_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_1_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_1_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_0_xo_0_1 "Mxor_ishift_data[69]_icrab_data[31]_xor_54_OUT_0_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_31_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_31_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_30_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_30_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_29_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_29_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_28_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_28_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_27_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_27_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_26_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_26_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_25_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_25_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_24_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_24_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_23_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_23_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_22_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_22_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_21_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_21_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_20_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_20_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_19_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_19_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_18_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_18_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_17_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_17_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_16_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_16_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_15_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_15_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_14_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_14_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_13_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_13_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_12_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_12_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_11_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_11_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_10_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_10_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_9_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_9_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_8_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_8_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_7_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_7_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_6_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_6_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_5_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_5_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_4_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_4_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_3_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_3_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_2_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_2_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_1_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_1_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename Mxor_addr_31__icrab_data_31__xor_28_OUT_0_xo_0_1 "Mxor_addr[31]_icrab_data[31]_xor_28_OUT_0_xo<0>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename ird_valid_ishift_data_71__AND_10_o1 "ird_valid_ishift_data[71]_AND_10_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___18___ird_valid_icmd_rd[1]_AND_11_o1") (owner "Xilinx")) + (property INIT (string "08") (owner "Xilinx")) + ) + (instance (rename &_n0181_inv1 "_n0181_inv1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___21____n0181_inv1") (owner "Xilinx")) + (property INIT (string "02") (owner "Xilinx")) + ) + (instance (rename Mmux_GND_1_o_cmd_1__MUX_42_o11 "Mmux_GND_1_o_cmd[1]_MUX_42_o11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___21____n0181_inv1") (owner "Xilinx")) + (property INIT (string "02") (owner "Xilinx")) + ) + (instance (rename &_n0186_inv1 "_n0186_inv1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___2____n0186_inv1") (owner "Xilinx")) + (property INIT (string "AE") (owner "Xilinx")) + ) + (instance (rename &_n0177_inv1 "_n0177_inv1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___1____n0173_inv1") (owner "Xilinx")) + (property INIT (string "A8") (owner "Xilinx")) + ) + (instance (rename Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW0 "Mmux_GND_1_o_ishift_data[71]_MUX_49_o11_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename Mmux_GND_1_o_ishift_data_71__MUX_49_o11_renamed_4 "Mmux_GND_1_o_ishift_data[71]_MUX_49_o11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000001000000") (owner "Xilinx")) + ) + (instance (rename &_n0202_inv_SW0 "_n0202_inv_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00011111FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename dop1950_r_0_renamed_5 "dop1950_r_0") + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename &_n0202_inv_SW1 "_n0202_inv_SW1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___24____n0202_inv_SW1") (owner "Xilinx")) + (property INIT (string "10") (owner "Xilinx")) + ) + (instance (rename Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW1 "Mmux_GND_1_o_ishift_data[71]_MUX_49_o11_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FBFF") (owner "Xilinx")) + ) + (instance (rename dop_clk_r_2__ishift_cnt_7__AND_13_o1 "dop_clk_r[2]_ishift_cnt[7]_AND_13_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000100") (owner "Xilinx")) + ) + (instance oshift_0 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_1 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_2 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_3 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_4 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_5 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_6 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_7 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_8 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_9 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_10 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_11 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_12 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_13 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_14 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_15 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_16 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_17 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_18 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_19 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_20 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_21 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_22 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_23 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_24 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_25 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_26 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_27 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_28 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_29 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_30 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_31 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_32 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_33 + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance oshift_33_rstpot_SW0 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_33_rstpot_renamed_6 "oshift_33_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00A2A2") (owner "Xilinx")) + ) + (instance (rename Mmux_GND_1_o_ishift_data_71__MUX_49_o1_SW0_SW0 "Mmux_GND_1_o_ishift_data[71]_MUX_49_o1_SW0_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___20___Mxor_wdata[31]_icrab_data[31]_xor_31_OUT_31_xo<0>1") (owner "Xilinx")) + (property INIT (string "B") (owner "Xilinx")) + ) + (instance (rename &_n0202_inv_SW2 "_n0202_inv_SW2") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___2____n0186_inv1") (owner "Xilinx")) + (property INIT (string "AEA2") (owner "Xilinx")) + ) + (instance (rename dop1950_r_0_rstpot_renamed_7 "dop1950_r_0_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAAFE02FF00") (owner "Xilinx")) + ) + (instance oshift_2_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___17___oshift_2_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_2_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB7B887B") (owner "Xilinx")) + ) + (instance (rename oshift_2_rstpot_renamed_8 "oshift_2_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_3_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___17___oshift_2_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_3_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_3_rstpot_renamed_9 "oshift_3_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_4_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___16___oshift_4_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_4_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_4_rstpot_renamed_10 "oshift_4_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_5_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___16___oshift_4_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_5_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_5_rstpot_renamed_11 "oshift_5_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_6_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___15___oshift_6_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_6_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_6_rstpot_renamed_12 "oshift_6_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_7_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___15___oshift_6_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_7_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_7_rstpot_renamed_13 "oshift_7_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_8_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___14___oshift_8_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_8_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_8_rstpot_renamed_14 "oshift_8_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_9_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___14___oshift_8_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_9_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_9_rstpot_renamed_15 "oshift_9_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_10_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___13___oshift_10_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_10_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_10_rstpot_renamed_16 "oshift_10_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_11_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___13___oshift_10_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_11_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_11_rstpot_renamed_17 "oshift_11_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_12_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___12___oshift_12_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_12_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_12_rstpot_renamed_18 "oshift_12_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_13_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___12___oshift_12_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_13_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_13_rstpot_renamed_19 "oshift_13_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_14_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___11___oshift_14_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_14_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_14_rstpot_renamed_20 "oshift_14_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_15_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___11___oshift_14_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_15_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_15_rstpot_renamed_21 "oshift_15_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_16_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___10___oshift_16_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_16_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_16_rstpot_renamed_22 "oshift_16_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_17_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___10___oshift_16_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_17_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_17_rstpot_renamed_23 "oshift_17_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_18_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___9___oshift_18_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_18_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_18_rstpot_renamed_24 "oshift_18_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_19_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___9___oshift_18_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_19_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_19_rstpot_renamed_25 "oshift_19_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_20_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___8___oshift_20_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_20_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_20_rstpot_renamed_26 "oshift_20_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_21_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___8___oshift_20_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_21_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_21_rstpot_renamed_27 "oshift_21_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_22_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___7___oshift_22_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_22_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_22_rstpot_renamed_28 "oshift_22_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_23_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___7___oshift_22_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_23_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_23_rstpot_renamed_29 "oshift_23_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_24_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___6___oshift_24_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_24_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_24_rstpot_renamed_30 "oshift_24_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_25_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___6___oshift_24_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_25_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_25_rstpot_renamed_31 "oshift_25_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_26_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___5___oshift_26_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_26_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_26_rstpot_renamed_32 "oshift_26_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_27_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___5___oshift_26_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_27_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_27_rstpot_renamed_33 "oshift_27_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_28_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___4___oshift_28_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_28_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_28_rstpot_renamed_34 "oshift_28_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_29_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___4___oshift_28_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_29_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_29_rstpot_renamed_35 "oshift_29_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_30_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___22___dop_clk_r[2]_dop_clk_r[1]_AND_3_o1") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_30_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_30_rstpot_renamed_36 "oshift_30_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_31_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___3___oshift_31_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance oshift_31_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_31_rstpot_renamed_37 "oshift_31_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance oshift_32_rstpot_SW0 + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___3___oshift_31_rstpot_SW0") (owner "Xilinx")) + (property INIT (string "CA") (owner "Xilinx")) + ) + (instance oshift_32_rstpot_SW1 + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F05ACC00") (owner "Xilinx")) + ) + (instance (rename oshift_32_rstpot_renamed_38 "oshift_32_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00AAAAFF00E2E2") (owner "Xilinx")) + ) + (instance (rename &_n0198_inv1_SW0 "_n0198_inv1_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___0____n0198_inv1_SW0") (owner "Xilinx")) + (property INIT (string "AEA2") (owner "Xilinx")) + ) + (instance (rename oshift_0_rstpot_renamed_39 "oshift_0_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EFEFAAAAEFEFFF00") (owner "Xilinx")) + ) + (instance (rename &_n0198_inv1_SW1 "_n0198_inv1_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___0____n0198_inv1_SW0") (owner "Xilinx")) + (property INIT (string "AEA2") (owner "Xilinx")) + ) + (instance (rename oshift_1_rstpot_renamed_40 "oshift_1_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EFEFAAAAEFEFFF00") (owner "Xilinx")) + ) + (instance (rename &_n0206_inv1_rstpot_renamed_41 "_n0206_inv1_rstpot") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00000100") (owner "Xilinx")) + ) + (instance (rename icmd_rd_0_dpot_renamed_42 "icmd_rd_0_dpot") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___19___icmd_rd_0_dpot") (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename icmd_rd_1_dpot_renamed_43 "icmd_rd_1_dpot") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___19___icmd_rd_0_dpot") (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW2 "Mmux_GND_1_o_ishift_data[71]_MUX_49_o11_SW2") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFDF") (owner "Xilinx")) + ) + (instance (rename Mmux_GND_1_o_ishift_data_71__MUX_49_o1 "Mmux_GND_1_o_ishift_data[71]_MUX_49_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000004") (owner "Xilinx")) + ) + (instance (rename dop_clk_r_1_1_renamed_44 "dop_clk_r_1_1") + (viewRef view_1 (cellRef FDC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename chip_r_1__inv1_INV_0 "chip_r<1>_inv1_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (net (rename localbus_rdata_31_ "localbus_rdata<31>") + (joined + (portRef (member localbus_rdata 0)) + (portRef I0 (instanceRef oshift_33_rstpot_SW0)) + ) + ) + (net (rename localbus_rdata_30_ "localbus_rdata<30>") + (joined + (portRef (member localbus_rdata 1)) + (portRef I0 (instanceRef oshift_32_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_29_ "localbus_rdata<29>") + (joined + (portRef (member localbus_rdata 2)) + (portRef I0 (instanceRef oshift_31_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_28_ "localbus_rdata<28>") + (joined + (portRef (member localbus_rdata 3)) + (portRef I0 (instanceRef oshift_30_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_27_ "localbus_rdata<27>") + (joined + (portRef (member localbus_rdata 4)) + (portRef I0 (instanceRef oshift_29_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_26_ "localbus_rdata<26>") + (joined + (portRef (member localbus_rdata 5)) + (portRef I0 (instanceRef oshift_28_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_25_ "localbus_rdata<25>") + (joined + (portRef (member localbus_rdata 6)) + (portRef I0 (instanceRef oshift_27_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_24_ "localbus_rdata<24>") + (joined + (portRef (member localbus_rdata 7)) + (portRef I0 (instanceRef oshift_26_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_23_ "localbus_rdata<23>") + (joined + (portRef (member localbus_rdata 8)) + (portRef I0 (instanceRef oshift_25_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_22_ "localbus_rdata<22>") + (joined + (portRef (member localbus_rdata 9)) + (portRef I0 (instanceRef oshift_24_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_21_ "localbus_rdata<21>") + (joined + (portRef (member localbus_rdata 10)) + (portRef I0 (instanceRef oshift_23_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_20_ "localbus_rdata<20>") + (joined + (portRef (member localbus_rdata 11)) + (portRef I0 (instanceRef oshift_22_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_19_ "localbus_rdata<19>") + (joined + (portRef (member localbus_rdata 12)) + (portRef I0 (instanceRef oshift_21_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_18_ "localbus_rdata<18>") + (joined + (portRef (member localbus_rdata 13)) + (portRef I0 (instanceRef oshift_20_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_17_ "localbus_rdata<17>") + (joined + (portRef (member localbus_rdata 14)) + (portRef I0 (instanceRef oshift_19_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_16_ "localbus_rdata<16>") + (joined + (portRef (member localbus_rdata 15)) + (portRef I0 (instanceRef oshift_18_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_15_ "localbus_rdata<15>") + (joined + (portRef (member localbus_rdata 16)) + (portRef I0 (instanceRef oshift_17_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_14_ "localbus_rdata<14>") + (joined + (portRef (member localbus_rdata 17)) + (portRef I0 (instanceRef oshift_16_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_13_ "localbus_rdata<13>") + (joined + (portRef (member localbus_rdata 18)) + (portRef I0 (instanceRef oshift_15_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_12_ "localbus_rdata<12>") + (joined + (portRef (member localbus_rdata 19)) + (portRef I0 (instanceRef oshift_14_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_11_ "localbus_rdata<11>") + (joined + (portRef (member localbus_rdata 20)) + (portRef I0 (instanceRef oshift_13_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_10_ "localbus_rdata<10>") + (joined + (portRef (member localbus_rdata 21)) + (portRef I0 (instanceRef oshift_12_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_9_ "localbus_rdata<9>") + (joined + (portRef (member localbus_rdata 22)) + (portRef I0 (instanceRef oshift_11_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_8_ "localbus_rdata<8>") + (joined + (portRef (member localbus_rdata 23)) + (portRef I0 (instanceRef oshift_10_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_7_ "localbus_rdata<7>") + (joined + (portRef (member localbus_rdata 24)) + (portRef I0 (instanceRef oshift_9_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_6_ "localbus_rdata<6>") + (joined + (portRef (member localbus_rdata 25)) + (portRef I0 (instanceRef oshift_8_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_5_ "localbus_rdata<5>") + (joined + (portRef (member localbus_rdata 26)) + (portRef I0 (instanceRef oshift_7_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_4_ "localbus_rdata<4>") + (joined + (portRef (member localbus_rdata 27)) + (portRef I0 (instanceRef oshift_6_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_3_ "localbus_rdata<3>") + (joined + (portRef (member localbus_rdata 28)) + (portRef I0 (instanceRef oshift_5_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_2_ "localbus_rdata<2>") + (joined + (portRef (member localbus_rdata 29)) + (portRef I0 (instanceRef oshift_4_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_1_ "localbus_rdata<1>") + (joined + (portRef (member localbus_rdata 30)) + (portRef I0 (instanceRef oshift_3_rstpot_SW1)) + ) + ) + (net (rename localbus_rdata_0_ "localbus_rdata<0>") + (joined + (portRef (member localbus_rdata 31)) + (portRef I2 (instanceRef oshift_2_rstpot_SW1)) + ) + ) + (net clk + (joined + (portRef clk) + (portRef C (instanceRef localbus_wvalid_renamed_0)) + (portRef C (instanceRef localbus_rvalid_renamed_1)) + (portRef C (instanceRef wdata_0)) + (portRef C (instanceRef wdata_1)) + (portRef C (instanceRef wdata_2)) + (portRef C (instanceRef wdata_3)) + (portRef C (instanceRef wdata_4)) + (portRef C (instanceRef wdata_5)) + (portRef C (instanceRef wdata_6)) + (portRef C (instanceRef wdata_7)) + (portRef C (instanceRef wdata_8)) + (portRef C (instanceRef wdata_9)) + (portRef C (instanceRef wdata_10)) + (portRef C (instanceRef wdata_11)) + (portRef C (instanceRef wdata_12)) + (portRef C (instanceRef wdata_13)) + (portRef C (instanceRef wdata_14)) + (portRef C (instanceRef wdata_15)) + (portRef C (instanceRef wdata_16)) + (portRef C (instanceRef wdata_17)) + (portRef C (instanceRef wdata_18)) + (portRef C (instanceRef wdata_19)) + (portRef C (instanceRef wdata_20)) + (portRef C (instanceRef wdata_21)) + (portRef C (instanceRef wdata_22)) + (portRef C (instanceRef wdata_23)) + (portRef C (instanceRef wdata_24)) + (portRef C (instanceRef wdata_25)) + (portRef C (instanceRef wdata_26)) + (portRef C (instanceRef wdata_27)) + (portRef C (instanceRef wdata_28)) + (portRef C (instanceRef wdata_29)) + (portRef C (instanceRef wdata_30)) + (portRef C (instanceRef wdata_31)) + (portRef C (instanceRef iwr_valid_renamed_2)) + (portRef C (instanceRef ird_valid_renamed_3)) + (portRef C (instanceRef cmd_0)) + (portRef C (instanceRef cmd_1)) + (portRef C (instanceRef cmd_2)) + (portRef C (instanceRef cmd_3)) + (portRef C (instanceRef cmd_4)) + (portRef C (instanceRef cmd_5)) + (portRef C (instanceRef cmd_6)) + (portRef C (instanceRef cmd_7)) + (portRef C (instanceRef icrab_data_0)) + (portRef C (instanceRef icrab_data_1)) + (portRef C (instanceRef icrab_data_2)) + (portRef C (instanceRef icrab_data_3)) + (portRef C (instanceRef icrab_data_4)) + (portRef C (instanceRef icrab_data_5)) + (portRef C (instanceRef icrab_data_6)) + (portRef C (instanceRef icrab_data_7)) + (portRef C (instanceRef icrab_data_8)) + (portRef C (instanceRef icrab_data_9)) + (portRef C (instanceRef icrab_data_10)) + (portRef C (instanceRef icrab_data_11)) + (portRef C (instanceRef icrab_data_12)) + (portRef C (instanceRef icrab_data_13)) + (portRef C (instanceRef icrab_data_14)) + (portRef C (instanceRef icrab_data_15)) + (portRef C (instanceRef icrab_data_16)) + (portRef C (instanceRef icrab_data_17)) + (portRef C (instanceRef icrab_data_18)) + (portRef C (instanceRef icrab_data_19)) + (portRef C (instanceRef icrab_data_20)) + (portRef C (instanceRef icrab_data_21)) + (portRef C (instanceRef icrab_data_22)) + (portRef C (instanceRef icrab_data_23)) + (portRef C (instanceRef icrab_data_24)) + (portRef C (instanceRef icrab_data_25)) + (portRef C (instanceRef icrab_data_26)) + (portRef C (instanceRef icrab_data_27)) + (portRef C (instanceRef icrab_data_28)) + (portRef C (instanceRef icrab_data_29)) + (portRef C (instanceRef icrab_data_30)) + (portRef C (instanceRef icrab_data_31)) + (portRef C (instanceRef icmd_rd_0)) + (portRef C (instanceRef icmd_rd_1)) + (portRef C (instanceRef localbus_wmask_0)) + (portRef C (instanceRef localbus_wmask_1)) + (portRef C (instanceRef localbus_wmask_2)) + (portRef C (instanceRef localbus_wmask_3)) + (portRef C (instanceRef addr_0)) + (portRef C (instanceRef addr_1)) + (portRef C (instanceRef addr_2)) + (portRef C (instanceRef addr_3)) + (portRef C (instanceRef addr_4)) + (portRef C (instanceRef addr_5)) + (portRef C (instanceRef addr_6)) + (portRef C (instanceRef addr_7)) + (portRef C (instanceRef addr_8)) + (portRef C (instanceRef addr_9)) + (portRef C (instanceRef addr_10)) + (portRef C (instanceRef addr_11)) + (portRef C (instanceRef addr_12)) + (portRef C (instanceRef addr_13)) + (portRef C (instanceRef addr_14)) + (portRef C (instanceRef addr_15)) + (portRef C (instanceRef addr_16)) + (portRef C (instanceRef addr_17)) + (portRef C (instanceRef addr_18)) + (portRef C (instanceRef addr_19)) + (portRef C (instanceRef addr_20)) + (portRef C (instanceRef addr_21)) + (portRef C (instanceRef addr_22)) + (portRef C (instanceRef addr_23)) + (portRef C (instanceRef addr_24)) + (portRef C (instanceRef addr_25)) + (portRef C (instanceRef addr_26)) + (portRef C (instanceRef addr_27)) + (portRef C (instanceRef addr_28)) + (portRef C (instanceRef addr_29)) + (portRef C (instanceRef addr_30)) + (portRef C (instanceRef addr_31)) + (portRef C (instanceRef localbus_wdata_0)) + (portRef C (instanceRef localbus_wdata_1)) + (portRef C (instanceRef localbus_wdata_2)) + (portRef C (instanceRef localbus_wdata_3)) + (portRef C (instanceRef localbus_wdata_4)) + (portRef C (instanceRef localbus_wdata_5)) + (portRef C (instanceRef localbus_wdata_6)) + (portRef C (instanceRef localbus_wdata_7)) + (portRef C (instanceRef localbus_wdata_8)) + (portRef C (instanceRef localbus_wdata_9)) + (portRef C (instanceRef localbus_wdata_10)) + (portRef C (instanceRef localbus_wdata_11)) + (portRef C (instanceRef localbus_wdata_12)) + (portRef C (instanceRef localbus_wdata_13)) + (portRef C (instanceRef localbus_wdata_14)) + (portRef C (instanceRef localbus_wdata_15)) + (portRef C (instanceRef localbus_wdata_16)) + (portRef C (instanceRef localbus_wdata_17)) + (portRef C (instanceRef localbus_wdata_18)) + (portRef C (instanceRef localbus_wdata_19)) + (portRef C (instanceRef localbus_wdata_20)) + (portRef C (instanceRef localbus_wdata_21)) + (portRef C (instanceRef localbus_wdata_22)) + (portRef C (instanceRef localbus_wdata_23)) + (portRef C (instanceRef localbus_wdata_24)) + (portRef C (instanceRef localbus_wdata_25)) + (portRef C (instanceRef localbus_wdata_26)) + (portRef C (instanceRef localbus_wdata_27)) + (portRef C (instanceRef localbus_wdata_28)) + (portRef C (instanceRef localbus_wdata_29)) + (portRef C (instanceRef localbus_wdata_30)) + (portRef C (instanceRef localbus_wdata_31)) + (portRef C (instanceRef localbus_raddr_0)) + (portRef C (instanceRef localbus_raddr_1)) + (portRef C (instanceRef localbus_raddr_2)) + (portRef C (instanceRef localbus_raddr_3)) + (portRef C (instanceRef localbus_raddr_4)) + (portRef C (instanceRef localbus_raddr_5)) + (portRef C (instanceRef localbus_raddr_6)) + (portRef C (instanceRef localbus_raddr_7)) + (portRef C (instanceRef localbus_raddr_8)) + (portRef C (instanceRef localbus_raddr_9)) + (portRef C (instanceRef localbus_raddr_10)) + (portRef C (instanceRef localbus_raddr_11)) + (portRef C (instanceRef localbus_raddr_12)) + (portRef C (instanceRef localbus_raddr_13)) + (portRef C (instanceRef localbus_raddr_14)) + (portRef C (instanceRef localbus_raddr_15)) + (portRef C (instanceRef localbus_raddr_16)) + (portRef C (instanceRef localbus_raddr_17)) + (portRef C (instanceRef localbus_raddr_18)) + (portRef C (instanceRef localbus_raddr_19)) + (portRef C (instanceRef localbus_raddr_20)) + (portRef C (instanceRef localbus_raddr_21)) + (portRef C (instanceRef localbus_raddr_22)) + (portRef C (instanceRef localbus_raddr_23)) + (portRef C (instanceRef localbus_raddr_24)) + (portRef C (instanceRef localbus_raddr_25)) + (portRef C (instanceRef localbus_raddr_26)) + (portRef C (instanceRef localbus_raddr_27)) + (portRef C (instanceRef localbus_raddr_28)) + (portRef C (instanceRef localbus_raddr_29)) + (portRef C (instanceRef localbus_raddr_30)) + (portRef C (instanceRef localbus_raddr_31)) + (portRef C (instanceRef localbus_waddr_0)) + (portRef C (instanceRef localbus_waddr_1)) + (portRef C (instanceRef localbus_waddr_2)) + (portRef C (instanceRef localbus_waddr_3)) + (portRef C (instanceRef localbus_waddr_4)) + (portRef C (instanceRef localbus_waddr_5)) + (portRef C (instanceRef localbus_waddr_6)) + (portRef C (instanceRef localbus_waddr_7)) + (portRef C (instanceRef localbus_waddr_8)) + (portRef C (instanceRef localbus_waddr_9)) + (portRef C (instanceRef localbus_waddr_10)) + (portRef C (instanceRef localbus_waddr_11)) + (portRef C (instanceRef localbus_waddr_12)) + (portRef C (instanceRef localbus_waddr_13)) + (portRef C (instanceRef localbus_waddr_14)) + (portRef C (instanceRef localbus_waddr_15)) + (portRef C (instanceRef localbus_waddr_16)) + (portRef C (instanceRef localbus_waddr_17)) + (portRef C (instanceRef localbus_waddr_18)) + (portRef C (instanceRef localbus_waddr_19)) + (portRef C (instanceRef localbus_waddr_20)) + (portRef C (instanceRef localbus_waddr_21)) + (portRef C (instanceRef localbus_waddr_22)) + (portRef C (instanceRef localbus_waddr_23)) + (portRef C (instanceRef localbus_waddr_24)) + (portRef C (instanceRef localbus_waddr_25)) + (portRef C (instanceRef localbus_waddr_26)) + (portRef C (instanceRef localbus_waddr_27)) + (portRef C (instanceRef localbus_waddr_28)) + (portRef C (instanceRef localbus_waddr_29)) + (portRef C (instanceRef localbus_waddr_30)) + (portRef C (instanceRef localbus_waddr_31)) + (portRef C (instanceRef dop1949_r_0)) + (portRef C (instanceRef dop1949_r_1)) + (portRef C (instanceRef dop_clk_r_0)) + (portRef C (instanceRef dop_clk_r_1)) + (portRef C (instanceRef dop_clk_r_2)) + (portRef C (instanceRef dop_clk_r_3)) + (portRef C (instanceRef chip_r_0)) + (portRef C (instanceRef chip_r_1)) + (portRef C (instanceRef chip_r_2)) + (portRef C (instanceRef ishift_cnt_0)) + (portRef C (instanceRef ishift_cnt_1)) + (portRef C (instanceRef ishift_cnt_2)) + (portRef C (instanceRef ishift_cnt_3)) + (portRef C (instanceRef ishift_cnt_4)) + (portRef C (instanceRef ishift_cnt_5)) + (portRef C (instanceRef ishift_cnt_6)) + (portRef C (instanceRef ishift_cnt_7)) + (portRef C (instanceRef dop1950_r_0_renamed_5)) + (portRef C (instanceRef oshift_0)) + (portRef C (instanceRef oshift_1)) + (portRef C (instanceRef oshift_2)) + (portRef C (instanceRef oshift_3)) + (portRef C (instanceRef oshift_4)) + (portRef C (instanceRef oshift_5)) + (portRef C (instanceRef oshift_6)) + (portRef C (instanceRef oshift_7)) + (portRef C (instanceRef oshift_8)) + (portRef C (instanceRef oshift_9)) + (portRef C (instanceRef oshift_10)) + (portRef C (instanceRef oshift_11)) + (portRef C (instanceRef oshift_12)) + (portRef C (instanceRef oshift_13)) + (portRef C (instanceRef oshift_14)) + (portRef C (instanceRef oshift_15)) + (portRef C (instanceRef oshift_16)) + (portRef C (instanceRef oshift_17)) + (portRef C (instanceRef oshift_18)) + (portRef C (instanceRef oshift_19)) + (portRef C (instanceRef oshift_20)) + (portRef C (instanceRef oshift_21)) + (portRef C (instanceRef oshift_22)) + (portRef C (instanceRef oshift_23)) + (portRef C (instanceRef oshift_24)) + (portRef C (instanceRef oshift_25)) + (portRef C (instanceRef oshift_26)) + (portRef C (instanceRef oshift_27)) + (portRef C (instanceRef oshift_28)) + (portRef C (instanceRef oshift_29)) + (portRef C (instanceRef oshift_30)) + (portRef C (instanceRef oshift_31)) + (portRef C (instanceRef oshift_32)) + (portRef C (instanceRef oshift_33)) + (portRef C (instanceRef dop_clk_r_1_1_renamed_44)) + ) + ) + (net rst + (joined + (portRef rst) + (portRef CLR (instanceRef localbus_wvalid_renamed_0)) + (portRef CLR (instanceRef localbus_rvalid_renamed_1)) + (portRef CLR (instanceRef wdata_0)) + (portRef CLR (instanceRef wdata_1)) + (portRef CLR (instanceRef wdata_2)) + (portRef CLR (instanceRef wdata_3)) + (portRef CLR (instanceRef wdata_4)) + (portRef CLR (instanceRef wdata_5)) + (portRef CLR (instanceRef wdata_6)) + (portRef CLR (instanceRef wdata_7)) + (portRef CLR (instanceRef wdata_8)) + (portRef CLR (instanceRef wdata_9)) + (portRef CLR (instanceRef wdata_10)) + (portRef CLR (instanceRef wdata_11)) + (portRef CLR (instanceRef wdata_12)) + (portRef CLR (instanceRef wdata_13)) + (portRef CLR (instanceRef wdata_14)) + (portRef CLR (instanceRef wdata_15)) + (portRef CLR (instanceRef wdata_16)) + (portRef CLR (instanceRef wdata_17)) + (portRef CLR (instanceRef wdata_18)) + (portRef CLR (instanceRef wdata_19)) + (portRef CLR (instanceRef wdata_20)) + (portRef CLR (instanceRef wdata_21)) + (portRef CLR (instanceRef wdata_22)) + (portRef CLR (instanceRef wdata_23)) + (portRef CLR (instanceRef wdata_24)) + (portRef CLR (instanceRef wdata_25)) + (portRef CLR (instanceRef wdata_26)) + (portRef CLR (instanceRef wdata_27)) + (portRef CLR (instanceRef wdata_28)) + (portRef CLR (instanceRef wdata_29)) + (portRef CLR (instanceRef wdata_30)) + (portRef CLR (instanceRef wdata_31)) + (portRef CLR (instanceRef iwr_valid_renamed_2)) + (portRef CLR (instanceRef ird_valid_renamed_3)) + (portRef CLR (instanceRef cmd_0)) + (portRef CLR (instanceRef cmd_1)) + (portRef CLR (instanceRef cmd_2)) + (portRef CLR (instanceRef cmd_3)) + (portRef CLR (instanceRef cmd_4)) + (portRef CLR (instanceRef cmd_5)) + (portRef CLR (instanceRef cmd_6)) + (portRef CLR (instanceRef cmd_7)) + (portRef CLR (instanceRef icrab_data_0)) + (portRef CLR (instanceRef icrab_data_1)) + (portRef CLR (instanceRef icrab_data_2)) + (portRef CLR (instanceRef icrab_data_3)) + (portRef CLR (instanceRef icrab_data_4)) + (portRef CLR (instanceRef icrab_data_5)) + (portRef CLR (instanceRef icrab_data_6)) + (portRef CLR (instanceRef icrab_data_7)) + (portRef CLR (instanceRef icrab_data_8)) + (portRef CLR (instanceRef icrab_data_9)) + (portRef CLR (instanceRef icrab_data_10)) + (portRef CLR (instanceRef icrab_data_11)) + (portRef CLR (instanceRef icrab_data_12)) + (portRef CLR (instanceRef icrab_data_13)) + (portRef CLR (instanceRef icrab_data_14)) + (portRef CLR (instanceRef icrab_data_15)) + (portRef CLR (instanceRef icrab_data_16)) + (portRef CLR (instanceRef icrab_data_17)) + (portRef CLR (instanceRef icrab_data_18)) + (portRef CLR (instanceRef icrab_data_19)) + (portRef CLR (instanceRef icrab_data_20)) + (portRef CLR (instanceRef icrab_data_21)) + (portRef CLR (instanceRef icrab_data_22)) + (portRef CLR (instanceRef icrab_data_23)) + (portRef CLR (instanceRef icrab_data_24)) + (portRef CLR (instanceRef icrab_data_25)) + (portRef CLR (instanceRef icrab_data_26)) + (portRef CLR (instanceRef icrab_data_27)) + (portRef CLR (instanceRef icrab_data_28)) + (portRef CLR (instanceRef icrab_data_29)) + (portRef CLR (instanceRef icrab_data_30)) + (portRef CLR (instanceRef icrab_data_31)) + (portRef CLR (instanceRef localbus_wmask_0)) + (portRef CLR (instanceRef localbus_wmask_1)) + (portRef CLR (instanceRef localbus_wmask_2)) + (portRef CLR (instanceRef localbus_wmask_3)) + (portRef CLR (instanceRef addr_0)) + (portRef CLR (instanceRef addr_1)) + (portRef CLR (instanceRef addr_2)) + (portRef CLR (instanceRef addr_3)) + (portRef CLR (instanceRef addr_4)) + (portRef CLR (instanceRef addr_5)) + (portRef CLR (instanceRef addr_6)) + (portRef CLR (instanceRef addr_7)) + (portRef CLR (instanceRef addr_8)) + (portRef CLR (instanceRef addr_9)) + (portRef CLR (instanceRef addr_10)) + (portRef CLR (instanceRef addr_11)) + (portRef CLR (instanceRef addr_12)) + (portRef CLR (instanceRef addr_13)) + (portRef CLR (instanceRef addr_14)) + (portRef CLR (instanceRef addr_15)) + (portRef CLR (instanceRef addr_16)) + (portRef CLR (instanceRef addr_17)) + (portRef CLR (instanceRef addr_18)) + (portRef CLR (instanceRef addr_19)) + (portRef CLR (instanceRef addr_20)) + (portRef CLR (instanceRef addr_21)) + (portRef CLR (instanceRef addr_22)) + (portRef CLR (instanceRef addr_23)) + (portRef CLR (instanceRef addr_24)) + (portRef CLR (instanceRef addr_25)) + (portRef CLR (instanceRef addr_26)) + (portRef CLR (instanceRef addr_27)) + (portRef CLR (instanceRef addr_28)) + (portRef CLR (instanceRef addr_29)) + (portRef CLR (instanceRef addr_30)) + (portRef CLR (instanceRef addr_31)) + (portRef CLR (instanceRef localbus_wdata_0)) + (portRef CLR (instanceRef localbus_wdata_1)) + (portRef CLR (instanceRef localbus_wdata_2)) + (portRef CLR (instanceRef localbus_wdata_3)) + (portRef CLR (instanceRef localbus_wdata_4)) + (portRef CLR (instanceRef localbus_wdata_5)) + (portRef CLR (instanceRef localbus_wdata_6)) + (portRef CLR (instanceRef localbus_wdata_7)) + (portRef CLR (instanceRef localbus_wdata_8)) + (portRef CLR (instanceRef localbus_wdata_9)) + (portRef CLR (instanceRef localbus_wdata_10)) + (portRef CLR (instanceRef localbus_wdata_11)) + (portRef CLR (instanceRef localbus_wdata_12)) + (portRef CLR (instanceRef localbus_wdata_13)) + (portRef CLR (instanceRef localbus_wdata_14)) + (portRef CLR (instanceRef localbus_wdata_15)) + (portRef CLR (instanceRef localbus_wdata_16)) + (portRef CLR (instanceRef localbus_wdata_17)) + (portRef CLR (instanceRef localbus_wdata_18)) + (portRef CLR (instanceRef localbus_wdata_19)) + (portRef CLR (instanceRef localbus_wdata_20)) + (portRef CLR (instanceRef localbus_wdata_21)) + (portRef CLR (instanceRef localbus_wdata_22)) + (portRef CLR (instanceRef localbus_wdata_23)) + (portRef CLR (instanceRef localbus_wdata_24)) + (portRef CLR (instanceRef localbus_wdata_25)) + (portRef CLR (instanceRef localbus_wdata_26)) + (portRef CLR (instanceRef localbus_wdata_27)) + (portRef CLR (instanceRef localbus_wdata_28)) + (portRef CLR (instanceRef localbus_wdata_29)) + (portRef CLR (instanceRef localbus_wdata_30)) + (portRef CLR (instanceRef localbus_wdata_31)) + (portRef CLR (instanceRef localbus_raddr_0)) + (portRef CLR (instanceRef localbus_raddr_1)) + (portRef CLR (instanceRef localbus_raddr_2)) + (portRef CLR (instanceRef localbus_raddr_3)) + (portRef CLR (instanceRef localbus_raddr_4)) + (portRef CLR (instanceRef localbus_raddr_5)) + (portRef CLR (instanceRef localbus_raddr_6)) + (portRef CLR (instanceRef localbus_raddr_7)) + (portRef CLR (instanceRef localbus_raddr_8)) + (portRef CLR (instanceRef localbus_raddr_9)) + (portRef CLR (instanceRef localbus_raddr_10)) + (portRef CLR (instanceRef localbus_raddr_11)) + (portRef CLR (instanceRef localbus_raddr_12)) + (portRef CLR (instanceRef localbus_raddr_13)) + (portRef CLR (instanceRef localbus_raddr_14)) + (portRef CLR (instanceRef localbus_raddr_15)) + (portRef CLR (instanceRef localbus_raddr_16)) + (portRef CLR (instanceRef localbus_raddr_17)) + (portRef CLR (instanceRef localbus_raddr_18)) + (portRef CLR (instanceRef localbus_raddr_19)) + (portRef CLR (instanceRef localbus_raddr_20)) + (portRef CLR (instanceRef localbus_raddr_21)) + (portRef CLR (instanceRef localbus_raddr_22)) + (portRef CLR (instanceRef localbus_raddr_23)) + (portRef CLR (instanceRef localbus_raddr_24)) + (portRef CLR (instanceRef localbus_raddr_25)) + (portRef CLR (instanceRef localbus_raddr_26)) + (portRef CLR (instanceRef localbus_raddr_27)) + (portRef CLR (instanceRef localbus_raddr_28)) + (portRef CLR (instanceRef localbus_raddr_29)) + (portRef CLR (instanceRef localbus_raddr_30)) + (portRef CLR (instanceRef localbus_raddr_31)) + (portRef CLR (instanceRef localbus_waddr_0)) + (portRef CLR (instanceRef localbus_waddr_1)) + (portRef CLR (instanceRef localbus_waddr_2)) + (portRef CLR (instanceRef localbus_waddr_3)) + (portRef CLR (instanceRef localbus_waddr_4)) + (portRef CLR (instanceRef localbus_waddr_5)) + (portRef CLR (instanceRef localbus_waddr_6)) + (portRef CLR (instanceRef localbus_waddr_7)) + (portRef CLR (instanceRef localbus_waddr_8)) + (portRef CLR (instanceRef localbus_waddr_9)) + (portRef CLR (instanceRef localbus_waddr_10)) + (portRef CLR (instanceRef localbus_waddr_11)) + (portRef CLR (instanceRef localbus_waddr_12)) + (portRef CLR (instanceRef localbus_waddr_13)) + (portRef CLR (instanceRef localbus_waddr_14)) + (portRef CLR (instanceRef localbus_waddr_15)) + (portRef CLR (instanceRef localbus_waddr_16)) + (portRef CLR (instanceRef localbus_waddr_17)) + (portRef CLR (instanceRef localbus_waddr_18)) + (portRef CLR (instanceRef localbus_waddr_19)) + (portRef CLR (instanceRef localbus_waddr_20)) + (portRef CLR (instanceRef localbus_waddr_21)) + (portRef CLR (instanceRef localbus_waddr_22)) + (portRef CLR (instanceRef localbus_waddr_23)) + (portRef CLR (instanceRef localbus_waddr_24)) + (portRef CLR (instanceRef localbus_waddr_25)) + (portRef CLR (instanceRef localbus_waddr_26)) + (portRef CLR (instanceRef localbus_waddr_27)) + (portRef CLR (instanceRef localbus_waddr_28)) + (portRef CLR (instanceRef localbus_waddr_29)) + (portRef CLR (instanceRef localbus_waddr_30)) + (portRef CLR (instanceRef localbus_waddr_31)) + (portRef CLR (instanceRef dop1949_r_0)) + (portRef CLR (instanceRef dop1949_r_1)) + (portRef CLR (instanceRef dop_clk_r_0)) + (portRef CLR (instanceRef dop_clk_r_1)) + (portRef CLR (instanceRef dop_clk_r_2)) + (portRef CLR (instanceRef dop_clk_r_3)) + (portRef CLR (instanceRef chip_r_0)) + (portRef CLR (instanceRef chip_r_1)) + (portRef CLR (instanceRef chip_r_2)) + (portRef CLR (instanceRef ishift_cnt_0)) + (portRef CLR (instanceRef ishift_cnt_1)) + (portRef CLR (instanceRef ishift_cnt_2)) + (portRef CLR (instanceRef ishift_cnt_3)) + (portRef CLR (instanceRef ishift_cnt_4)) + (portRef CLR (instanceRef ishift_cnt_5)) + (portRef CLR (instanceRef ishift_cnt_6)) + (portRef CLR (instanceRef ishift_cnt_7)) + (portRef CLR (instanceRef dop1950_r_0_renamed_5)) + (portRef CLR (instanceRef oshift_0)) + (portRef CLR (instanceRef oshift_1)) + (portRef CLR (instanceRef oshift_2)) + (portRef CLR (instanceRef oshift_3)) + (portRef CLR (instanceRef oshift_4)) + (portRef CLR (instanceRef oshift_5)) + (portRef CLR (instanceRef oshift_6)) + (portRef CLR (instanceRef oshift_7)) + (portRef CLR (instanceRef oshift_8)) + (portRef CLR (instanceRef oshift_9)) + (portRef CLR (instanceRef oshift_10)) + (portRef CLR (instanceRef oshift_11)) + (portRef CLR (instanceRef oshift_12)) + (portRef CLR (instanceRef oshift_13)) + (portRef CLR (instanceRef oshift_14)) + (portRef CLR (instanceRef oshift_15)) + (portRef CLR (instanceRef oshift_16)) + (portRef CLR (instanceRef oshift_17)) + (portRef CLR (instanceRef oshift_18)) + (portRef CLR (instanceRef oshift_19)) + (portRef CLR (instanceRef oshift_20)) + (portRef CLR (instanceRef oshift_21)) + (portRef CLR (instanceRef oshift_22)) + (portRef CLR (instanceRef oshift_23)) + (portRef CLR (instanceRef oshift_24)) + (portRef CLR (instanceRef oshift_25)) + (portRef CLR (instanceRef oshift_26)) + (portRef CLR (instanceRef oshift_27)) + (portRef CLR (instanceRef oshift_28)) + (portRef CLR (instanceRef oshift_29)) + (portRef CLR (instanceRef oshift_30)) + (portRef CLR (instanceRef oshift_31)) + (portRef CLR (instanceRef oshift_32)) + (portRef CLR (instanceRef oshift_33)) + (portRef I0 (instanceRef &_n0206_inv1_rstpot_renamed_41)) + (portRef CLR (instanceRef dop_clk_r_1_1_renamed_44)) + ) + ) + (net (rename dop1949_r_0_ "dop1949_r<0>") + (joined + (portRef Q (instanceRef dop1949_r_0)) + (portRef D (instanceRef dop1949_r_1)) + ) + ) + (net (rename dop1949_r_1_ "dop1949_r<1>") + (joined + (portRef D (instanceRef wdata_31)) + (portRef Q (instanceRef dop1949_r_1)) + ) + ) + (net (rename dop_clk_r_2_ "dop_clk_r<2>") + (joined + (portRef Q (instanceRef dop_clk_r_2)) + (portRef D (instanceRef dop_clk_r_3)) + (portRef I0 (instanceRef dop_clk_r_2__dop_clk_r_1__AND_3_o1)) + (portRef I2 (instanceRef &_n0186_inv1)) + (portRef I3 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_renamed_4)) + (portRef I1 (instanceRef &_n0202_inv_SW2)) + (portRef I1 (instanceRef &_n0198_inv1_SW0)) + (portRef I1 (instanceRef &_n0198_inv1_SW1)) + (portRef I2 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW2)) + (portRef I3 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW1)) + (portRef I1 (instanceRef oshift_33_rstpot_renamed_6)) + (portRef I1 (instanceRef oshift_2_rstpot_renamed_8)) + (portRef I1 (instanceRef oshift_3_rstpot_renamed_9)) + (portRef I1 (instanceRef oshift_4_rstpot_renamed_10)) + (portRef I1 (instanceRef oshift_5_rstpot_renamed_11)) + (portRef I1 (instanceRef oshift_6_rstpot_renamed_12)) + (portRef I1 (instanceRef oshift_7_rstpot_renamed_13)) + (portRef I1 (instanceRef oshift_8_rstpot_renamed_14)) + (portRef I1 (instanceRef oshift_9_rstpot_renamed_15)) + (portRef I1 (instanceRef oshift_10_rstpot_renamed_16)) + (portRef I1 (instanceRef oshift_11_rstpot_renamed_17)) + (portRef I1 (instanceRef oshift_12_rstpot_renamed_18)) + (portRef I1 (instanceRef oshift_13_rstpot_renamed_19)) + (portRef I1 (instanceRef oshift_14_rstpot_renamed_20)) + (portRef I1 (instanceRef oshift_15_rstpot_renamed_21)) + (portRef I1 (instanceRef oshift_16_rstpot_renamed_22)) + (portRef I1 (instanceRef oshift_17_rstpot_renamed_23)) + (portRef I1 (instanceRef oshift_18_rstpot_renamed_24)) + (portRef I1 (instanceRef oshift_19_rstpot_renamed_25)) + (portRef I1 (instanceRef oshift_20_rstpot_renamed_26)) + (portRef I1 (instanceRef oshift_21_rstpot_renamed_27)) + (portRef I1 (instanceRef oshift_22_rstpot_renamed_28)) + (portRef I1 (instanceRef oshift_23_rstpot_renamed_29)) + (portRef I1 (instanceRef oshift_24_rstpot_renamed_30)) + (portRef I1 (instanceRef oshift_25_rstpot_renamed_31)) + (portRef I1 (instanceRef oshift_26_rstpot_renamed_32)) + (portRef I1 (instanceRef oshift_27_rstpot_renamed_33)) + (portRef I1 (instanceRef oshift_28_rstpot_renamed_34)) + (portRef I1 (instanceRef oshift_29_rstpot_renamed_35)) + (portRef I1 (instanceRef oshift_30_rstpot_renamed_36)) + (portRef I1 (instanceRef oshift_31_rstpot_renamed_37)) + (portRef I1 (instanceRef oshift_32_rstpot_renamed_38)) + ) + ) + (net (rename dop_clk_r_1_ "dop_clk_r<1>") + (joined + (portRef Q (instanceRef dop_clk_r_1)) + (portRef D (instanceRef dop_clk_r_2)) + (portRef I1 (instanceRef dop_clk_r_2__dop_clk_r_1__AND_3_o1)) + (portRef I1 (instanceRef &_n0186_inv1)) + (portRef I2 (instanceRef &_n0202_inv_SW2)) + (portRef I2 (instanceRef &_n0198_inv1_SW0)) + (portRef I2 (instanceRef &_n0198_inv1_SW1)) + (portRef I2 (instanceRef oshift_33_rstpot_renamed_6)) + (portRef I2 (instanceRef oshift_2_rstpot_SW0)) + (portRef I2 (instanceRef oshift_3_rstpot_SW0)) + (portRef I2 (instanceRef oshift_4_rstpot_SW0)) + (portRef I2 (instanceRef oshift_5_rstpot_SW0)) + (portRef I2 (instanceRef oshift_6_rstpot_SW0)) + (portRef I2 (instanceRef oshift_7_rstpot_SW0)) + (portRef I2 (instanceRef oshift_8_rstpot_SW0)) + (portRef I2 (instanceRef oshift_9_rstpot_SW0)) + (portRef I2 (instanceRef oshift_10_rstpot_SW0)) + (portRef I2 (instanceRef oshift_11_rstpot_SW0)) + (portRef I2 (instanceRef oshift_12_rstpot_SW0)) + (portRef I2 (instanceRef oshift_13_rstpot_SW0)) + (portRef I2 (instanceRef oshift_14_rstpot_SW0)) + (portRef I2 (instanceRef oshift_15_rstpot_SW0)) + (portRef I2 (instanceRef oshift_16_rstpot_SW0)) + (portRef I2 (instanceRef oshift_17_rstpot_SW0)) + (portRef I2 (instanceRef oshift_18_rstpot_SW0)) + (portRef I2 (instanceRef oshift_19_rstpot_SW0)) + (portRef I2 (instanceRef oshift_20_rstpot_SW0)) + (portRef I2 (instanceRef oshift_21_rstpot_SW0)) + (portRef I2 (instanceRef oshift_22_rstpot_SW0)) + (portRef I2 (instanceRef oshift_23_rstpot_SW0)) + (portRef I2 (instanceRef oshift_24_rstpot_SW0)) + (portRef I2 (instanceRef oshift_25_rstpot_SW0)) + (portRef I2 (instanceRef oshift_26_rstpot_SW0)) + (portRef I2 (instanceRef oshift_27_rstpot_SW0)) + (portRef I2 (instanceRef oshift_28_rstpot_SW0)) + (portRef I2 (instanceRef oshift_29_rstpot_SW0)) + (portRef I2 (instanceRef oshift_30_rstpot_SW0)) + (portRef I2 (instanceRef oshift_31_rstpot_SW0)) + (portRef I2 (instanceRef oshift_32_rstpot_SW0)) + ) + ) + (net (rename dop_clk_r_0_ "dop_clk_r<0>") + (joined + (portRef Q (instanceRef dop_clk_r_0)) + (portRef D (instanceRef dop_clk_r_1)) + (portRef D (instanceRef dop_clk_r_1_1_renamed_44)) + ) + ) + (net (rename dop_clk_r_3_ "dop_clk_r<3>") + (joined + (portRef Q (instanceRef dop_clk_r_3)) + (portRef I0 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o1_SW0_SW0)) + (portRef I4 (instanceRef &_n0206_inv1_rstpot_renamed_41)) + ) + ) + (net (rename chip_r_1_ "chip_r<1>") + (joined + (portRef Q (instanceRef chip_r_1)) + (portRef D (instanceRef chip_r_2)) + (portRef I0 (instanceRef Mcount_ishift_cnt_lut_0__)) + (portRef I0 (instanceRef Mcount_ishift_cnt_lut_1__)) + (portRef I0 (instanceRef Mcount_ishift_cnt_lut_2__)) + (portRef I0 (instanceRef Mcount_ishift_cnt_lut_3__)) + (portRef I0 (instanceRef Mcount_ishift_cnt_lut_4__)) + (portRef I0 (instanceRef Mcount_ishift_cnt_lut_5__)) + (portRef I0 (instanceRef Mcount_ishift_cnt_lut_6__)) + (portRef I0 (instanceRef Mcount_ishift_cnt_lut_7__)) + (portRef I0 (instanceRef Mmux_GND_1_o_cmd_1__MUX_42_o11)) + (portRef I0 (instanceRef &_n0186_inv1)) + (portRef I1 (instanceRef &_n0206_inv1_rstpot_renamed_41)) + (portRef I4 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW2)) + (portRef I (instanceRef chip_r_1__inv1_INV_0)) + ) + ) + (net (rename chip_r_2_ "chip_r<2>") + (joined + (portRef Q (instanceRef chip_r_2)) + (portRef I2 (instanceRef Mmux_GND_1_o_cmd_1__MUX_42_o11)) + ) + ) + (net (rename chip_r_0_ "chip_r<0>") + (joined + (portRef Q (instanceRef chip_r_0)) + (portRef D (instanceRef chip_r_1)) + ) + ) + (net iwr_valid + (joined + (portRef Q (instanceRef iwr_valid_renamed_2)) + (portRef CE (instanceRef localbus_wmask_0)) + (portRef CE (instanceRef localbus_wmask_1)) + (portRef CE (instanceRef localbus_wmask_2)) + (portRef CE (instanceRef localbus_wmask_3)) + (portRef I1 (instanceRef &_n0173_inv1)) + (portRef I0 (instanceRef &_n0181_inv1)) + (portRef I0 (instanceRef &_n0177_inv1)) + ) + ) + (net localbus_wvalid + (joined + (portRef localbus_wvalid) + (portRef Q (instanceRef localbus_wvalid_renamed_0)) + ) + ) + (net ird_valid + (joined + (portRef Q (instanceRef ird_valid_renamed_3)) + (portRef I0 (instanceRef ird_valid_icmd_rd_1__AND_11_o1)) + (portRef I0 (instanceRef ird_valid_ishift_data_71__AND_10_o1)) + ) + ) + (net localbus_rvalid + (joined + (portRef localbus_rvalid) + (portRef Q (instanceRef localbus_rvalid_renamed_1)) + ) + ) + (net (rename localbus_wmask_3_ "localbus_wmask<3>") + (joined + (portRef (member localbus_wmask 0)) + (portRef Q (instanceRef localbus_wmask_3)) + ) + ) + (net (rename localbus_wmask_2_ "localbus_wmask<2>") + (joined + (portRef (member localbus_wmask 1)) + (portRef Q (instanceRef localbus_wmask_2)) + ) + ) + (net (rename localbus_wmask_1_ "localbus_wmask<1>") + (joined + (portRef (member localbus_wmask 2)) + (portRef Q (instanceRef localbus_wmask_1)) + ) + ) + (net (rename localbus_wmask_0_ "localbus_wmask<0>") + (joined + (portRef (member localbus_wmask 3)) + (portRef Q (instanceRef localbus_wmask_0)) + ) + ) + (net (rename addr_31_ "addr<31>") + (joined + (portRef D (instanceRef addr_30)) + (portRef Q (instanceRef addr_31)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_31_xo_0_1)) + ) + ) + (net (rename addr_30_ "addr<30>") + (joined + (portRef D (instanceRef addr_29)) + (portRef Q (instanceRef addr_30)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_30_xo_0_1)) + ) + ) + (net (rename addr_29_ "addr<29>") + (joined + (portRef D (instanceRef addr_28)) + (portRef Q (instanceRef addr_29)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_29_xo_0_1)) + ) + ) + (net (rename addr_28_ "addr<28>") + (joined + (portRef D (instanceRef addr_27)) + (portRef Q (instanceRef addr_28)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_28_xo_0_1)) + ) + ) + (net (rename addr_27_ "addr<27>") + (joined + (portRef D (instanceRef addr_26)) + (portRef Q (instanceRef addr_27)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_27_xo_0_1)) + ) + ) + (net (rename addr_26_ "addr<26>") + (joined + (portRef D (instanceRef addr_25)) + (portRef Q (instanceRef addr_26)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_26_xo_0_1)) + ) + ) + (net (rename addr_25_ "addr<25>") + (joined + (portRef D (instanceRef addr_24)) + (portRef Q (instanceRef addr_25)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_25_xo_0_1)) + ) + ) + (net (rename addr_24_ "addr<24>") + (joined + (portRef D (instanceRef addr_23)) + (portRef Q (instanceRef addr_24)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_24_xo_0_1)) + ) + ) + (net (rename addr_23_ "addr<23>") + (joined + (portRef D (instanceRef addr_22)) + (portRef Q (instanceRef addr_23)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_23_xo_0_1)) + ) + ) + (net (rename addr_22_ "addr<22>") + (joined + (portRef D (instanceRef addr_21)) + (portRef Q (instanceRef addr_22)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_22_xo_0_1)) + ) + ) + (net (rename addr_21_ "addr<21>") + (joined + (portRef D (instanceRef addr_20)) + (portRef Q (instanceRef addr_21)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_21_xo_0_1)) + ) + ) + (net (rename addr_20_ "addr<20>") + (joined + (portRef D (instanceRef addr_19)) + (portRef Q (instanceRef addr_20)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_20_xo_0_1)) + ) + ) + (net (rename addr_19_ "addr<19>") + (joined + (portRef D (instanceRef addr_18)) + (portRef Q (instanceRef addr_19)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_19_xo_0_1)) + ) + ) + (net (rename addr_18_ "addr<18>") + (joined + (portRef D (instanceRef addr_17)) + (portRef Q (instanceRef addr_18)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_18_xo_0_1)) + ) + ) + (net (rename addr_17_ "addr<17>") + (joined + (portRef D (instanceRef addr_16)) + (portRef Q (instanceRef addr_17)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_17_xo_0_1)) + ) + ) + (net (rename addr_16_ "addr<16>") + (joined + (portRef D (instanceRef addr_15)) + (portRef Q (instanceRef addr_16)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_16_xo_0_1)) + ) + ) + (net (rename addr_15_ "addr<15>") + (joined + (portRef D (instanceRef addr_14)) + (portRef Q (instanceRef addr_15)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_15_xo_0_1)) + ) + ) + (net (rename addr_14_ "addr<14>") + (joined + (portRef D (instanceRef addr_13)) + (portRef Q (instanceRef addr_14)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_14_xo_0_1)) + ) + ) + (net (rename addr_13_ "addr<13>") + (joined + (portRef D (instanceRef addr_12)) + (portRef Q (instanceRef addr_13)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_13_xo_0_1)) + ) + ) + (net (rename addr_12_ "addr<12>") + (joined + (portRef D (instanceRef addr_11)) + (portRef Q (instanceRef addr_12)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_12_xo_0_1)) + ) + ) + (net (rename addr_11_ "addr<11>") + (joined + (portRef D (instanceRef addr_10)) + (portRef Q (instanceRef addr_11)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_11_xo_0_1)) + ) + ) + (net (rename addr_10_ "addr<10>") + (joined + (portRef D (instanceRef addr_9)) + (portRef Q (instanceRef addr_10)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_10_xo_0_1)) + ) + ) + (net (rename addr_9_ "addr<9>") + (joined + (portRef D (instanceRef addr_8)) + (portRef Q (instanceRef addr_9)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_9_xo_0_1)) + ) + ) + (net (rename addr_8_ "addr<8>") + (joined + (portRef D (instanceRef addr_7)) + (portRef Q (instanceRef addr_8)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_8_xo_0_1)) + ) + ) + (net (rename addr_7_ "addr<7>") + (joined + (portRef D (instanceRef addr_6)) + (portRef Q (instanceRef addr_7)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_7_xo_0_1)) + ) + ) + (net (rename addr_6_ "addr<6>") + (joined + (portRef D (instanceRef addr_5)) + (portRef Q (instanceRef addr_6)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_6_xo_0_1)) + ) + ) + (net (rename addr_5_ "addr<5>") + (joined + (portRef D (instanceRef addr_4)) + (portRef Q (instanceRef addr_5)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_5_xo_0_1)) + ) + ) + (net (rename addr_4_ "addr<4>") + (joined + (portRef D (instanceRef addr_3)) + (portRef Q (instanceRef addr_4)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_4_xo_0_1)) + ) + ) + (net (rename addr_3_ "addr<3>") + (joined + (portRef D (instanceRef addr_2)) + (portRef Q (instanceRef addr_3)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_3_xo_0_1)) + ) + ) + (net (rename addr_2_ "addr<2>") + (joined + (portRef D (instanceRef addr_1)) + (portRef Q (instanceRef addr_2)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_2_xo_0_1)) + ) + ) + (net (rename addr_1_ "addr<1>") + (joined + (portRef D (instanceRef addr_0)) + (portRef Q (instanceRef addr_1)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_1_xo_0_1)) + ) + ) + (net (rename addr_0_ "addr<0>") + (joined + (portRef Q (instanceRef addr_0)) + (portRef I0 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_0_xo_0_1)) + ) + ) + (net (rename wdata_0_ "wdata<0>") + (joined + (portRef Q (instanceRef wdata_0)) + (portRef D (instanceRef cmd_7)) + (portRef D (instanceRef icrab_data_0)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_0_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_2_xo_0_1)) + ) + ) + (net (rename wdata_31_ "wdata<31>") + (joined + (portRef D (instanceRef wdata_30)) + (portRef Q (instanceRef wdata_31)) + (portRef D (instanceRef icrab_data_31)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_31_xo_0_1)) + (portRef I1 (instanceRef ird_valid_ishift_data_71__AND_10_o1)) + (portRef I1 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o1_SW0_SW0)) + (portRef I2 (instanceRef icmd_rd_1_dpot_renamed_43)) + ) + ) + (net (rename wdata_30_ "wdata<30>") + (joined + (portRef D (instanceRef wdata_29)) + (portRef Q (instanceRef wdata_30)) + (portRef D (instanceRef icrab_data_30)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_30_xo_0_1)) + (portRef I2 (instanceRef ird_valid_ishift_data_71__AND_10_o1)) + (portRef I2 (instanceRef icmd_rd_0_dpot_renamed_42)) + (portRef I5 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW2)) + ) + ) + (net (rename wdata_29_ "wdata<29>") + (joined + (portRef D (instanceRef wdata_28)) + (portRef Q (instanceRef wdata_29)) + (portRef D (instanceRef icrab_data_29)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_29_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_31_xo_0_1)) + ) + ) + (net (rename wdata_28_ "wdata<28>") + (joined + (portRef D (instanceRef wdata_27)) + (portRef Q (instanceRef wdata_28)) + (portRef D (instanceRef icrab_data_28)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_28_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_30_xo_0_1)) + ) + ) + (net (rename wdata_27_ "wdata<27>") + (joined + (portRef D (instanceRef wdata_26)) + (portRef Q (instanceRef wdata_27)) + (portRef D (instanceRef icrab_data_27)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_27_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_29_xo_0_1)) + ) + ) + (net (rename wdata_26_ "wdata<26>") + (joined + (portRef D (instanceRef wdata_25)) + (portRef Q (instanceRef wdata_26)) + (portRef D (instanceRef icrab_data_26)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_26_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_28_xo_0_1)) + ) + ) + (net (rename wdata_25_ "wdata<25>") + (joined + (portRef D (instanceRef wdata_24)) + (portRef Q (instanceRef wdata_25)) + (portRef D (instanceRef icrab_data_25)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_25_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_27_xo_0_1)) + ) + ) + (net (rename wdata_24_ "wdata<24>") + (joined + (portRef D (instanceRef wdata_23)) + (portRef Q (instanceRef wdata_24)) + (portRef D (instanceRef icrab_data_24)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_24_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_26_xo_0_1)) + ) + ) + (net (rename wdata_23_ "wdata<23>") + (joined + (portRef D (instanceRef wdata_22)) + (portRef Q (instanceRef wdata_23)) + (portRef D (instanceRef icrab_data_23)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_23_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_25_xo_0_1)) + ) + ) + (net (rename wdata_22_ "wdata<22>") + (joined + (portRef D (instanceRef wdata_21)) + (portRef Q (instanceRef wdata_22)) + (portRef D (instanceRef icrab_data_22)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_22_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_24_xo_0_1)) + ) + ) + (net (rename wdata_21_ "wdata<21>") + (joined + (portRef D (instanceRef wdata_20)) + (portRef Q (instanceRef wdata_21)) + (portRef D (instanceRef icrab_data_21)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_21_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_23_xo_0_1)) + ) + ) + (net (rename wdata_20_ "wdata<20>") + (joined + (portRef D (instanceRef wdata_19)) + (portRef Q (instanceRef wdata_20)) + (portRef D (instanceRef icrab_data_20)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_20_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_22_xo_0_1)) + ) + ) + (net (rename wdata_19_ "wdata<19>") + (joined + (portRef D (instanceRef wdata_18)) + (portRef Q (instanceRef wdata_19)) + (portRef D (instanceRef icrab_data_19)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_19_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_21_xo_0_1)) + ) + ) + (net (rename wdata_18_ "wdata<18>") + (joined + (portRef D (instanceRef wdata_17)) + (portRef Q (instanceRef wdata_18)) + (portRef D (instanceRef icrab_data_18)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_18_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_20_xo_0_1)) + ) + ) + (net (rename wdata_17_ "wdata<17>") + (joined + (portRef D (instanceRef wdata_16)) + (portRef Q (instanceRef wdata_17)) + (portRef D (instanceRef icrab_data_17)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_17_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_19_xo_0_1)) + ) + ) + (net (rename wdata_16_ "wdata<16>") + (joined + (portRef D (instanceRef wdata_15)) + (portRef Q (instanceRef wdata_16)) + (portRef D (instanceRef icrab_data_16)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_16_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_18_xo_0_1)) + ) + ) + (net (rename wdata_15_ "wdata<15>") + (joined + (portRef D (instanceRef wdata_14)) + (portRef Q (instanceRef wdata_15)) + (portRef D (instanceRef icrab_data_15)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_15_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_17_xo_0_1)) + ) + ) + (net (rename wdata_14_ "wdata<14>") + (joined + (portRef D (instanceRef wdata_13)) + (portRef Q (instanceRef wdata_14)) + (portRef D (instanceRef icrab_data_14)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_14_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_16_xo_0_1)) + ) + ) + (net (rename wdata_13_ "wdata<13>") + (joined + (portRef D (instanceRef wdata_12)) + (portRef Q (instanceRef wdata_13)) + (portRef D (instanceRef icrab_data_13)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_13_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_15_xo_0_1)) + ) + ) + (net (rename wdata_12_ "wdata<12>") + (joined + (portRef D (instanceRef wdata_11)) + (portRef Q (instanceRef wdata_12)) + (portRef D (instanceRef icrab_data_12)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_12_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_14_xo_0_1)) + ) + ) + (net (rename wdata_11_ "wdata<11>") + (joined + (portRef D (instanceRef wdata_10)) + (portRef Q (instanceRef wdata_11)) + (portRef D (instanceRef icrab_data_11)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_11_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_13_xo_0_1)) + ) + ) + (net (rename wdata_10_ "wdata<10>") + (joined + (portRef D (instanceRef wdata_9)) + (portRef Q (instanceRef wdata_10)) + (portRef D (instanceRef icrab_data_10)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_10_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_12_xo_0_1)) + ) + ) + (net (rename wdata_9_ "wdata<9>") + (joined + (portRef D (instanceRef wdata_8)) + (portRef Q (instanceRef wdata_9)) + (portRef D (instanceRef icrab_data_9)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_9_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_11_xo_0_1)) + ) + ) + (net (rename wdata_8_ "wdata<8>") + (joined + (portRef D (instanceRef wdata_7)) + (portRef Q (instanceRef wdata_8)) + (portRef D (instanceRef icrab_data_8)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_8_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_10_xo_0_1)) + ) + ) + (net (rename wdata_7_ "wdata<7>") + (joined + (portRef D (instanceRef wdata_6)) + (portRef Q (instanceRef wdata_7)) + (portRef D (instanceRef icrab_data_7)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_7_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_9_xo_0_1)) + ) + ) + (net (rename wdata_6_ "wdata<6>") + (joined + (portRef D (instanceRef wdata_5)) + (portRef Q (instanceRef wdata_6)) + (portRef D (instanceRef icrab_data_6)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_6_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_8_xo_0_1)) + ) + ) + (net (rename wdata_5_ "wdata<5>") + (joined + (portRef D (instanceRef wdata_4)) + (portRef Q (instanceRef wdata_5)) + (portRef D (instanceRef icrab_data_5)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_5_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_7_xo_0_1)) + ) + ) + (net (rename wdata_4_ "wdata<4>") + (joined + (portRef D (instanceRef wdata_3)) + (portRef Q (instanceRef wdata_4)) + (portRef D (instanceRef icrab_data_4)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_4_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_6_xo_0_1)) + ) + ) + (net (rename wdata_3_ "wdata<3>") + (joined + (portRef D (instanceRef wdata_2)) + (portRef Q (instanceRef wdata_3)) + (portRef D (instanceRef icrab_data_3)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_3_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_5_xo_0_1)) + ) + ) + (net (rename wdata_2_ "wdata<2>") + (joined + (portRef D (instanceRef wdata_1)) + (portRef Q (instanceRef wdata_2)) + (portRef D (instanceRef icrab_data_2)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_2_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_4_xo_0_1)) + ) + ) + (net (rename wdata_1_ "wdata<1>") + (joined + (portRef D (instanceRef wdata_0)) + (portRef Q (instanceRef wdata_1)) + (portRef D (instanceRef icrab_data_1)) + (portRef I1 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_1_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_3_xo_0_1)) + ) + ) + (net (rename localbus_waddr_31_ "localbus_waddr<31>") + (joined + (portRef (member localbus_waddr 0)) + (portRef Q (instanceRef localbus_waddr_31)) + ) + ) + (net (rename localbus_waddr_30_ "localbus_waddr<30>") + (joined + (portRef (member localbus_waddr 1)) + (portRef Q (instanceRef localbus_waddr_30)) + ) + ) + (net (rename localbus_waddr_29_ "localbus_waddr<29>") + (joined + (portRef (member localbus_waddr 2)) + (portRef Q (instanceRef localbus_waddr_29)) + ) + ) + (net (rename localbus_waddr_28_ "localbus_waddr<28>") + (joined + (portRef (member localbus_waddr 3)) + (portRef Q (instanceRef localbus_waddr_28)) + ) + ) + (net (rename localbus_waddr_27_ "localbus_waddr<27>") + (joined + (portRef (member localbus_waddr 4)) + (portRef Q (instanceRef localbus_waddr_27)) + ) + ) + (net (rename localbus_waddr_26_ "localbus_waddr<26>") + (joined + (portRef (member localbus_waddr 5)) + (portRef Q (instanceRef localbus_waddr_26)) + ) + ) + (net (rename localbus_waddr_25_ "localbus_waddr<25>") + (joined + (portRef (member localbus_waddr 6)) + (portRef Q (instanceRef localbus_waddr_25)) + ) + ) + (net (rename localbus_waddr_24_ "localbus_waddr<24>") + (joined + (portRef (member localbus_waddr 7)) + (portRef Q (instanceRef localbus_waddr_24)) + ) + ) + (net (rename localbus_waddr_23_ "localbus_waddr<23>") + (joined + (portRef (member localbus_waddr 8)) + (portRef Q (instanceRef localbus_waddr_23)) + ) + ) + (net (rename localbus_waddr_22_ "localbus_waddr<22>") + (joined + (portRef (member localbus_waddr 9)) + (portRef Q (instanceRef localbus_waddr_22)) + ) + ) + (net (rename localbus_waddr_21_ "localbus_waddr<21>") + (joined + (portRef (member localbus_waddr 10)) + (portRef Q (instanceRef localbus_waddr_21)) + ) + ) + (net (rename localbus_waddr_20_ "localbus_waddr<20>") + (joined + (portRef (member localbus_waddr 11)) + (portRef Q (instanceRef localbus_waddr_20)) + ) + ) + (net (rename localbus_waddr_19_ "localbus_waddr<19>") + (joined + (portRef (member localbus_waddr 12)) + (portRef Q (instanceRef localbus_waddr_19)) + ) + ) + (net (rename localbus_waddr_18_ "localbus_waddr<18>") + (joined + (portRef (member localbus_waddr 13)) + (portRef Q (instanceRef localbus_waddr_18)) + ) + ) + (net (rename localbus_waddr_17_ "localbus_waddr<17>") + (joined + (portRef (member localbus_waddr 14)) + (portRef Q (instanceRef localbus_waddr_17)) + ) + ) + (net (rename localbus_waddr_16_ "localbus_waddr<16>") + (joined + (portRef (member localbus_waddr 15)) + (portRef Q (instanceRef localbus_waddr_16)) + ) + ) + (net (rename localbus_waddr_15_ "localbus_waddr<15>") + (joined + (portRef (member localbus_waddr 16)) + (portRef Q (instanceRef localbus_waddr_15)) + ) + ) + (net (rename localbus_waddr_14_ "localbus_waddr<14>") + (joined + (portRef (member localbus_waddr 17)) + (portRef Q (instanceRef localbus_waddr_14)) + ) + ) + (net (rename localbus_waddr_13_ "localbus_waddr<13>") + (joined + (portRef (member localbus_waddr 18)) + (portRef Q (instanceRef localbus_waddr_13)) + ) + ) + (net (rename localbus_waddr_12_ "localbus_waddr<12>") + (joined + (portRef (member localbus_waddr 19)) + (portRef Q (instanceRef localbus_waddr_12)) + ) + ) + (net (rename localbus_waddr_11_ "localbus_waddr<11>") + (joined + (portRef (member localbus_waddr 20)) + (portRef Q (instanceRef localbus_waddr_11)) + ) + ) + (net (rename localbus_waddr_10_ "localbus_waddr<10>") + (joined + (portRef (member localbus_waddr 21)) + (portRef Q (instanceRef localbus_waddr_10)) + ) + ) + (net (rename localbus_waddr_9_ "localbus_waddr<9>") + (joined + (portRef (member localbus_waddr 22)) + (portRef Q (instanceRef localbus_waddr_9)) + ) + ) + (net (rename localbus_waddr_8_ "localbus_waddr<8>") + (joined + (portRef (member localbus_waddr 23)) + (portRef Q (instanceRef localbus_waddr_8)) + ) + ) + (net (rename localbus_waddr_7_ "localbus_waddr<7>") + (joined + (portRef (member localbus_waddr 24)) + (portRef Q (instanceRef localbus_waddr_7)) + ) + ) + (net (rename localbus_waddr_6_ "localbus_waddr<6>") + (joined + (portRef (member localbus_waddr 25)) + (portRef Q (instanceRef localbus_waddr_6)) + ) + ) + (net (rename localbus_waddr_5_ "localbus_waddr<5>") + (joined + (portRef (member localbus_waddr 26)) + (portRef Q (instanceRef localbus_waddr_5)) + ) + ) + (net (rename localbus_waddr_4_ "localbus_waddr<4>") + (joined + (portRef (member localbus_waddr 27)) + (portRef Q (instanceRef localbus_waddr_4)) + ) + ) + (net (rename localbus_waddr_3_ "localbus_waddr<3>") + (joined + (portRef (member localbus_waddr 28)) + (portRef Q (instanceRef localbus_waddr_3)) + ) + ) + (net (rename localbus_waddr_2_ "localbus_waddr<2>") + (joined + (portRef (member localbus_waddr 29)) + (portRef Q (instanceRef localbus_waddr_2)) + ) + ) + (net (rename localbus_waddr_1_ "localbus_waddr<1>") + (joined + (portRef (member localbus_waddr 30)) + (portRef Q (instanceRef localbus_waddr_1)) + ) + ) + (net (rename localbus_waddr_0_ "localbus_waddr<0>") + (joined + (portRef (member localbus_waddr 31)) + (portRef Q (instanceRef localbus_waddr_0)) + ) + ) + (net (rename localbus_wdata_31_ "localbus_wdata<31>") + (joined + (portRef (member localbus_wdata 0)) + (portRef Q (instanceRef localbus_wdata_31)) + ) + ) + (net (rename localbus_wdata_30_ "localbus_wdata<30>") + (joined + (portRef (member localbus_wdata 1)) + (portRef Q (instanceRef localbus_wdata_30)) + ) + ) + (net (rename localbus_wdata_29_ "localbus_wdata<29>") + (joined + (portRef (member localbus_wdata 2)) + (portRef Q (instanceRef localbus_wdata_29)) + ) + ) + (net (rename localbus_wdata_28_ "localbus_wdata<28>") + (joined + (portRef (member localbus_wdata 3)) + (portRef Q (instanceRef localbus_wdata_28)) + ) + ) + (net (rename localbus_wdata_27_ "localbus_wdata<27>") + (joined + (portRef (member localbus_wdata 4)) + (portRef Q (instanceRef localbus_wdata_27)) + ) + ) + (net (rename localbus_wdata_26_ "localbus_wdata<26>") + (joined + (portRef (member localbus_wdata 5)) + (portRef Q (instanceRef localbus_wdata_26)) + ) + ) + (net (rename localbus_wdata_25_ "localbus_wdata<25>") + (joined + (portRef (member localbus_wdata 6)) + (portRef Q (instanceRef localbus_wdata_25)) + ) + ) + (net (rename localbus_wdata_24_ "localbus_wdata<24>") + (joined + (portRef (member localbus_wdata 7)) + (portRef Q (instanceRef localbus_wdata_24)) + ) + ) + (net (rename localbus_wdata_23_ "localbus_wdata<23>") + (joined + (portRef (member localbus_wdata 8)) + (portRef Q (instanceRef localbus_wdata_23)) + ) + ) + (net (rename localbus_wdata_22_ "localbus_wdata<22>") + (joined + (portRef (member localbus_wdata 9)) + (portRef Q (instanceRef localbus_wdata_22)) + ) + ) + (net (rename localbus_wdata_21_ "localbus_wdata<21>") + (joined + (portRef (member localbus_wdata 10)) + (portRef Q (instanceRef localbus_wdata_21)) + ) + ) + (net (rename localbus_wdata_20_ "localbus_wdata<20>") + (joined + (portRef (member localbus_wdata 11)) + (portRef Q (instanceRef localbus_wdata_20)) + ) + ) + (net (rename localbus_wdata_19_ "localbus_wdata<19>") + (joined + (portRef (member localbus_wdata 12)) + (portRef Q (instanceRef localbus_wdata_19)) + ) + ) + (net (rename localbus_wdata_18_ "localbus_wdata<18>") + (joined + (portRef (member localbus_wdata 13)) + (portRef Q (instanceRef localbus_wdata_18)) + ) + ) + (net (rename localbus_wdata_17_ "localbus_wdata<17>") + (joined + (portRef (member localbus_wdata 14)) + (portRef Q (instanceRef localbus_wdata_17)) + ) + ) + (net (rename localbus_wdata_16_ "localbus_wdata<16>") + (joined + (portRef (member localbus_wdata 15)) + (portRef Q (instanceRef localbus_wdata_16)) + ) + ) + (net (rename localbus_wdata_15_ "localbus_wdata<15>") + (joined + (portRef (member localbus_wdata 16)) + (portRef Q (instanceRef localbus_wdata_15)) + ) + ) + (net (rename localbus_wdata_14_ "localbus_wdata<14>") + (joined + (portRef (member localbus_wdata 17)) + (portRef Q (instanceRef localbus_wdata_14)) + ) + ) + (net (rename localbus_wdata_13_ "localbus_wdata<13>") + (joined + (portRef (member localbus_wdata 18)) + (portRef Q (instanceRef localbus_wdata_13)) + ) + ) + (net (rename localbus_wdata_12_ "localbus_wdata<12>") + (joined + (portRef (member localbus_wdata 19)) + (portRef Q (instanceRef localbus_wdata_12)) + ) + ) + (net (rename localbus_wdata_11_ "localbus_wdata<11>") + (joined + (portRef (member localbus_wdata 20)) + (portRef Q (instanceRef localbus_wdata_11)) + ) + ) + (net (rename localbus_wdata_10_ "localbus_wdata<10>") + (joined + (portRef (member localbus_wdata 21)) + (portRef Q (instanceRef localbus_wdata_10)) + ) + ) + (net (rename localbus_wdata_9_ "localbus_wdata<9>") + (joined + (portRef (member localbus_wdata 22)) + (portRef Q (instanceRef localbus_wdata_9)) + ) + ) + (net (rename localbus_wdata_8_ "localbus_wdata<8>") + (joined + (portRef (member localbus_wdata 23)) + (portRef Q (instanceRef localbus_wdata_8)) + ) + ) + (net (rename localbus_wdata_7_ "localbus_wdata<7>") + (joined + (portRef (member localbus_wdata 24)) + (portRef Q (instanceRef localbus_wdata_7)) + ) + ) + (net (rename localbus_wdata_6_ "localbus_wdata<6>") + (joined + (portRef (member localbus_wdata 25)) + (portRef Q (instanceRef localbus_wdata_6)) + ) + ) + (net (rename localbus_wdata_5_ "localbus_wdata<5>") + (joined + (portRef (member localbus_wdata 26)) + (portRef Q (instanceRef localbus_wdata_5)) + ) + ) + (net (rename localbus_wdata_4_ "localbus_wdata<4>") + (joined + (portRef (member localbus_wdata 27)) + (portRef Q (instanceRef localbus_wdata_4)) + ) + ) + (net (rename localbus_wdata_3_ "localbus_wdata<3>") + (joined + (portRef (member localbus_wdata 28)) + (portRef Q (instanceRef localbus_wdata_3)) + ) + ) + (net (rename localbus_wdata_2_ "localbus_wdata<2>") + (joined + (portRef (member localbus_wdata 29)) + (portRef Q (instanceRef localbus_wdata_2)) + ) + ) + (net (rename localbus_wdata_1_ "localbus_wdata<1>") + (joined + (portRef (member localbus_wdata 30)) + (portRef Q (instanceRef localbus_wdata_1)) + ) + ) + (net (rename localbus_wdata_0_ "localbus_wdata<0>") + (joined + (portRef (member localbus_wdata 31)) + (portRef Q (instanceRef localbus_wdata_0)) + ) + ) + (net (rename icrab_data_31_ "icrab_data<31>") + (joined + (portRef Q (instanceRef icrab_data_31)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_31_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_31_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_31_xo_0_1)) + (portRef I2 (instanceRef oshift_33_rstpot_SW0)) + ) + ) + (net (rename icrab_data_30_ "icrab_data<30>") + (joined + (portRef Q (instanceRef icrab_data_30)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_30_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_30_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_30_xo_0_1)) + (portRef I2 (instanceRef oshift_32_rstpot_SW1)) + ) + ) + (net (rename icrab_data_29_ "icrab_data<29>") + (joined + (portRef Q (instanceRef icrab_data_29)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_29_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_29_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_29_xo_0_1)) + (portRef I2 (instanceRef oshift_31_rstpot_SW1)) + ) + ) + (net (rename icrab_data_28_ "icrab_data<28>") + (joined + (portRef Q (instanceRef icrab_data_28)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_28_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_28_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_28_xo_0_1)) + (portRef I2 (instanceRef oshift_30_rstpot_SW1)) + ) + ) + (net (rename icrab_data_27_ "icrab_data<27>") + (joined + (portRef Q (instanceRef icrab_data_27)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_27_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_27_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_27_xo_0_1)) + (portRef I2 (instanceRef oshift_29_rstpot_SW1)) + ) + ) + (net (rename icrab_data_26_ "icrab_data<26>") + (joined + (portRef Q (instanceRef icrab_data_26)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_26_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_26_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_26_xo_0_1)) + (portRef I2 (instanceRef oshift_28_rstpot_SW1)) + ) + ) + (net (rename icrab_data_25_ "icrab_data<25>") + (joined + (portRef Q (instanceRef icrab_data_25)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_25_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_25_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_25_xo_0_1)) + (portRef I2 (instanceRef oshift_27_rstpot_SW1)) + ) + ) + (net (rename icrab_data_24_ "icrab_data<24>") + (joined + (portRef Q (instanceRef icrab_data_24)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_24_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_24_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_24_xo_0_1)) + (portRef I2 (instanceRef oshift_26_rstpot_SW1)) + ) + ) + (net (rename icrab_data_23_ "icrab_data<23>") + (joined + (portRef Q (instanceRef icrab_data_23)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_23_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_23_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_23_xo_0_1)) + (portRef I2 (instanceRef oshift_25_rstpot_SW1)) + ) + ) + (net (rename icrab_data_22_ "icrab_data<22>") + (joined + (portRef Q (instanceRef icrab_data_22)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_22_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_22_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_22_xo_0_1)) + (portRef I2 (instanceRef oshift_24_rstpot_SW1)) + ) + ) + (net (rename icrab_data_21_ "icrab_data<21>") + (joined + (portRef Q (instanceRef icrab_data_21)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_21_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_21_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_21_xo_0_1)) + (portRef I2 (instanceRef oshift_23_rstpot_SW1)) + ) + ) + (net (rename icrab_data_20_ "icrab_data<20>") + (joined + (portRef Q (instanceRef icrab_data_20)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_20_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_20_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_20_xo_0_1)) + (portRef I2 (instanceRef oshift_22_rstpot_SW1)) + ) + ) + (net (rename icrab_data_19_ "icrab_data<19>") + (joined + (portRef Q (instanceRef icrab_data_19)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_19_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_19_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_19_xo_0_1)) + (portRef I2 (instanceRef oshift_21_rstpot_SW1)) + ) + ) + (net (rename icrab_data_18_ "icrab_data<18>") + (joined + (portRef Q (instanceRef icrab_data_18)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_18_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_18_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_18_xo_0_1)) + (portRef I2 (instanceRef oshift_20_rstpot_SW1)) + ) + ) + (net (rename icrab_data_17_ "icrab_data<17>") + (joined + (portRef Q (instanceRef icrab_data_17)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_17_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_17_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_17_xo_0_1)) + (portRef I2 (instanceRef oshift_19_rstpot_SW1)) + ) + ) + (net (rename icrab_data_16_ "icrab_data<16>") + (joined + (portRef Q (instanceRef icrab_data_16)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_16_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_16_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_16_xo_0_1)) + (portRef I2 (instanceRef oshift_18_rstpot_SW1)) + ) + ) + (net (rename icrab_data_15_ "icrab_data<15>") + (joined + (portRef Q (instanceRef icrab_data_15)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_15_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_15_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_15_xo_0_1)) + (portRef I2 (instanceRef oshift_17_rstpot_SW1)) + ) + ) + (net (rename icrab_data_14_ "icrab_data<14>") + (joined + (portRef Q (instanceRef icrab_data_14)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_14_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_14_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_14_xo_0_1)) + (portRef I2 (instanceRef oshift_16_rstpot_SW1)) + ) + ) + (net (rename icrab_data_13_ "icrab_data<13>") + (joined + (portRef Q (instanceRef icrab_data_13)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_13_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_13_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_13_xo_0_1)) + (portRef I2 (instanceRef oshift_15_rstpot_SW1)) + ) + ) + (net (rename icrab_data_12_ "icrab_data<12>") + (joined + (portRef Q (instanceRef icrab_data_12)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_12_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_12_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_12_xo_0_1)) + (portRef I2 (instanceRef oshift_14_rstpot_SW1)) + ) + ) + (net (rename icrab_data_11_ "icrab_data<11>") + (joined + (portRef Q (instanceRef icrab_data_11)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_11_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_11_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_11_xo_0_1)) + (portRef I2 (instanceRef oshift_13_rstpot_SW1)) + ) + ) + (net (rename icrab_data_10_ "icrab_data<10>") + (joined + (portRef Q (instanceRef icrab_data_10)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_10_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_10_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_10_xo_0_1)) + (portRef I2 (instanceRef oshift_12_rstpot_SW1)) + ) + ) + (net (rename icrab_data_9_ "icrab_data<9>") + (joined + (portRef Q (instanceRef icrab_data_9)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_9_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_9_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_9_xo_0_1)) + (portRef I2 (instanceRef oshift_11_rstpot_SW1)) + ) + ) + (net (rename icrab_data_8_ "icrab_data<8>") + (joined + (portRef Q (instanceRef icrab_data_8)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_8_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_8_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_8_xo_0_1)) + (portRef I2 (instanceRef oshift_10_rstpot_SW1)) + ) + ) + (net (rename icrab_data_7_ "icrab_data<7>") + (joined + (portRef Q (instanceRef icrab_data_7)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_7_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_7_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_7_xo_0_1)) + (portRef I2 (instanceRef oshift_9_rstpot_SW1)) + ) + ) + (net (rename icrab_data_6_ "icrab_data<6>") + (joined + (portRef Q (instanceRef icrab_data_6)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_6_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_6_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_6_xo_0_1)) + (portRef I2 (instanceRef oshift_8_rstpot_SW1)) + ) + ) + (net (rename icrab_data_5_ "icrab_data<5>") + (joined + (portRef Q (instanceRef icrab_data_5)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_5_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_5_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_5_xo_0_1)) + (portRef I2 (instanceRef oshift_7_rstpot_SW1)) + ) + ) + (net (rename icrab_data_4_ "icrab_data<4>") + (joined + (portRef Q (instanceRef icrab_data_4)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_4_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_4_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_4_xo_0_1)) + (portRef I2 (instanceRef oshift_6_rstpot_SW1)) + ) + ) + (net (rename icrab_data_3_ "icrab_data<3>") + (joined + (portRef Q (instanceRef icrab_data_3)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_3_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_3_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_3_xo_0_1)) + (portRef I2 (instanceRef oshift_5_rstpot_SW1)) + ) + ) + (net (rename icrab_data_2_ "icrab_data<2>") + (joined + (portRef Q (instanceRef icrab_data_2)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_2_xo_0_1)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_2_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_2_xo_0_1)) + (portRef I2 (instanceRef oshift_4_rstpot_SW1)) + ) + ) + (net (rename icrab_data_1_ "icrab_data<1>") + (joined + (portRef Q (instanceRef icrab_data_1)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_1_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_1_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_1_xo_0_1)) + (portRef I2 (instanceRef oshift_3_rstpot_SW1)) + ) + ) + (net (rename icrab_data_0_ "icrab_data<0>") + (joined + (portRef Q (instanceRef icrab_data_0)) + (portRef I0 (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_0_xo_0_1)) + (portRef I1 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_0_xo_0_1)) + (portRef I1 (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_0_xo_0_1)) + (portRef I0 (instanceRef oshift_2_rstpot_SW1)) + ) + ) + (net (rename localbus_raddr_31_ "localbus_raddr<31>") + (joined + (portRef (member localbus_raddr 0)) + (portRef Q (instanceRef localbus_raddr_31)) + ) + ) + (net (rename localbus_raddr_30_ "localbus_raddr<30>") + (joined + (portRef (member localbus_raddr 1)) + (portRef Q (instanceRef localbus_raddr_30)) + ) + ) + (net (rename localbus_raddr_29_ "localbus_raddr<29>") + (joined + (portRef (member localbus_raddr 2)) + (portRef Q (instanceRef localbus_raddr_29)) + ) + ) + (net (rename localbus_raddr_28_ "localbus_raddr<28>") + (joined + (portRef (member localbus_raddr 3)) + (portRef Q (instanceRef localbus_raddr_28)) + ) + ) + (net (rename localbus_raddr_27_ "localbus_raddr<27>") + (joined + (portRef (member localbus_raddr 4)) + (portRef Q (instanceRef localbus_raddr_27)) + ) + ) + (net (rename localbus_raddr_26_ "localbus_raddr<26>") + (joined + (portRef (member localbus_raddr 5)) + (portRef Q (instanceRef localbus_raddr_26)) + ) + ) + (net (rename localbus_raddr_25_ "localbus_raddr<25>") + (joined + (portRef (member localbus_raddr 6)) + (portRef Q (instanceRef localbus_raddr_25)) + ) + ) + (net (rename localbus_raddr_24_ "localbus_raddr<24>") + (joined + (portRef (member localbus_raddr 7)) + (portRef Q (instanceRef localbus_raddr_24)) + ) + ) + (net (rename localbus_raddr_23_ "localbus_raddr<23>") + (joined + (portRef (member localbus_raddr 8)) + (portRef Q (instanceRef localbus_raddr_23)) + ) + ) + (net (rename localbus_raddr_22_ "localbus_raddr<22>") + (joined + (portRef (member localbus_raddr 9)) + (portRef Q (instanceRef localbus_raddr_22)) + ) + ) + (net (rename localbus_raddr_21_ "localbus_raddr<21>") + (joined + (portRef (member localbus_raddr 10)) + (portRef Q (instanceRef localbus_raddr_21)) + ) + ) + (net (rename localbus_raddr_20_ "localbus_raddr<20>") + (joined + (portRef (member localbus_raddr 11)) + (portRef Q (instanceRef localbus_raddr_20)) + ) + ) + (net (rename localbus_raddr_19_ "localbus_raddr<19>") + (joined + (portRef (member localbus_raddr 12)) + (portRef Q (instanceRef localbus_raddr_19)) + ) + ) + (net (rename localbus_raddr_18_ "localbus_raddr<18>") + (joined + (portRef (member localbus_raddr 13)) + (portRef Q (instanceRef localbus_raddr_18)) + ) + ) + (net (rename localbus_raddr_17_ "localbus_raddr<17>") + (joined + (portRef (member localbus_raddr 14)) + (portRef Q (instanceRef localbus_raddr_17)) + ) + ) + (net (rename localbus_raddr_16_ "localbus_raddr<16>") + (joined + (portRef (member localbus_raddr 15)) + (portRef Q (instanceRef localbus_raddr_16)) + ) + ) + (net (rename localbus_raddr_15_ "localbus_raddr<15>") + (joined + (portRef (member localbus_raddr 16)) + (portRef Q (instanceRef localbus_raddr_15)) + ) + ) + (net (rename localbus_raddr_14_ "localbus_raddr<14>") + (joined + (portRef (member localbus_raddr 17)) + (portRef Q (instanceRef localbus_raddr_14)) + ) + ) + (net (rename localbus_raddr_13_ "localbus_raddr<13>") + (joined + (portRef (member localbus_raddr 18)) + (portRef Q (instanceRef localbus_raddr_13)) + ) + ) + (net (rename localbus_raddr_12_ "localbus_raddr<12>") + (joined + (portRef (member localbus_raddr 19)) + (portRef Q (instanceRef localbus_raddr_12)) + ) + ) + (net (rename localbus_raddr_11_ "localbus_raddr<11>") + (joined + (portRef (member localbus_raddr 20)) + (portRef Q (instanceRef localbus_raddr_11)) + ) + ) + (net (rename localbus_raddr_10_ "localbus_raddr<10>") + (joined + (portRef (member localbus_raddr 21)) + (portRef Q (instanceRef localbus_raddr_10)) + ) + ) + (net (rename localbus_raddr_9_ "localbus_raddr<9>") + (joined + (portRef (member localbus_raddr 22)) + (portRef Q (instanceRef localbus_raddr_9)) + ) + ) + (net (rename localbus_raddr_8_ "localbus_raddr<8>") + (joined + (portRef (member localbus_raddr 23)) + (portRef Q (instanceRef localbus_raddr_8)) + ) + ) + (net (rename localbus_raddr_7_ "localbus_raddr<7>") + (joined + (portRef (member localbus_raddr 24)) + (portRef Q (instanceRef localbus_raddr_7)) + ) + ) + (net (rename localbus_raddr_6_ "localbus_raddr<6>") + (joined + (portRef (member localbus_raddr 25)) + (portRef Q (instanceRef localbus_raddr_6)) + ) + ) + (net (rename localbus_raddr_5_ "localbus_raddr<5>") + (joined + (portRef (member localbus_raddr 26)) + (portRef Q (instanceRef localbus_raddr_5)) + ) + ) + (net (rename localbus_raddr_4_ "localbus_raddr<4>") + (joined + (portRef (member localbus_raddr 27)) + (portRef Q (instanceRef localbus_raddr_4)) + ) + ) + (net (rename localbus_raddr_3_ "localbus_raddr<3>") + (joined + (portRef (member localbus_raddr 28)) + (portRef Q (instanceRef localbus_raddr_3)) + ) + ) + (net (rename localbus_raddr_2_ "localbus_raddr<2>") + (joined + (portRef (member localbus_raddr 29)) + (portRef Q (instanceRef localbus_raddr_2)) + ) + ) + (net (rename localbus_raddr_1_ "localbus_raddr<1>") + (joined + (portRef (member localbus_raddr 30)) + (portRef Q (instanceRef localbus_raddr_1)) + ) + ) + (net (rename localbus_raddr_0_ "localbus_raddr<0>") + (joined + (portRef (member localbus_raddr 31)) + (portRef Q (instanceRef localbus_raddr_0)) + ) + ) + (net (rename cmd_7_ "cmd<7>") + (joined + (portRef D (instanceRef cmd_6)) + (portRef Q (instanceRef cmd_7)) + (portRef D (instanceRef localbus_wmask_3)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_1_xo_0_1)) + ) + ) + (net (rename cmd_6_ "cmd<6>") + (joined + (portRef D (instanceRef cmd_5)) + (portRef Q (instanceRef cmd_6)) + (portRef D (instanceRef localbus_wmask_2)) + (portRef I0 (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_0_xo_0_1)) + ) + ) + (net (rename cmd_5_ "cmd<5>") + (joined + (portRef D (instanceRef cmd_4)) + (portRef Q (instanceRef cmd_5)) + (portRef D (instanceRef localbus_wmask_1)) + ) + ) + (net (rename cmd_4_ "cmd<4>") + (joined + (portRef D (instanceRef cmd_3)) + (portRef Q (instanceRef cmd_4)) + (portRef D (instanceRef localbus_wmask_0)) + ) + ) + (net (rename cmd_0_ "cmd<0>") + (joined + (portRef Q (instanceRef cmd_0)) + (portRef D (instanceRef addr_31)) + (portRef I0 (instanceRef &_n0173_inv1)) + (portRef I2 (instanceRef &_n0181_inv1)) + (portRef I1 (instanceRef &_n0177_inv1)) + ) + ) + (net (rename cmd_3_ "cmd<3>") + (joined + (portRef D (instanceRef cmd_2)) + (portRef Q (instanceRef cmd_3)) + ) + ) + (net (rename cmd_2_ "cmd<2>") + (joined + (portRef D (instanceRef cmd_1)) + (portRef Q (instanceRef cmd_2)) + ) + ) + (net (rename cmd_1_ "cmd<1>") + (joined + (portRef D (instanceRef cmd_0)) + (portRef Q (instanceRef cmd_1)) + (portRef I2 (instanceRef &_n0173_inv1)) + (portRef I1 (instanceRef &_n0181_inv1)) + (portRef I1 (instanceRef Mmux_GND_1_o_cmd_1__MUX_42_o11)) + (portRef I2 (instanceRef &_n0177_inv1)) + ) + ) + (net (rename ishift_cnt_7_ "ishift_cnt<7>") + (joined + (portRef I1 (instanceRef Mcount_ishift_cnt_lut_7__)) + (portRef Q (instanceRef ishift_cnt_7)) + (portRef I1 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW0)) + (portRef I1 (instanceRef &_n0202_inv_SW1)) + (portRef I1 (instanceRef dop1950_r_0_rstpot_renamed_7)) + ) + ) + (net (rename ishift_cnt_6_ "ishift_cnt<6>") + (joined + (portRef I1 (instanceRef Mcount_ishift_cnt_lut_6__)) + (portRef Q (instanceRef ishift_cnt_6)) + (portRef I0 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW0)) + (portRef I2 (instanceRef dop1950_r_0_rstpot_renamed_7)) + (portRef I0 (instanceRef &_n0202_inv_SW1)) + ) + ) + (net (rename ishift_cnt_5_ "ishift_cnt<5>") + (joined + (portRef I1 (instanceRef Mcount_ishift_cnt_lut_5__)) + (portRef Q (instanceRef ishift_cnt_5)) + (portRef I4 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_renamed_4)) + (portRef I5 (instanceRef &_n0202_inv_SW0)) + (portRef I1 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o1)) + (portRef I3 (instanceRef dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + ) + ) + (net (rename ishift_cnt_4_ "ishift_cnt<4>") + (joined + (portRef I1 (instanceRef Mcount_ishift_cnt_lut_4__)) + (portRef Q (instanceRef ishift_cnt_4)) + (portRef I1 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_renamed_4)) + (portRef I1 (instanceRef &_n0202_inv_SW0)) + (portRef I2 (instanceRef dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + (portRef I3 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o1)) + ) + ) + (net (rename ishift_cnt_3_ "ishift_cnt<3>") + (joined + (portRef I1 (instanceRef Mcount_ishift_cnt_lut_3__)) + (portRef Q (instanceRef ishift_cnt_3)) + (portRef I2 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_renamed_4)) + (portRef I0 (instanceRef &_n0202_inv_SW0)) + (portRef I4 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o1)) + (portRef I1 (instanceRef dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + ) + ) + (net (rename ishift_cnt_2_ "ishift_cnt<2>") + (joined + (portRef I1 (instanceRef Mcount_ishift_cnt_lut_2__)) + (portRef Q (instanceRef ishift_cnt_2)) + (portRef I4 (instanceRef &_n0202_inv_SW0)) + (portRef I2 (instanceRef &_n0206_inv1_rstpot_renamed_41)) + (portRef I3 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW2)) + (portRef I1 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW1)) + ) + ) + (net (rename ishift_cnt_1_ "ishift_cnt<1>") + (joined + (portRef I1 (instanceRef Mcount_ishift_cnt_lut_1__)) + (portRef Q (instanceRef ishift_cnt_1)) + (portRef I2 (instanceRef &_n0202_inv_SW0)) + (portRef I2 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW1)) + (portRef I3 (instanceRef &_n0206_inv1_rstpot_renamed_41)) + (portRef I0 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW2)) + ) + ) + (net (rename ishift_cnt_0_ "ishift_cnt<0>") + (joined + (portRef I1 (instanceRef Mcount_ishift_cnt_lut_0__)) + (portRef Q (instanceRef ishift_cnt_0)) + (portRef I0 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_renamed_4)) + (portRef I3 (instanceRef &_n0202_inv_SW0)) + (portRef I1 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW2)) + (portRef I0 (instanceRef dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + ) + ) + (net (rename oshift_0_ "oshift<0>") + (joined + (portRef Q (instanceRef oshift_0)) + (portRef I3 (instanceRef &_n0202_inv_SW2)) + (portRef I0 (instanceRef &_n0198_inv1_SW0)) + (portRef I0 (instanceRef oshift_0_rstpot_renamed_39)) + ) + ) + (net (rename oshift_33_ "oshift<33>") + (joined + (portRef Q (instanceRef oshift_33)) + (portRef I1 (instanceRef oshift_33_rstpot_SW0)) + (portRef I0 (instanceRef oshift_33_rstpot_renamed_6)) + (portRef I0 (instanceRef oshift_32_rstpot_SW0)) + ) + ) + (net (rename oshift_32_ "oshift<32>") + (joined + (portRef Q (instanceRef oshift_32)) + (portRef I1 (instanceRef oshift_31_rstpot_SW0)) + (portRef I1 (instanceRef oshift_32_rstpot_SW0)) + (portRef I1 (instanceRef oshift_32_rstpot_SW1)) + (portRef I0 (instanceRef oshift_32_rstpot_renamed_38)) + ) + ) + (net (rename oshift_31_ "oshift<31>") + (joined + (portRef Q (instanceRef oshift_31)) + (portRef I1 (instanceRef oshift_30_rstpot_SW0)) + (portRef I0 (instanceRef oshift_31_rstpot_SW0)) + (portRef I1 (instanceRef oshift_31_rstpot_SW1)) + (portRef I0 (instanceRef oshift_31_rstpot_renamed_37)) + ) + ) + (net (rename oshift_30_ "oshift<30>") + (joined + (portRef Q (instanceRef oshift_30)) + (portRef I1 (instanceRef oshift_29_rstpot_SW0)) + (portRef I0 (instanceRef oshift_30_rstpot_SW0)) + (portRef I1 (instanceRef oshift_30_rstpot_SW1)) + (portRef I0 (instanceRef oshift_30_rstpot_renamed_36)) + ) + ) + (net (rename oshift_29_ "oshift<29>") + (joined + (portRef Q (instanceRef oshift_29)) + (portRef I1 (instanceRef oshift_28_rstpot_SW0)) + (portRef I0 (instanceRef oshift_29_rstpot_SW0)) + (portRef I1 (instanceRef oshift_29_rstpot_SW1)) + (portRef I0 (instanceRef oshift_29_rstpot_renamed_35)) + ) + ) + (net (rename oshift_28_ "oshift<28>") + (joined + (portRef Q (instanceRef oshift_28)) + (portRef I1 (instanceRef oshift_27_rstpot_SW0)) + (portRef I0 (instanceRef oshift_28_rstpot_SW0)) + (portRef I1 (instanceRef oshift_28_rstpot_SW1)) + (portRef I0 (instanceRef oshift_28_rstpot_renamed_34)) + ) + ) + (net (rename oshift_27_ "oshift<27>") + (joined + (portRef Q (instanceRef oshift_27)) + (portRef I1 (instanceRef oshift_26_rstpot_SW0)) + (portRef I0 (instanceRef oshift_27_rstpot_SW0)) + (portRef I1 (instanceRef oshift_27_rstpot_SW1)) + (portRef I0 (instanceRef oshift_27_rstpot_renamed_33)) + ) + ) + (net (rename oshift_26_ "oshift<26>") + (joined + (portRef Q (instanceRef oshift_26)) + (portRef I1 (instanceRef oshift_25_rstpot_SW0)) + (portRef I0 (instanceRef oshift_26_rstpot_SW0)) + (portRef I1 (instanceRef oshift_26_rstpot_SW1)) + (portRef I0 (instanceRef oshift_26_rstpot_renamed_32)) + ) + ) + (net (rename oshift_25_ "oshift<25>") + (joined + (portRef Q (instanceRef oshift_25)) + (portRef I1 (instanceRef oshift_24_rstpot_SW0)) + (portRef I0 (instanceRef oshift_25_rstpot_SW0)) + (portRef I1 (instanceRef oshift_25_rstpot_SW1)) + (portRef I0 (instanceRef oshift_25_rstpot_renamed_31)) + ) + ) + (net (rename oshift_24_ "oshift<24>") + (joined + (portRef Q (instanceRef oshift_24)) + (portRef I1 (instanceRef oshift_23_rstpot_SW0)) + (portRef I0 (instanceRef oshift_24_rstpot_SW0)) + (portRef I1 (instanceRef oshift_24_rstpot_SW1)) + (portRef I0 (instanceRef oshift_24_rstpot_renamed_30)) + ) + ) + (net (rename oshift_23_ "oshift<23>") + (joined + (portRef Q (instanceRef oshift_23)) + (portRef I1 (instanceRef oshift_22_rstpot_SW0)) + (portRef I0 (instanceRef oshift_23_rstpot_SW0)) + (portRef I1 (instanceRef oshift_23_rstpot_SW1)) + (portRef I0 (instanceRef oshift_23_rstpot_renamed_29)) + ) + ) + (net (rename oshift_22_ "oshift<22>") + (joined + (portRef Q (instanceRef oshift_22)) + (portRef I1 (instanceRef oshift_21_rstpot_SW0)) + (portRef I0 (instanceRef oshift_22_rstpot_SW0)) + (portRef I1 (instanceRef oshift_22_rstpot_SW1)) + (portRef I0 (instanceRef oshift_22_rstpot_renamed_28)) + ) + ) + (net (rename oshift_21_ "oshift<21>") + (joined + (portRef Q (instanceRef oshift_21)) + (portRef I1 (instanceRef oshift_20_rstpot_SW0)) + (portRef I0 (instanceRef oshift_21_rstpot_SW0)) + (portRef I1 (instanceRef oshift_21_rstpot_SW1)) + (portRef I0 (instanceRef oshift_21_rstpot_renamed_27)) + ) + ) + (net (rename oshift_20_ "oshift<20>") + (joined + (portRef Q (instanceRef oshift_20)) + (portRef I1 (instanceRef oshift_19_rstpot_SW0)) + (portRef I0 (instanceRef oshift_20_rstpot_SW0)) + (portRef I1 (instanceRef oshift_20_rstpot_SW1)) + (portRef I0 (instanceRef oshift_20_rstpot_renamed_26)) + ) + ) + (net (rename oshift_19_ "oshift<19>") + (joined + (portRef Q (instanceRef oshift_19)) + (portRef I1 (instanceRef oshift_18_rstpot_SW0)) + (portRef I0 (instanceRef oshift_19_rstpot_SW0)) + (portRef I1 (instanceRef oshift_19_rstpot_SW1)) + (portRef I0 (instanceRef oshift_19_rstpot_renamed_25)) + ) + ) + (net (rename oshift_18_ "oshift<18>") + (joined + (portRef Q (instanceRef oshift_18)) + (portRef I1 (instanceRef oshift_17_rstpot_SW0)) + (portRef I0 (instanceRef oshift_18_rstpot_SW0)) + (portRef I1 (instanceRef oshift_18_rstpot_SW1)) + (portRef I0 (instanceRef oshift_18_rstpot_renamed_24)) + ) + ) + (net (rename oshift_17_ "oshift<17>") + (joined + (portRef Q (instanceRef oshift_17)) + (portRef I1 (instanceRef oshift_16_rstpot_SW0)) + (portRef I0 (instanceRef oshift_17_rstpot_SW0)) + (portRef I1 (instanceRef oshift_17_rstpot_SW1)) + (portRef I0 (instanceRef oshift_17_rstpot_renamed_23)) + ) + ) + (net (rename oshift_16_ "oshift<16>") + (joined + (portRef Q (instanceRef oshift_16)) + (portRef I1 (instanceRef oshift_15_rstpot_SW0)) + (portRef I0 (instanceRef oshift_16_rstpot_SW0)) + (portRef I1 (instanceRef oshift_16_rstpot_SW1)) + (portRef I0 (instanceRef oshift_16_rstpot_renamed_22)) + ) + ) + (net (rename oshift_15_ "oshift<15>") + (joined + (portRef Q (instanceRef oshift_15)) + (portRef I1 (instanceRef oshift_14_rstpot_SW0)) + (portRef I0 (instanceRef oshift_15_rstpot_SW0)) + (portRef I1 (instanceRef oshift_15_rstpot_SW1)) + (portRef I0 (instanceRef oshift_15_rstpot_renamed_21)) + ) + ) + (net (rename oshift_14_ "oshift<14>") + (joined + (portRef Q (instanceRef oshift_14)) + (portRef I1 (instanceRef oshift_13_rstpot_SW0)) + (portRef I0 (instanceRef oshift_14_rstpot_SW0)) + (portRef I1 (instanceRef oshift_14_rstpot_SW1)) + (portRef I0 (instanceRef oshift_14_rstpot_renamed_20)) + ) + ) + (net (rename oshift_13_ "oshift<13>") + (joined + (portRef Q (instanceRef oshift_13)) + (portRef I1 (instanceRef oshift_12_rstpot_SW0)) + (portRef I0 (instanceRef oshift_13_rstpot_SW0)) + (portRef I1 (instanceRef oshift_13_rstpot_SW1)) + (portRef I0 (instanceRef oshift_13_rstpot_renamed_19)) + ) + ) + (net (rename oshift_12_ "oshift<12>") + (joined + (portRef Q (instanceRef oshift_12)) + (portRef I1 (instanceRef oshift_11_rstpot_SW0)) + (portRef I0 (instanceRef oshift_12_rstpot_SW0)) + (portRef I1 (instanceRef oshift_12_rstpot_SW1)) + (portRef I0 (instanceRef oshift_12_rstpot_renamed_18)) + ) + ) + (net (rename oshift_11_ "oshift<11>") + (joined + (portRef Q (instanceRef oshift_11)) + (portRef I1 (instanceRef oshift_10_rstpot_SW0)) + (portRef I0 (instanceRef oshift_11_rstpot_SW0)) + (portRef I1 (instanceRef oshift_11_rstpot_SW1)) + (portRef I0 (instanceRef oshift_11_rstpot_renamed_17)) + ) + ) + (net (rename oshift_10_ "oshift<10>") + (joined + (portRef Q (instanceRef oshift_10)) + (portRef I1 (instanceRef oshift_9_rstpot_SW0)) + (portRef I0 (instanceRef oshift_10_rstpot_SW0)) + (portRef I1 (instanceRef oshift_10_rstpot_SW1)) + (portRef I0 (instanceRef oshift_10_rstpot_renamed_16)) + ) + ) + (net (rename oshift_9_ "oshift<9>") + (joined + (portRef Q (instanceRef oshift_9)) + (portRef I1 (instanceRef oshift_8_rstpot_SW0)) + (portRef I0 (instanceRef oshift_9_rstpot_SW0)) + (portRef I1 (instanceRef oshift_9_rstpot_SW1)) + (portRef I0 (instanceRef oshift_9_rstpot_renamed_15)) + ) + ) + (net (rename oshift_8_ "oshift<8>") + (joined + (portRef Q (instanceRef oshift_8)) + (portRef I1 (instanceRef oshift_7_rstpot_SW0)) + (portRef I0 (instanceRef oshift_8_rstpot_SW0)) + (portRef I1 (instanceRef oshift_8_rstpot_SW1)) + (portRef I0 (instanceRef oshift_8_rstpot_renamed_14)) + ) + ) + (net (rename oshift_7_ "oshift<7>") + (joined + (portRef Q (instanceRef oshift_7)) + (portRef I1 (instanceRef oshift_6_rstpot_SW0)) + (portRef I0 (instanceRef oshift_7_rstpot_SW0)) + (portRef I1 (instanceRef oshift_7_rstpot_SW1)) + (portRef I0 (instanceRef oshift_7_rstpot_renamed_13)) + ) + ) + (net (rename oshift_6_ "oshift<6>") + (joined + (portRef Q (instanceRef oshift_6)) + (portRef I1 (instanceRef oshift_5_rstpot_SW0)) + (portRef I0 (instanceRef oshift_6_rstpot_SW0)) + (portRef I1 (instanceRef oshift_6_rstpot_SW1)) + (portRef I0 (instanceRef oshift_6_rstpot_renamed_12)) + ) + ) + (net (rename oshift_5_ "oshift<5>") + (joined + (portRef Q (instanceRef oshift_5)) + (portRef I1 (instanceRef oshift_4_rstpot_SW0)) + (portRef I0 (instanceRef oshift_5_rstpot_SW0)) + (portRef I1 (instanceRef oshift_5_rstpot_SW1)) + (portRef I0 (instanceRef oshift_5_rstpot_renamed_11)) + ) + ) + (net (rename oshift_4_ "oshift<4>") + (joined + (portRef Q (instanceRef oshift_4)) + (portRef I1 (instanceRef oshift_3_rstpot_SW0)) + (portRef I0 (instanceRef oshift_4_rstpot_SW0)) + (portRef I1 (instanceRef oshift_4_rstpot_SW1)) + (portRef I0 (instanceRef oshift_4_rstpot_renamed_10)) + ) + ) + (net (rename oshift_3_ "oshift<3>") + (joined + (portRef Q (instanceRef oshift_3)) + (portRef I1 (instanceRef oshift_2_rstpot_SW0)) + (portRef I0 (instanceRef oshift_3_rstpot_SW0)) + (portRef I1 (instanceRef oshift_3_rstpot_SW1)) + (portRef I0 (instanceRef oshift_3_rstpot_renamed_9)) + ) + ) + (net (rename oshift_2_ "oshift<2>") + (joined + (portRef Q (instanceRef oshift_2)) + (portRef I4 (instanceRef oshift_2_rstpot_SW1)) + (portRef I3 (instanceRef &_n0198_inv1_SW1)) + (portRef I0 (instanceRef oshift_2_rstpot_SW0)) + (portRef I0 (instanceRef oshift_2_rstpot_renamed_8)) + ) + ) + (net (rename oshift_1_ "oshift<1>") + (joined + (portRef Q (instanceRef oshift_1)) + (portRef I3 (instanceRef &_n0198_inv1_SW0)) + (portRef I0 (instanceRef &_n0198_inv1_SW1)) + (portRef I0 (instanceRef oshift_1_rstpot_renamed_40)) + ) + ) + (net dop1950_r_0 + (joined + (portRef TDO (instanceRef bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef Q (instanceRef dop1950_r_0_renamed_5)) + (portRef I0 (instanceRef &_n0202_inv_SW2)) + (portRef I0 (instanceRef dop1950_r_0_rstpot_renamed_7)) + ) + ) + (net (rename icmd_rd_1_ "icmd_rd<1>") + (joined + (portRef Q (instanceRef icmd_rd_1)) + (portRef I1 (instanceRef ird_valid_icmd_rd_1__AND_11_o1)) + (portRef I1 (instanceRef oshift_2_rstpot_SW1)) + (portRef I1 (instanceRef icmd_rd_1_dpot_renamed_43)) + (portRef I4 (instanceRef oshift_33_rstpot_SW0)) + (portRef I4 (instanceRef oshift_3_rstpot_SW1)) + (portRef I4 (instanceRef oshift_4_rstpot_SW1)) + (portRef I4 (instanceRef oshift_5_rstpot_SW1)) + (portRef I4 (instanceRef oshift_6_rstpot_SW1)) + (portRef I4 (instanceRef oshift_7_rstpot_SW1)) + (portRef I4 (instanceRef oshift_8_rstpot_SW1)) + (portRef I4 (instanceRef oshift_9_rstpot_SW1)) + (portRef I4 (instanceRef oshift_10_rstpot_SW1)) + (portRef I4 (instanceRef oshift_11_rstpot_SW1)) + (portRef I4 (instanceRef oshift_12_rstpot_SW1)) + (portRef I4 (instanceRef oshift_13_rstpot_SW1)) + (portRef I4 (instanceRef oshift_14_rstpot_SW1)) + (portRef I4 (instanceRef oshift_15_rstpot_SW1)) + (portRef I4 (instanceRef oshift_16_rstpot_SW1)) + (portRef I4 (instanceRef oshift_17_rstpot_SW1)) + (portRef I4 (instanceRef oshift_18_rstpot_SW1)) + (portRef I4 (instanceRef oshift_19_rstpot_SW1)) + (portRef I4 (instanceRef oshift_20_rstpot_SW1)) + (portRef I4 (instanceRef oshift_21_rstpot_SW1)) + (portRef I4 (instanceRef oshift_22_rstpot_SW1)) + (portRef I4 (instanceRef oshift_23_rstpot_SW1)) + (portRef I4 (instanceRef oshift_24_rstpot_SW1)) + (portRef I4 (instanceRef oshift_25_rstpot_SW1)) + (portRef I4 (instanceRef oshift_26_rstpot_SW1)) + (portRef I4 (instanceRef oshift_27_rstpot_SW1)) + (portRef I4 (instanceRef oshift_28_rstpot_SW1)) + (portRef I4 (instanceRef oshift_29_rstpot_SW1)) + (portRef I4 (instanceRef oshift_30_rstpot_SW1)) + (portRef I4 (instanceRef oshift_31_rstpot_SW1)) + (portRef I4 (instanceRef oshift_32_rstpot_SW1)) + (portRef I1 (instanceRef oshift_0_rstpot_renamed_39)) + (portRef I1 (instanceRef oshift_1_rstpot_renamed_40)) + ) + ) + (net (rename icmd_rd_0_ "icmd_rd<0>") + (joined + (portRef Q (instanceRef icmd_rd_0)) + (portRef I2 (instanceRef ird_valid_icmd_rd_1__AND_11_o1)) + (portRef I3 (instanceRef oshift_33_rstpot_SW0)) + (portRef I3 (instanceRef oshift_2_rstpot_SW1)) + (portRef I3 (instanceRef oshift_3_rstpot_SW1)) + (portRef I3 (instanceRef oshift_4_rstpot_SW1)) + (portRef I3 (instanceRef oshift_5_rstpot_SW1)) + (portRef I3 (instanceRef oshift_6_rstpot_SW1)) + (portRef I3 (instanceRef oshift_7_rstpot_SW1)) + (portRef I3 (instanceRef oshift_8_rstpot_SW1)) + (portRef I3 (instanceRef oshift_9_rstpot_SW1)) + (portRef I3 (instanceRef oshift_10_rstpot_SW1)) + (portRef I3 (instanceRef oshift_11_rstpot_SW1)) + (portRef I3 (instanceRef oshift_12_rstpot_SW1)) + (portRef I3 (instanceRef oshift_13_rstpot_SW1)) + (portRef I3 (instanceRef oshift_14_rstpot_SW1)) + (portRef I3 (instanceRef oshift_15_rstpot_SW1)) + (portRef I3 (instanceRef oshift_16_rstpot_SW1)) + (portRef I3 (instanceRef oshift_17_rstpot_SW1)) + (portRef I3 (instanceRef oshift_18_rstpot_SW1)) + (portRef I3 (instanceRef oshift_19_rstpot_SW1)) + (portRef I3 (instanceRef oshift_20_rstpot_SW1)) + (portRef I3 (instanceRef oshift_21_rstpot_SW1)) + (portRef I3 (instanceRef oshift_22_rstpot_SW1)) + (portRef I3 (instanceRef oshift_23_rstpot_SW1)) + (portRef I3 (instanceRef oshift_24_rstpot_SW1)) + (portRef I3 (instanceRef oshift_25_rstpot_SW1)) + (portRef I3 (instanceRef oshift_26_rstpot_SW1)) + (portRef I3 (instanceRef oshift_27_rstpot_SW1)) + (portRef I3 (instanceRef oshift_28_rstpot_SW1)) + (portRef I3 (instanceRef oshift_29_rstpot_SW1)) + (portRef I3 (instanceRef oshift_30_rstpot_SW1)) + (portRef I3 (instanceRef oshift_31_rstpot_SW1)) + (portRef I3 (instanceRef oshift_32_rstpot_SW1)) + (portRef I1 (instanceRef icmd_rd_0_dpot_renamed_42)) + (portRef I2 (instanceRef oshift_0_rstpot_renamed_39)) + (portRef I2 (instanceRef oshift_1_rstpot_renamed_40)) + ) + ) + (net (rename ird_valid_ishift_data_71__AND_10_o "ird_valid_ishift_data[71]_AND_10_o") + (joined + (portRef D (instanceRef localbus_rvalid_renamed_1)) + (portRef O (instanceRef ird_valid_ishift_data_71__AND_10_o1)) + ) + ) + (net (rename ird_valid_icmd_rd_1__AND_11_o "ird_valid_icmd_rd[1]_AND_11_o") + (joined + (portRef CE (instanceRef localbus_raddr_0)) + (portRef CE (instanceRef localbus_raddr_1)) + (portRef CE (instanceRef localbus_raddr_2)) + (portRef CE (instanceRef localbus_raddr_3)) + (portRef CE (instanceRef localbus_raddr_4)) + (portRef CE (instanceRef localbus_raddr_5)) + (portRef CE (instanceRef localbus_raddr_6)) + (portRef CE (instanceRef localbus_raddr_7)) + (portRef CE (instanceRef localbus_raddr_8)) + (portRef CE (instanceRef localbus_raddr_9)) + (portRef CE (instanceRef localbus_raddr_10)) + (portRef CE (instanceRef localbus_raddr_11)) + (portRef CE (instanceRef localbus_raddr_12)) + (portRef CE (instanceRef localbus_raddr_13)) + (portRef CE (instanceRef localbus_raddr_14)) + (portRef CE (instanceRef localbus_raddr_15)) + (portRef CE (instanceRef localbus_raddr_16)) + (portRef CE (instanceRef localbus_raddr_17)) + (portRef CE (instanceRef localbus_raddr_18)) + (portRef CE (instanceRef localbus_raddr_19)) + (portRef CE (instanceRef localbus_raddr_20)) + (portRef CE (instanceRef localbus_raddr_21)) + (portRef CE (instanceRef localbus_raddr_22)) + (portRef CE (instanceRef localbus_raddr_23)) + (portRef CE (instanceRef localbus_raddr_24)) + (portRef CE (instanceRef localbus_raddr_25)) + (portRef CE (instanceRef localbus_raddr_26)) + (portRef CE (instanceRef localbus_raddr_27)) + (portRef CE (instanceRef localbus_raddr_28)) + (portRef CE (instanceRef localbus_raddr_29)) + (portRef CE (instanceRef localbus_raddr_30)) + (portRef CE (instanceRef localbus_raddr_31)) + (portRef O (instanceRef ird_valid_icmd_rd_1__AND_11_o1)) + ) + ) + (net chip + (joined + (portRef D (instanceRef chip_r_0)) + (portRef O (instanceRef bscan_xjtag_uut_Mmux_CS11)) + ) + ) + (net dop_clk + (joined + (portRef D (instanceRef dop_clk_r_0)) + (portRef O (instanceRef bscan_xjtag_uut_CLK1)) + ) + ) + (net dop1949 + (joined + (portRef D (instanceRef dop1949_r_0)) + (portRef O (instanceRef bscan_xjtag_uut_DOP19491)) + ) + ) + (net (rename dop_clk_r_2__dop_clk_r_1__AND_3_o "dop_clk_r[2]_dop_clk_r[1]_AND_3_o") + (joined + (portRef CE (instanceRef wdata_0)) + (portRef CE (instanceRef wdata_1)) + (portRef CE (instanceRef wdata_2)) + (portRef CE (instanceRef wdata_3)) + (portRef CE (instanceRef wdata_4)) + (portRef CE (instanceRef wdata_5)) + (portRef CE (instanceRef wdata_6)) + (portRef CE (instanceRef wdata_7)) + (portRef CE (instanceRef wdata_8)) + (portRef CE (instanceRef wdata_9)) + (portRef CE (instanceRef wdata_10)) + (portRef CE (instanceRef wdata_11)) + (portRef CE (instanceRef wdata_12)) + (portRef CE (instanceRef wdata_13)) + (portRef CE (instanceRef wdata_14)) + (portRef CE (instanceRef wdata_15)) + (portRef CE (instanceRef wdata_16)) + (portRef CE (instanceRef wdata_17)) + (portRef CE (instanceRef wdata_18)) + (portRef CE (instanceRef wdata_19)) + (portRef CE (instanceRef wdata_20)) + (portRef CE (instanceRef wdata_21)) + (portRef CE (instanceRef wdata_22)) + (portRef CE (instanceRef wdata_23)) + (portRef CE (instanceRef wdata_24)) + (portRef CE (instanceRef wdata_25)) + (portRef CE (instanceRef wdata_26)) + (portRef CE (instanceRef wdata_27)) + (portRef CE (instanceRef wdata_28)) + (portRef CE (instanceRef wdata_29)) + (portRef CE (instanceRef wdata_30)) + (portRef CE (instanceRef wdata_31)) + (portRef CE (instanceRef cmd_0)) + (portRef CE (instanceRef cmd_1)) + (portRef CE (instanceRef cmd_2)) + (portRef CE (instanceRef cmd_3)) + (portRef CE (instanceRef cmd_4)) + (portRef CE (instanceRef cmd_5)) + (portRef CE (instanceRef cmd_6)) + (portRef CE (instanceRef cmd_7)) + (portRef CE (instanceRef addr_0)) + (portRef CE (instanceRef addr_1)) + (portRef CE (instanceRef addr_2)) + (portRef CE (instanceRef addr_3)) + (portRef CE (instanceRef addr_4)) + (portRef CE (instanceRef addr_5)) + (portRef CE (instanceRef addr_6)) + (portRef CE (instanceRef addr_7)) + (portRef CE (instanceRef addr_8)) + (portRef CE (instanceRef addr_9)) + (portRef CE (instanceRef addr_10)) + (portRef CE (instanceRef addr_11)) + (portRef CE (instanceRef addr_12)) + (portRef CE (instanceRef addr_13)) + (portRef CE (instanceRef addr_14)) + (portRef CE (instanceRef addr_15)) + (portRef CE (instanceRef addr_16)) + (portRef CE (instanceRef addr_17)) + (portRef CE (instanceRef addr_18)) + (portRef CE (instanceRef addr_19)) + (portRef CE (instanceRef addr_20)) + (portRef CE (instanceRef addr_21)) + (portRef CE (instanceRef addr_22)) + (portRef CE (instanceRef addr_23)) + (portRef CE (instanceRef addr_24)) + (portRef CE (instanceRef addr_25)) + (portRef CE (instanceRef addr_26)) + (portRef CE (instanceRef addr_27)) + (portRef CE (instanceRef addr_28)) + (portRef CE (instanceRef addr_29)) + (portRef CE (instanceRef addr_30)) + (portRef CE (instanceRef addr_31)) + (portRef O (instanceRef dop_clk_r_2__dop_clk_r_1__AND_3_o1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_31_ "addr[31]_icrab_data[31]_xor_28_OUT<31>") + (joined + (portRef D (instanceRef localbus_waddr_31)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_31_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_30_ "addr[31]_icrab_data[31]_xor_28_OUT<30>") + (joined + (portRef D (instanceRef localbus_waddr_30)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_30_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_29_ "addr[31]_icrab_data[31]_xor_28_OUT<29>") + (joined + (portRef D (instanceRef localbus_waddr_29)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_29_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_28_ "addr[31]_icrab_data[31]_xor_28_OUT<28>") + (joined + (portRef D (instanceRef localbus_waddr_28)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_28_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_27_ "addr[31]_icrab_data[31]_xor_28_OUT<27>") + (joined + (portRef D (instanceRef localbus_waddr_27)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_27_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_26_ "addr[31]_icrab_data[31]_xor_28_OUT<26>") + (joined + (portRef D (instanceRef localbus_waddr_26)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_26_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_25_ "addr[31]_icrab_data[31]_xor_28_OUT<25>") + (joined + (portRef D (instanceRef localbus_waddr_25)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_25_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_24_ "addr[31]_icrab_data[31]_xor_28_OUT<24>") + (joined + (portRef D (instanceRef localbus_waddr_24)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_24_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_23_ "addr[31]_icrab_data[31]_xor_28_OUT<23>") + (joined + (portRef D (instanceRef localbus_waddr_23)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_23_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_22_ "addr[31]_icrab_data[31]_xor_28_OUT<22>") + (joined + (portRef D (instanceRef localbus_waddr_22)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_22_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_21_ "addr[31]_icrab_data[31]_xor_28_OUT<21>") + (joined + (portRef D (instanceRef localbus_waddr_21)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_21_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_20_ "addr[31]_icrab_data[31]_xor_28_OUT<20>") + (joined + (portRef D (instanceRef localbus_waddr_20)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_20_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_19_ "addr[31]_icrab_data[31]_xor_28_OUT<19>") + (joined + (portRef D (instanceRef localbus_waddr_19)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_19_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_18_ "addr[31]_icrab_data[31]_xor_28_OUT<18>") + (joined + (portRef D (instanceRef localbus_waddr_18)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_18_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_17_ "addr[31]_icrab_data[31]_xor_28_OUT<17>") + (joined + (portRef D (instanceRef localbus_waddr_17)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_17_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_16_ "addr[31]_icrab_data[31]_xor_28_OUT<16>") + (joined + (portRef D (instanceRef localbus_waddr_16)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_16_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_15_ "addr[31]_icrab_data[31]_xor_28_OUT<15>") + (joined + (portRef D (instanceRef localbus_waddr_15)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_15_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_14_ "addr[31]_icrab_data[31]_xor_28_OUT<14>") + (joined + (portRef D (instanceRef localbus_waddr_14)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_14_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_13_ "addr[31]_icrab_data[31]_xor_28_OUT<13>") + (joined + (portRef D (instanceRef localbus_waddr_13)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_13_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_12_ "addr[31]_icrab_data[31]_xor_28_OUT<12>") + (joined + (portRef D (instanceRef localbus_waddr_12)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_12_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_11_ "addr[31]_icrab_data[31]_xor_28_OUT<11>") + (joined + (portRef D (instanceRef localbus_waddr_11)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_11_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_10_ "addr[31]_icrab_data[31]_xor_28_OUT<10>") + (joined + (portRef D (instanceRef localbus_waddr_10)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_10_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_9_ "addr[31]_icrab_data[31]_xor_28_OUT<9>") + (joined + (portRef D (instanceRef localbus_waddr_9)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_9_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_8_ "addr[31]_icrab_data[31]_xor_28_OUT<8>") + (joined + (portRef D (instanceRef localbus_waddr_8)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_8_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_7_ "addr[31]_icrab_data[31]_xor_28_OUT<7>") + (joined + (portRef D (instanceRef localbus_waddr_7)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_7_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_6_ "addr[31]_icrab_data[31]_xor_28_OUT<6>") + (joined + (portRef D (instanceRef localbus_waddr_6)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_6_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_5_ "addr[31]_icrab_data[31]_xor_28_OUT<5>") + (joined + (portRef D (instanceRef localbus_waddr_5)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_5_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_4_ "addr[31]_icrab_data[31]_xor_28_OUT<4>") + (joined + (portRef D (instanceRef localbus_waddr_4)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_4_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_3_ "addr[31]_icrab_data[31]_xor_28_OUT<3>") + (joined + (portRef D (instanceRef localbus_waddr_3)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_3_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_2_ "addr[31]_icrab_data[31]_xor_28_OUT<2>") + (joined + (portRef D (instanceRef localbus_waddr_2)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_2_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_1_ "addr[31]_icrab_data[31]_xor_28_OUT<1>") + (joined + (portRef D (instanceRef localbus_waddr_1)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_1_xo_0_1)) + ) + ) + (net (rename addr_31__icrab_data_31__xor_28_OUT_0_ "addr[31]_icrab_data[31]_xor_28_OUT<0>") + (joined + (portRef D (instanceRef localbus_waddr_0)) + (portRef O (instanceRef Mxor_addr_31__icrab_data_31__xor_28_OUT_0_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_31_ "wdata[31]_icrab_data[31]_xor_31_OUT<31>") + (joined + (portRef D (instanceRef localbus_wdata_31)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_31_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_30_ "wdata[31]_icrab_data[31]_xor_31_OUT<30>") + (joined + (portRef D (instanceRef localbus_wdata_30)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_30_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_29_ "wdata[31]_icrab_data[31]_xor_31_OUT<29>") + (joined + (portRef D (instanceRef localbus_wdata_29)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_29_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_28_ "wdata[31]_icrab_data[31]_xor_31_OUT<28>") + (joined + (portRef D (instanceRef localbus_wdata_28)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_28_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_27_ "wdata[31]_icrab_data[31]_xor_31_OUT<27>") + (joined + (portRef D (instanceRef localbus_wdata_27)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_27_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_26_ "wdata[31]_icrab_data[31]_xor_31_OUT<26>") + (joined + (portRef D (instanceRef localbus_wdata_26)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_26_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_25_ "wdata[31]_icrab_data[31]_xor_31_OUT<25>") + (joined + (portRef D (instanceRef localbus_wdata_25)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_25_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_24_ "wdata[31]_icrab_data[31]_xor_31_OUT<24>") + (joined + (portRef D (instanceRef localbus_wdata_24)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_24_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_23_ "wdata[31]_icrab_data[31]_xor_31_OUT<23>") + (joined + (portRef D (instanceRef localbus_wdata_23)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_23_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_22_ "wdata[31]_icrab_data[31]_xor_31_OUT<22>") + (joined + (portRef D (instanceRef localbus_wdata_22)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_22_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_21_ "wdata[31]_icrab_data[31]_xor_31_OUT<21>") + (joined + (portRef D (instanceRef localbus_wdata_21)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_21_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_20_ "wdata[31]_icrab_data[31]_xor_31_OUT<20>") + (joined + (portRef D (instanceRef localbus_wdata_20)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_20_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_19_ "wdata[31]_icrab_data[31]_xor_31_OUT<19>") + (joined + (portRef D (instanceRef localbus_wdata_19)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_19_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_18_ "wdata[31]_icrab_data[31]_xor_31_OUT<18>") + (joined + (portRef D (instanceRef localbus_wdata_18)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_18_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_17_ "wdata[31]_icrab_data[31]_xor_31_OUT<17>") + (joined + (portRef D (instanceRef localbus_wdata_17)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_17_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_16_ "wdata[31]_icrab_data[31]_xor_31_OUT<16>") + (joined + (portRef D (instanceRef localbus_wdata_16)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_16_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_15_ "wdata[31]_icrab_data[31]_xor_31_OUT<15>") + (joined + (portRef D (instanceRef localbus_wdata_15)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_15_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_14_ "wdata[31]_icrab_data[31]_xor_31_OUT<14>") + (joined + (portRef D (instanceRef localbus_wdata_14)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_14_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_13_ "wdata[31]_icrab_data[31]_xor_31_OUT<13>") + (joined + (portRef D (instanceRef localbus_wdata_13)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_13_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_12_ "wdata[31]_icrab_data[31]_xor_31_OUT<12>") + (joined + (portRef D (instanceRef localbus_wdata_12)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_12_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_11_ "wdata[31]_icrab_data[31]_xor_31_OUT<11>") + (joined + (portRef D (instanceRef localbus_wdata_11)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_11_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_10_ "wdata[31]_icrab_data[31]_xor_31_OUT<10>") + (joined + (portRef D (instanceRef localbus_wdata_10)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_10_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_9_ "wdata[31]_icrab_data[31]_xor_31_OUT<9>") + (joined + (portRef D (instanceRef localbus_wdata_9)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_9_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_8_ "wdata[31]_icrab_data[31]_xor_31_OUT<8>") + (joined + (portRef D (instanceRef localbus_wdata_8)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_8_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_7_ "wdata[31]_icrab_data[31]_xor_31_OUT<7>") + (joined + (portRef D (instanceRef localbus_wdata_7)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_7_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_6_ "wdata[31]_icrab_data[31]_xor_31_OUT<6>") + (joined + (portRef D (instanceRef localbus_wdata_6)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_6_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_5_ "wdata[31]_icrab_data[31]_xor_31_OUT<5>") + (joined + (portRef D (instanceRef localbus_wdata_5)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_5_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_4_ "wdata[31]_icrab_data[31]_xor_31_OUT<4>") + (joined + (portRef D (instanceRef localbus_wdata_4)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_4_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_3_ "wdata[31]_icrab_data[31]_xor_31_OUT<3>") + (joined + (portRef D (instanceRef localbus_wdata_3)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_3_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_2_ "wdata[31]_icrab_data[31]_xor_31_OUT<2>") + (joined + (portRef D (instanceRef localbus_wdata_2)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_2_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_1_ "wdata[31]_icrab_data[31]_xor_31_OUT<1>") + (joined + (portRef D (instanceRef localbus_wdata_1)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_1_xo_0_1)) + ) + ) + (net (rename wdata_31__icrab_data_31__xor_31_OUT_0_ "wdata[31]_icrab_data[31]_xor_31_OUT<0>") + (joined + (portRef D (instanceRef localbus_wdata_0)) + (portRef O (instanceRef Mxor_wdata_31__icrab_data_31__xor_31_OUT_0_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_31_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<31>") + (joined + (portRef D (instanceRef localbus_raddr_31)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_31_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_30_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<30>") + (joined + (portRef D (instanceRef localbus_raddr_30)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_30_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_29_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<29>") + (joined + (portRef D (instanceRef localbus_raddr_29)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_29_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_28_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<28>") + (joined + (portRef D (instanceRef localbus_raddr_28)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_28_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_27_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<27>") + (joined + (portRef D (instanceRef localbus_raddr_27)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_27_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_26_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<26>") + (joined + (portRef D (instanceRef localbus_raddr_26)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_26_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_25_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<25>") + (joined + (portRef D (instanceRef localbus_raddr_25)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_25_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_24_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<24>") + (joined + (portRef D (instanceRef localbus_raddr_24)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_24_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_23_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<23>") + (joined + (portRef D (instanceRef localbus_raddr_23)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_23_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_22_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<22>") + (joined + (portRef D (instanceRef localbus_raddr_22)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_22_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_21_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<21>") + (joined + (portRef D (instanceRef localbus_raddr_21)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_21_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_20_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<20>") + (joined + (portRef D (instanceRef localbus_raddr_20)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_20_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_19_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<19>") + (joined + (portRef D (instanceRef localbus_raddr_19)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_19_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_18_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<18>") + (joined + (portRef D (instanceRef localbus_raddr_18)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_18_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_17_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<17>") + (joined + (portRef D (instanceRef localbus_raddr_17)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_17_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_16_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<16>") + (joined + (portRef D (instanceRef localbus_raddr_16)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_16_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_15_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<15>") + (joined + (portRef D (instanceRef localbus_raddr_15)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_15_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_14_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<14>") + (joined + (portRef D (instanceRef localbus_raddr_14)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_14_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_13_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<13>") + (joined + (portRef D (instanceRef localbus_raddr_13)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_13_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_12_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<12>") + (joined + (portRef D (instanceRef localbus_raddr_12)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_12_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_11_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<11>") + (joined + (portRef D (instanceRef localbus_raddr_11)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_11_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_10_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<10>") + (joined + (portRef D (instanceRef localbus_raddr_10)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_10_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_9_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<9>") + (joined + (portRef D (instanceRef localbus_raddr_9)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_9_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_8_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<8>") + (joined + (portRef D (instanceRef localbus_raddr_8)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_8_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_7_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<7>") + (joined + (portRef D (instanceRef localbus_raddr_7)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_7_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_6_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<6>") + (joined + (portRef D (instanceRef localbus_raddr_6)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_6_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_5_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<5>") + (joined + (portRef D (instanceRef localbus_raddr_5)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_5_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_4_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<4>") + (joined + (portRef D (instanceRef localbus_raddr_4)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_4_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_3_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<3>") + (joined + (portRef D (instanceRef localbus_raddr_3)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_3_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_2_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<2>") + (joined + (portRef D (instanceRef localbus_raddr_2)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_2_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_1_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<1>") + (joined + (portRef D (instanceRef localbus_raddr_1)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_1_xo_0_1)) + ) + ) + (net (rename ishift_data_69__icrab_data_31__xor_54_OUT_0_ "ishift_data[69]_icrab_data[31]_xor_54_OUT<0>") + (joined + (portRef D (instanceRef localbus_raddr_0)) + (portRef O (instanceRef Mxor_ishift_data_69__icrab_data_31__xor_54_OUT_0_xo_0_1)) + ) + ) + (net (rename dop_clk_r_2__ishift_cnt_7__AND_13_o "dop_clk_r[2]_ishift_cnt[7]_AND_13_o") + (joined + (portRef O (instanceRef dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + (portRef I4 (instanceRef oshift_33_rstpot_renamed_6)) + (portRef I5 (instanceRef dop1950_r_0_rstpot_renamed_7)) + (portRef I4 (instanceRef oshift_2_rstpot_renamed_8)) + (portRef I4 (instanceRef oshift_3_rstpot_renamed_9)) + (portRef I4 (instanceRef oshift_4_rstpot_renamed_10)) + (portRef I4 (instanceRef oshift_5_rstpot_renamed_11)) + (portRef I4 (instanceRef oshift_6_rstpot_renamed_12)) + (portRef I4 (instanceRef oshift_7_rstpot_renamed_13)) + (portRef I4 (instanceRef oshift_8_rstpot_renamed_14)) + (portRef I4 (instanceRef oshift_9_rstpot_renamed_15)) + (portRef I4 (instanceRef oshift_10_rstpot_renamed_16)) + (portRef I4 (instanceRef oshift_11_rstpot_renamed_17)) + (portRef I4 (instanceRef oshift_12_rstpot_renamed_18)) + (portRef I4 (instanceRef oshift_13_rstpot_renamed_19)) + (portRef I4 (instanceRef oshift_14_rstpot_renamed_20)) + (portRef I4 (instanceRef oshift_15_rstpot_renamed_21)) + (portRef I4 (instanceRef oshift_16_rstpot_renamed_22)) + (portRef I4 (instanceRef oshift_17_rstpot_renamed_23)) + (portRef I4 (instanceRef oshift_18_rstpot_renamed_24)) + (portRef I4 (instanceRef oshift_19_rstpot_renamed_25)) + (portRef I4 (instanceRef oshift_20_rstpot_renamed_26)) + (portRef I4 (instanceRef oshift_21_rstpot_renamed_27)) + (portRef I4 (instanceRef oshift_22_rstpot_renamed_28)) + (portRef I4 (instanceRef oshift_23_rstpot_renamed_29)) + (portRef I4 (instanceRef oshift_24_rstpot_renamed_30)) + (portRef I4 (instanceRef oshift_25_rstpot_renamed_31)) + (portRef I4 (instanceRef oshift_26_rstpot_renamed_32)) + (portRef I4 (instanceRef oshift_27_rstpot_renamed_33)) + (portRef I4 (instanceRef oshift_28_rstpot_renamed_34)) + (portRef I4 (instanceRef oshift_29_rstpot_renamed_35)) + (portRef I4 (instanceRef oshift_30_rstpot_renamed_36)) + (portRef I4 (instanceRef oshift_31_rstpot_renamed_37)) + (portRef I4 (instanceRef oshift_32_rstpot_renamed_38)) + (portRef I4 (instanceRef oshift_0_rstpot_renamed_39)) + (portRef I4 (instanceRef oshift_1_rstpot_renamed_40)) + ) + ) + (net (rename GND_1_o_ishift_data_71__MUX_49_o "GND_1_o_ishift_data[71]_MUX_49_o") + (joined + (portRef D (instanceRef ird_valid_renamed_3)) + (portRef O (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o1)) + ) + ) + (net (rename GND_1_o_cmd_1__MUX_42_o "GND_1_o_cmd[1]_MUX_42_o") + (joined + (portRef D (instanceRef iwr_valid_renamed_2)) + (portRef O (instanceRef Mmux_GND_1_o_cmd_1__MUX_42_o11)) + ) + ) + (net N1 + (joined + (portRef G (instanceRef XST_GND)) + (portRef I2 (instanceRef Mcount_ishift_cnt_lut_0__)) + (portRef DI (instanceRef Mcount_ishift_cnt_cy_0__)) + (portRef I2 (instanceRef Mcount_ishift_cnt_lut_1__)) + (portRef DI (instanceRef Mcount_ishift_cnt_cy_1__)) + (portRef I2 (instanceRef Mcount_ishift_cnt_lut_2__)) + (portRef DI (instanceRef Mcount_ishift_cnt_cy_2__)) + (portRef I2 (instanceRef Mcount_ishift_cnt_lut_3__)) + (portRef DI (instanceRef Mcount_ishift_cnt_cy_3__)) + (portRef I2 (instanceRef Mcount_ishift_cnt_lut_4__)) + (portRef DI (instanceRef Mcount_ishift_cnt_cy_4__)) + (portRef I2 (instanceRef Mcount_ishift_cnt_lut_5__)) + (portRef DI (instanceRef Mcount_ishift_cnt_cy_5__)) + (portRef I2 (instanceRef Mcount_ishift_cnt_lut_6__)) + (portRef DI (instanceRef Mcount_ishift_cnt_cy_6__)) + (portRef I2 (instanceRef Mcount_ishift_cnt_lut_7__)) + ) + ) + (net (rename &_n0181_inv "_n0181_inv") + (joined + (portRef CE (instanceRef icrab_data_0)) + (portRef CE (instanceRef icrab_data_1)) + (portRef CE (instanceRef icrab_data_2)) + (portRef CE (instanceRef icrab_data_3)) + (portRef CE (instanceRef icrab_data_4)) + (portRef CE (instanceRef icrab_data_5)) + (portRef CE (instanceRef icrab_data_6)) + (portRef CE (instanceRef icrab_data_7)) + (portRef CE (instanceRef icrab_data_8)) + (portRef CE (instanceRef icrab_data_9)) + (portRef CE (instanceRef icrab_data_10)) + (portRef CE (instanceRef icrab_data_11)) + (portRef CE (instanceRef icrab_data_12)) + (portRef CE (instanceRef icrab_data_13)) + (portRef CE (instanceRef icrab_data_14)) + (portRef CE (instanceRef icrab_data_15)) + (portRef CE (instanceRef icrab_data_16)) + (portRef CE (instanceRef icrab_data_17)) + (portRef CE (instanceRef icrab_data_18)) + (portRef CE (instanceRef icrab_data_19)) + (portRef CE (instanceRef icrab_data_20)) + (portRef CE (instanceRef icrab_data_21)) + (portRef CE (instanceRef icrab_data_22)) + (portRef CE (instanceRef icrab_data_23)) + (portRef CE (instanceRef icrab_data_24)) + (portRef CE (instanceRef icrab_data_25)) + (portRef CE (instanceRef icrab_data_26)) + (portRef CE (instanceRef icrab_data_27)) + (portRef CE (instanceRef icrab_data_28)) + (portRef CE (instanceRef icrab_data_29)) + (portRef CE (instanceRef icrab_data_30)) + (portRef CE (instanceRef icrab_data_31)) + (portRef O (instanceRef &_n0181_inv1)) + ) + ) + (net (rename &_n0177_inv "_n0177_inv") + (joined + (portRef CE (instanceRef localbus_wdata_0)) + (portRef CE (instanceRef localbus_wdata_1)) + (portRef CE (instanceRef localbus_wdata_2)) + (portRef CE (instanceRef localbus_wdata_3)) + (portRef CE (instanceRef localbus_wdata_4)) + (portRef CE (instanceRef localbus_wdata_5)) + (portRef CE (instanceRef localbus_wdata_6)) + (portRef CE (instanceRef localbus_wdata_7)) + (portRef CE (instanceRef localbus_wdata_8)) + (portRef CE (instanceRef localbus_wdata_9)) + (portRef CE (instanceRef localbus_wdata_10)) + (portRef CE (instanceRef localbus_wdata_11)) + (portRef CE (instanceRef localbus_wdata_12)) + (portRef CE (instanceRef localbus_wdata_13)) + (portRef CE (instanceRef localbus_wdata_14)) + (portRef CE (instanceRef localbus_wdata_15)) + (portRef CE (instanceRef localbus_wdata_16)) + (portRef CE (instanceRef localbus_wdata_17)) + (portRef CE (instanceRef localbus_wdata_18)) + (portRef CE (instanceRef localbus_wdata_19)) + (portRef CE (instanceRef localbus_wdata_20)) + (portRef CE (instanceRef localbus_wdata_21)) + (portRef CE (instanceRef localbus_wdata_22)) + (portRef CE (instanceRef localbus_wdata_23)) + (portRef CE (instanceRef localbus_wdata_24)) + (portRef CE (instanceRef localbus_wdata_25)) + (portRef CE (instanceRef localbus_wdata_26)) + (portRef CE (instanceRef localbus_wdata_27)) + (portRef CE (instanceRef localbus_wdata_28)) + (portRef CE (instanceRef localbus_wdata_29)) + (portRef CE (instanceRef localbus_wdata_30)) + (portRef CE (instanceRef localbus_wdata_31)) + (portRef O (instanceRef &_n0177_inv1)) + ) + ) + (net (rename &_n0173_inv "_n0173_inv") + (joined + (portRef CE (instanceRef localbus_waddr_0)) + (portRef CE (instanceRef localbus_waddr_1)) + (portRef CE (instanceRef localbus_waddr_2)) + (portRef CE (instanceRef localbus_waddr_3)) + (portRef CE (instanceRef localbus_waddr_4)) + (portRef CE (instanceRef localbus_waddr_5)) + (portRef CE (instanceRef localbus_waddr_6)) + (portRef CE (instanceRef localbus_waddr_7)) + (portRef CE (instanceRef localbus_waddr_8)) + (portRef CE (instanceRef localbus_waddr_9)) + (portRef CE (instanceRef localbus_waddr_10)) + (portRef CE (instanceRef localbus_waddr_11)) + (portRef CE (instanceRef localbus_waddr_12)) + (portRef CE (instanceRef localbus_waddr_13)) + (portRef CE (instanceRef localbus_waddr_14)) + (portRef CE (instanceRef localbus_waddr_15)) + (portRef CE (instanceRef localbus_waddr_16)) + (portRef CE (instanceRef localbus_waddr_17)) + (portRef CE (instanceRef localbus_waddr_18)) + (portRef CE (instanceRef localbus_waddr_19)) + (portRef CE (instanceRef localbus_waddr_20)) + (portRef CE (instanceRef localbus_waddr_21)) + (portRef CE (instanceRef localbus_waddr_22)) + (portRef CE (instanceRef localbus_waddr_23)) + (portRef CE (instanceRef localbus_waddr_24)) + (portRef CE (instanceRef localbus_waddr_25)) + (portRef CE (instanceRef localbus_waddr_26)) + (portRef CE (instanceRef localbus_waddr_27)) + (portRef CE (instanceRef localbus_waddr_28)) + (portRef CE (instanceRef localbus_waddr_29)) + (portRef CE (instanceRef localbus_waddr_30)) + (portRef CE (instanceRef localbus_waddr_31)) + (portRef D (instanceRef localbus_wvalid_renamed_0)) + (portRef O (instanceRef &_n0173_inv1)) + ) + ) + (net (rename bscan_xjtag_uut_TDI "bscan_xjtag_uut/TDI") + (joined + (portRef TDI (instanceRef bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef I0 (instanceRef bscan_xjtag_uut_DOP19491)) + ) + ) + (net (rename bscan_xjtag_uut_TCK "bscan_xjtag_uut/TCK") + (joined + (portRef TCK (instanceRef bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef I1 (instanceRef bscan_xjtag_uut_CLK1)) + ) + ) + (net (rename bscan_xjtag_uut_SHIFT "bscan_xjtag_uut/SHIFT") + (joined + (portRef SHIFT (instanceRef bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef I0 (instanceRef bscan_xjtag_uut_CLK1)) + (portRef I1 (instanceRef bscan_xjtag_uut_DOP19491)) + ) + ) + (net (rename bscan_xjtag_uut_SEL "bscan_xjtag_uut/SEL") + (joined + (portRef SEL (instanceRef bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef I1 (instanceRef bscan_xjtag_uut_Mmux_CS11)) + ) + ) + (net (rename bscan_xjtag_uut_RUNTEST "bscan_xjtag_uut/RUNTEST") + (joined + (portRef RUNTEST (instanceRef bscan_xjtag_uut_BSCAN_SPARTAN6_inst)) + (portRef I0 (instanceRef bscan_xjtag_uut_Mmux_CS11)) + ) + ) + (net (rename &_n0186_inv "_n0186_inv") + (joined + (portRef CE (instanceRef ishift_cnt_0)) + (portRef CE (instanceRef ishift_cnt_1)) + (portRef CE (instanceRef ishift_cnt_2)) + (portRef CE (instanceRef ishift_cnt_3)) + (portRef CE (instanceRef ishift_cnt_4)) + (portRef CE (instanceRef ishift_cnt_5)) + (portRef CE (instanceRef ishift_cnt_6)) + (portRef CE (instanceRef ishift_cnt_7)) + (portRef O (instanceRef &_n0186_inv1)) + ) + ) + (net (rename chip_r_1__inv "chip_r<1>_inv") + (joined + (portRef CI (instanceRef Mcount_ishift_cnt_cy_0__)) + (portRef CI (instanceRef Mcount_ishift_cnt_xor_0__)) + (portRef O (instanceRef chip_r_1__inv1_INV_0)) + ) + ) + (net Mcount_ishift_cnt + (joined + (portRef O (instanceRef Mcount_ishift_cnt_xor_0__)) + (portRef D (instanceRef ishift_cnt_0)) + ) + ) + (net (rename Mcount_ishift_cnt_lut_0_ "Mcount_ishift_cnt_lut<0>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_lut_0__)) + (portRef S (instanceRef Mcount_ishift_cnt_cy_0__)) + (portRef LI (instanceRef Mcount_ishift_cnt_xor_0__)) + ) + ) + (net (rename Mcount_ishift_cnt_cy_0_ "Mcount_ishift_cnt_cy<0>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_cy_0__)) + (portRef CI (instanceRef Mcount_ishift_cnt_cy_1__)) + (portRef CI (instanceRef Mcount_ishift_cnt_xor_1__)) + ) + ) + (net Mcount_ishift_cnt1 + (joined + (portRef O (instanceRef Mcount_ishift_cnt_xor_1__)) + (portRef D (instanceRef ishift_cnt_1)) + ) + ) + (net (rename Mcount_ishift_cnt_lut_1_ "Mcount_ishift_cnt_lut<1>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_lut_1__)) + (portRef S (instanceRef Mcount_ishift_cnt_cy_1__)) + (portRef LI (instanceRef Mcount_ishift_cnt_xor_1__)) + ) + ) + (net (rename Mcount_ishift_cnt_cy_1_ "Mcount_ishift_cnt_cy<1>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_cy_1__)) + (portRef CI (instanceRef Mcount_ishift_cnt_cy_2__)) + (portRef CI (instanceRef Mcount_ishift_cnt_xor_2__)) + ) + ) + (net Mcount_ishift_cnt2 + (joined + (portRef O (instanceRef Mcount_ishift_cnt_xor_2__)) + (portRef D (instanceRef ishift_cnt_2)) + ) + ) + (net (rename Mcount_ishift_cnt_lut_2_ "Mcount_ishift_cnt_lut<2>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_lut_2__)) + (portRef S (instanceRef Mcount_ishift_cnt_cy_2__)) + (portRef LI (instanceRef Mcount_ishift_cnt_xor_2__)) + ) + ) + (net (rename Mcount_ishift_cnt_cy_2_ "Mcount_ishift_cnt_cy<2>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_cy_2__)) + (portRef CI (instanceRef Mcount_ishift_cnt_cy_3__)) + (portRef CI (instanceRef Mcount_ishift_cnt_xor_3__)) + ) + ) + (net Mcount_ishift_cnt3 + (joined + (portRef O (instanceRef Mcount_ishift_cnt_xor_3__)) + (portRef D (instanceRef ishift_cnt_3)) + ) + ) + (net (rename Mcount_ishift_cnt_lut_3_ "Mcount_ishift_cnt_lut<3>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_lut_3__)) + (portRef S (instanceRef Mcount_ishift_cnt_cy_3__)) + (portRef LI (instanceRef Mcount_ishift_cnt_xor_3__)) + ) + ) + (net (rename Mcount_ishift_cnt_cy_3_ "Mcount_ishift_cnt_cy<3>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_cy_3__)) + (portRef CI (instanceRef Mcount_ishift_cnt_cy_4__)) + (portRef CI (instanceRef Mcount_ishift_cnt_xor_4__)) + ) + ) + (net Mcount_ishift_cnt4 + (joined + (portRef O (instanceRef Mcount_ishift_cnt_xor_4__)) + (portRef D (instanceRef ishift_cnt_4)) + ) + ) + (net (rename Mcount_ishift_cnt_lut_4_ "Mcount_ishift_cnt_lut<4>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_lut_4__)) + (portRef S (instanceRef Mcount_ishift_cnt_cy_4__)) + (portRef LI (instanceRef Mcount_ishift_cnt_xor_4__)) + ) + ) + (net (rename Mcount_ishift_cnt_cy_4_ "Mcount_ishift_cnt_cy<4>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_cy_4__)) + (portRef CI (instanceRef Mcount_ishift_cnt_cy_5__)) + (portRef CI (instanceRef Mcount_ishift_cnt_xor_5__)) + ) + ) + (net Mcount_ishift_cnt5 + (joined + (portRef O (instanceRef Mcount_ishift_cnt_xor_5__)) + (portRef D (instanceRef ishift_cnt_5)) + ) + ) + (net (rename Mcount_ishift_cnt_lut_5_ "Mcount_ishift_cnt_lut<5>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_lut_5__)) + (portRef S (instanceRef Mcount_ishift_cnt_cy_5__)) + (portRef LI (instanceRef Mcount_ishift_cnt_xor_5__)) + ) + ) + (net (rename Mcount_ishift_cnt_cy_5_ "Mcount_ishift_cnt_cy<5>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_cy_5__)) + (portRef CI (instanceRef Mcount_ishift_cnt_cy_6__)) + (portRef CI (instanceRef Mcount_ishift_cnt_xor_6__)) + ) + ) + (net Mcount_ishift_cnt6 + (joined + (portRef O (instanceRef Mcount_ishift_cnt_xor_6__)) + (portRef D (instanceRef ishift_cnt_6)) + ) + ) + (net (rename Mcount_ishift_cnt_lut_6_ "Mcount_ishift_cnt_lut<6>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_lut_6__)) + (portRef S (instanceRef Mcount_ishift_cnt_cy_6__)) + (portRef LI (instanceRef Mcount_ishift_cnt_xor_6__)) + ) + ) + (net (rename Mcount_ishift_cnt_cy_6_ "Mcount_ishift_cnt_cy<6>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_cy_6__)) + (portRef CI (instanceRef Mcount_ishift_cnt_xor_7__)) + ) + ) + (net Mcount_ishift_cnt7 + (joined + (portRef O (instanceRef Mcount_ishift_cnt_xor_7__)) + (portRef D (instanceRef ishift_cnt_7)) + ) + ) + (net (rename Mcount_ishift_cnt_lut_7_ "Mcount_ishift_cnt_lut<7>") + (joined + (portRef O (instanceRef Mcount_ishift_cnt_lut_7__)) + (portRef LI (instanceRef Mcount_ishift_cnt_xor_7__)) + ) + ) + (net (rename Mmux_GND_1_o_ishift_data_71__MUX_49_o11 "Mmux_GND_1_o_ishift_data[71]_MUX_49_o11") + (joined + (portRef O (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_renamed_4)) + (portRef CE (instanceRef icmd_rd_0)) + (portRef CE (instanceRef icmd_rd_1)) + ) + ) + (net N0 + (joined + (portRef O (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW0)) + (portRef I5 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_renamed_4)) + (portRef I0 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o1)) + (portRef I4 (instanceRef dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + ) + ) + (net N2 + (joined + (portRef O (instanceRef &_n0202_inv_SW0)) + (portRef I4 (instanceRef dop1950_r_0_rstpot_renamed_7)) + (portRef I2 (instanceRef &_n0202_inv_SW1)) + ) + ) + (net dop1950_r_0_rstpot + (joined + (portRef D (instanceRef dop1950_r_0_renamed_5)) + (portRef O (instanceRef dop1950_r_0_rstpot_renamed_7)) + ) + ) + (net N6 + (joined + (portRef O (instanceRef &_n0202_inv_SW1)) + (portRef I5 (instanceRef oshift_33_rstpot_renamed_6)) + (portRef I5 (instanceRef oshift_2_rstpot_renamed_8)) + (portRef I5 (instanceRef oshift_3_rstpot_renamed_9)) + (portRef I5 (instanceRef oshift_4_rstpot_renamed_10)) + (portRef I5 (instanceRef oshift_5_rstpot_renamed_11)) + (portRef I5 (instanceRef oshift_6_rstpot_renamed_12)) + (portRef I5 (instanceRef oshift_7_rstpot_renamed_13)) + (portRef I5 (instanceRef oshift_8_rstpot_renamed_14)) + (portRef I5 (instanceRef oshift_9_rstpot_renamed_15)) + (portRef I5 (instanceRef oshift_10_rstpot_renamed_16)) + (portRef I5 (instanceRef oshift_11_rstpot_renamed_17)) + (portRef I5 (instanceRef oshift_12_rstpot_renamed_18)) + (portRef I5 (instanceRef oshift_13_rstpot_renamed_19)) + (portRef I5 (instanceRef oshift_14_rstpot_renamed_20)) + (portRef I5 (instanceRef oshift_15_rstpot_renamed_21)) + (portRef I5 (instanceRef oshift_16_rstpot_renamed_22)) + (portRef I5 (instanceRef oshift_17_rstpot_renamed_23)) + (portRef I5 (instanceRef oshift_18_rstpot_renamed_24)) + (portRef I5 (instanceRef oshift_19_rstpot_renamed_25)) + (portRef I5 (instanceRef oshift_20_rstpot_renamed_26)) + (portRef I5 (instanceRef oshift_21_rstpot_renamed_27)) + (portRef I5 (instanceRef oshift_22_rstpot_renamed_28)) + (portRef I5 (instanceRef oshift_23_rstpot_renamed_29)) + (portRef I5 (instanceRef oshift_24_rstpot_renamed_30)) + (portRef I5 (instanceRef oshift_25_rstpot_renamed_31)) + (portRef I5 (instanceRef oshift_26_rstpot_renamed_32)) + (portRef I5 (instanceRef oshift_27_rstpot_renamed_33)) + (portRef I5 (instanceRef oshift_28_rstpot_renamed_34)) + (portRef I5 (instanceRef oshift_29_rstpot_renamed_35)) + (portRef I5 (instanceRef oshift_30_rstpot_renamed_36)) + (portRef I5 (instanceRef oshift_31_rstpot_renamed_37)) + (portRef I5 (instanceRef oshift_32_rstpot_renamed_38)) + (portRef I5 (instanceRef oshift_0_rstpot_renamed_39)) + (portRef I5 (instanceRef oshift_1_rstpot_renamed_40)) + ) + ) + (net N8 + (joined + (portRef O (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW1)) + (portRef I5 (instanceRef dop_clk_r_2__ishift_cnt_7__AND_13_o1)) + ) + ) + (net oshift_0_rstpot + (joined + (portRef D (instanceRef oshift_0)) + (portRef O (instanceRef oshift_0_rstpot_renamed_39)) + ) + ) + (net oshift_1_rstpot + (joined + (portRef D (instanceRef oshift_1)) + (portRef O (instanceRef oshift_1_rstpot_renamed_40)) + ) + ) + (net oshift_2_rstpot + (joined + (portRef D (instanceRef oshift_2)) + (portRef O (instanceRef oshift_2_rstpot_renamed_8)) + ) + ) + (net oshift_3_rstpot + (joined + (portRef D (instanceRef oshift_3)) + (portRef O (instanceRef oshift_3_rstpot_renamed_9)) + ) + ) + (net oshift_4_rstpot + (joined + (portRef D (instanceRef oshift_4)) + (portRef O (instanceRef oshift_4_rstpot_renamed_10)) + ) + ) + (net oshift_5_rstpot + (joined + (portRef D (instanceRef oshift_5)) + (portRef O (instanceRef oshift_5_rstpot_renamed_11)) + ) + ) + (net oshift_6_rstpot + (joined + (portRef D (instanceRef oshift_6)) + (portRef O (instanceRef oshift_6_rstpot_renamed_12)) + ) + ) + (net oshift_7_rstpot + (joined + (portRef D (instanceRef oshift_7)) + (portRef O (instanceRef oshift_7_rstpot_renamed_13)) + ) + ) + (net oshift_8_rstpot + (joined + (portRef D (instanceRef oshift_8)) + (portRef O (instanceRef oshift_8_rstpot_renamed_14)) + ) + ) + (net oshift_9_rstpot + (joined + (portRef D (instanceRef oshift_9)) + (portRef O (instanceRef oshift_9_rstpot_renamed_15)) + ) + ) + (net oshift_10_rstpot + (joined + (portRef D (instanceRef oshift_10)) + (portRef O (instanceRef oshift_10_rstpot_renamed_16)) + ) + ) + (net oshift_11_rstpot + (joined + (portRef D (instanceRef oshift_11)) + (portRef O (instanceRef oshift_11_rstpot_renamed_17)) + ) + ) + (net oshift_12_rstpot + (joined + (portRef D (instanceRef oshift_12)) + (portRef O (instanceRef oshift_12_rstpot_renamed_18)) + ) + ) + (net oshift_13_rstpot + (joined + (portRef D (instanceRef oshift_13)) + (portRef O (instanceRef oshift_13_rstpot_renamed_19)) + ) + ) + (net oshift_14_rstpot + (joined + (portRef D (instanceRef oshift_14)) + (portRef O (instanceRef oshift_14_rstpot_renamed_20)) + ) + ) + (net oshift_15_rstpot + (joined + (portRef D (instanceRef oshift_15)) + (portRef O (instanceRef oshift_15_rstpot_renamed_21)) + ) + ) + (net oshift_16_rstpot + (joined + (portRef D (instanceRef oshift_16)) + (portRef O (instanceRef oshift_16_rstpot_renamed_22)) + ) + ) + (net oshift_17_rstpot + (joined + (portRef D (instanceRef oshift_17)) + (portRef O (instanceRef oshift_17_rstpot_renamed_23)) + ) + ) + (net oshift_18_rstpot + (joined + (portRef D (instanceRef oshift_18)) + (portRef O (instanceRef oshift_18_rstpot_renamed_24)) + ) + ) + (net oshift_19_rstpot + (joined + (portRef D (instanceRef oshift_19)) + (portRef O (instanceRef oshift_19_rstpot_renamed_25)) + ) + ) + (net oshift_20_rstpot + (joined + (portRef D (instanceRef oshift_20)) + (portRef O (instanceRef oshift_20_rstpot_renamed_26)) + ) + ) + (net oshift_21_rstpot + (joined + (portRef D (instanceRef oshift_21)) + (portRef O (instanceRef oshift_21_rstpot_renamed_27)) + ) + ) + (net oshift_22_rstpot + (joined + (portRef D (instanceRef oshift_22)) + (portRef O (instanceRef oshift_22_rstpot_renamed_28)) + ) + ) + (net oshift_23_rstpot + (joined + (portRef D (instanceRef oshift_23)) + (portRef O (instanceRef oshift_23_rstpot_renamed_29)) + ) + ) + (net oshift_24_rstpot + (joined + (portRef D (instanceRef oshift_24)) + (portRef O (instanceRef oshift_24_rstpot_renamed_30)) + ) + ) + (net oshift_25_rstpot + (joined + (portRef D (instanceRef oshift_25)) + (portRef O (instanceRef oshift_25_rstpot_renamed_31)) + ) + ) + (net oshift_26_rstpot + (joined + (portRef D (instanceRef oshift_26)) + (portRef O (instanceRef oshift_26_rstpot_renamed_32)) + ) + ) + (net oshift_27_rstpot + (joined + (portRef D (instanceRef oshift_27)) + (portRef O (instanceRef oshift_27_rstpot_renamed_33)) + ) + ) + (net oshift_28_rstpot + (joined + (portRef D (instanceRef oshift_28)) + (portRef O (instanceRef oshift_28_rstpot_renamed_34)) + ) + ) + (net oshift_29_rstpot + (joined + (portRef D (instanceRef oshift_29)) + (portRef O (instanceRef oshift_29_rstpot_renamed_35)) + ) + ) + (net oshift_30_rstpot + (joined + (portRef D (instanceRef oshift_30)) + (portRef O (instanceRef oshift_30_rstpot_renamed_36)) + ) + ) + (net oshift_31_rstpot + (joined + (portRef D (instanceRef oshift_31)) + (portRef O (instanceRef oshift_31_rstpot_renamed_37)) + ) + ) + (net oshift_32_rstpot + (joined + (portRef D (instanceRef oshift_32)) + (portRef O (instanceRef oshift_32_rstpot_renamed_38)) + ) + ) + (net oshift_33_rstpot + (joined + (portRef D (instanceRef oshift_33)) + (portRef O (instanceRef oshift_33_rstpot_renamed_6)) + ) + ) + (net N10 + (joined + (portRef O (instanceRef oshift_33_rstpot_SW0)) + (portRef I3 (instanceRef oshift_33_rstpot_renamed_6)) + ) + ) + (net N12 + (joined + (portRef O (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o1_SW0_SW0)) + (portRef I2 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o1)) + ) + ) + (net N14 + (joined + (portRef O (instanceRef &_n0202_inv_SW2)) + (portRef I3 (instanceRef dop1950_r_0_rstpot_renamed_7)) + ) + ) + (net N16 + (joined + (portRef O (instanceRef oshift_2_rstpot_SW0)) + (portRef I2 (instanceRef oshift_2_rstpot_renamed_8)) + ) + ) + (net N17 + (joined + (portRef O (instanceRef oshift_2_rstpot_SW1)) + (portRef I3 (instanceRef oshift_2_rstpot_renamed_8)) + ) + ) + (net N19 + (joined + (portRef O (instanceRef oshift_3_rstpot_SW0)) + (portRef I2 (instanceRef oshift_3_rstpot_renamed_9)) + ) + ) + (net N20 + (joined + (portRef O (instanceRef oshift_3_rstpot_SW1)) + (portRef I3 (instanceRef oshift_3_rstpot_renamed_9)) + ) + ) + (net N22 + (joined + (portRef O (instanceRef oshift_4_rstpot_SW0)) + (portRef I2 (instanceRef oshift_4_rstpot_renamed_10)) + ) + ) + (net N23 + (joined + (portRef O (instanceRef oshift_4_rstpot_SW1)) + (portRef I3 (instanceRef oshift_4_rstpot_renamed_10)) + ) + ) + (net N25 + (joined + (portRef O (instanceRef oshift_5_rstpot_SW0)) + (portRef I2 (instanceRef oshift_5_rstpot_renamed_11)) + ) + ) + (net N26 + (joined + (portRef O (instanceRef oshift_5_rstpot_SW1)) + (portRef I3 (instanceRef oshift_5_rstpot_renamed_11)) + ) + ) + (net N28 + (joined + (portRef O (instanceRef oshift_6_rstpot_SW0)) + (portRef I2 (instanceRef oshift_6_rstpot_renamed_12)) + ) + ) + (net N29 + (joined + (portRef O (instanceRef oshift_6_rstpot_SW1)) + (portRef I3 (instanceRef oshift_6_rstpot_renamed_12)) + ) + ) + (net N31 + (joined + (portRef O (instanceRef oshift_7_rstpot_SW0)) + (portRef I2 (instanceRef oshift_7_rstpot_renamed_13)) + ) + ) + (net N32 + (joined + (portRef O (instanceRef oshift_7_rstpot_SW1)) + (portRef I3 (instanceRef oshift_7_rstpot_renamed_13)) + ) + ) + (net N34 + (joined + (portRef O (instanceRef oshift_8_rstpot_SW0)) + (portRef I2 (instanceRef oshift_8_rstpot_renamed_14)) + ) + ) + (net N35 + (joined + (portRef O (instanceRef oshift_8_rstpot_SW1)) + (portRef I3 (instanceRef oshift_8_rstpot_renamed_14)) + ) + ) + (net N37 + (joined + (portRef O (instanceRef oshift_9_rstpot_SW0)) + (portRef I2 (instanceRef oshift_9_rstpot_renamed_15)) + ) + ) + (net N38 + (joined + (portRef O (instanceRef oshift_9_rstpot_SW1)) + (portRef I3 (instanceRef oshift_9_rstpot_renamed_15)) + ) + ) + (net N40 + (joined + (portRef O (instanceRef oshift_10_rstpot_SW0)) + (portRef I2 (instanceRef oshift_10_rstpot_renamed_16)) + ) + ) + (net N41 + (joined + (portRef O (instanceRef oshift_10_rstpot_SW1)) + (portRef I3 (instanceRef oshift_10_rstpot_renamed_16)) + ) + ) + (net N43 + (joined + (portRef O (instanceRef oshift_11_rstpot_SW0)) + (portRef I2 (instanceRef oshift_11_rstpot_renamed_17)) + ) + ) + (net N44 + (joined + (portRef O (instanceRef oshift_11_rstpot_SW1)) + (portRef I3 (instanceRef oshift_11_rstpot_renamed_17)) + ) + ) + (net N46 + (joined + (portRef O (instanceRef oshift_12_rstpot_SW0)) + (portRef I2 (instanceRef oshift_12_rstpot_renamed_18)) + ) + ) + (net N47 + (joined + (portRef O (instanceRef oshift_12_rstpot_SW1)) + (portRef I3 (instanceRef oshift_12_rstpot_renamed_18)) + ) + ) + (net N49 + (joined + (portRef O (instanceRef oshift_13_rstpot_SW0)) + (portRef I2 (instanceRef oshift_13_rstpot_renamed_19)) + ) + ) + (net N50 + (joined + (portRef O (instanceRef oshift_13_rstpot_SW1)) + (portRef I3 (instanceRef oshift_13_rstpot_renamed_19)) + ) + ) + (net N52 + (joined + (portRef O (instanceRef oshift_14_rstpot_SW0)) + (portRef I2 (instanceRef oshift_14_rstpot_renamed_20)) + ) + ) + (net N53 + (joined + (portRef O (instanceRef oshift_14_rstpot_SW1)) + (portRef I3 (instanceRef oshift_14_rstpot_renamed_20)) + ) + ) + (net N55 + (joined + (portRef O (instanceRef oshift_15_rstpot_SW0)) + (portRef I2 (instanceRef oshift_15_rstpot_renamed_21)) + ) + ) + (net N56 + (joined + (portRef O (instanceRef oshift_15_rstpot_SW1)) + (portRef I3 (instanceRef oshift_15_rstpot_renamed_21)) + ) + ) + (net N58 + (joined + (portRef O (instanceRef oshift_16_rstpot_SW0)) + (portRef I2 (instanceRef oshift_16_rstpot_renamed_22)) + ) + ) + (net N59 + (joined + (portRef O (instanceRef oshift_16_rstpot_SW1)) + (portRef I3 (instanceRef oshift_16_rstpot_renamed_22)) + ) + ) + (net N61 + (joined + (portRef O (instanceRef oshift_17_rstpot_SW0)) + (portRef I2 (instanceRef oshift_17_rstpot_renamed_23)) + ) + ) + (net N62 + (joined + (portRef O (instanceRef oshift_17_rstpot_SW1)) + (portRef I3 (instanceRef oshift_17_rstpot_renamed_23)) + ) + ) + (net N64 + (joined + (portRef O (instanceRef oshift_18_rstpot_SW0)) + (portRef I2 (instanceRef oshift_18_rstpot_renamed_24)) + ) + ) + (net N65 + (joined + (portRef O (instanceRef oshift_18_rstpot_SW1)) + (portRef I3 (instanceRef oshift_18_rstpot_renamed_24)) + ) + ) + (net N67 + (joined + (portRef O (instanceRef oshift_19_rstpot_SW0)) + (portRef I2 (instanceRef oshift_19_rstpot_renamed_25)) + ) + ) + (net N68 + (joined + (portRef O (instanceRef oshift_19_rstpot_SW1)) + (portRef I3 (instanceRef oshift_19_rstpot_renamed_25)) + ) + ) + (net N70 + (joined + (portRef O (instanceRef oshift_20_rstpot_SW0)) + (portRef I2 (instanceRef oshift_20_rstpot_renamed_26)) + ) + ) + (net N71 + (joined + (portRef O (instanceRef oshift_20_rstpot_SW1)) + (portRef I3 (instanceRef oshift_20_rstpot_renamed_26)) + ) + ) + (net N73 + (joined + (portRef O (instanceRef oshift_21_rstpot_SW0)) + (portRef I2 (instanceRef oshift_21_rstpot_renamed_27)) + ) + ) + (net N74 + (joined + (portRef O (instanceRef oshift_21_rstpot_SW1)) + (portRef I3 (instanceRef oshift_21_rstpot_renamed_27)) + ) + ) + (net N76 + (joined + (portRef O (instanceRef oshift_22_rstpot_SW0)) + (portRef I2 (instanceRef oshift_22_rstpot_renamed_28)) + ) + ) + (net N77 + (joined + (portRef O (instanceRef oshift_22_rstpot_SW1)) + (portRef I3 (instanceRef oshift_22_rstpot_renamed_28)) + ) + ) + (net N79 + (joined + (portRef O (instanceRef oshift_23_rstpot_SW0)) + (portRef I2 (instanceRef oshift_23_rstpot_renamed_29)) + ) + ) + (net N80 + (joined + (portRef O (instanceRef oshift_23_rstpot_SW1)) + (portRef I3 (instanceRef oshift_23_rstpot_renamed_29)) + ) + ) + (net N82 + (joined + (portRef O (instanceRef oshift_24_rstpot_SW0)) + (portRef I2 (instanceRef oshift_24_rstpot_renamed_30)) + ) + ) + (net N83 + (joined + (portRef O (instanceRef oshift_24_rstpot_SW1)) + (portRef I3 (instanceRef oshift_24_rstpot_renamed_30)) + ) + ) + (net N85 + (joined + (portRef O (instanceRef oshift_25_rstpot_SW0)) + (portRef I2 (instanceRef oshift_25_rstpot_renamed_31)) + ) + ) + (net N86 + (joined + (portRef O (instanceRef oshift_25_rstpot_SW1)) + (portRef I3 (instanceRef oshift_25_rstpot_renamed_31)) + ) + ) + (net N88 + (joined + (portRef O (instanceRef oshift_26_rstpot_SW0)) + (portRef I2 (instanceRef oshift_26_rstpot_renamed_32)) + ) + ) + (net N89 + (joined + (portRef O (instanceRef oshift_26_rstpot_SW1)) + (portRef I3 (instanceRef oshift_26_rstpot_renamed_32)) + ) + ) + (net N91 + (joined + (portRef O (instanceRef oshift_27_rstpot_SW0)) + (portRef I2 (instanceRef oshift_27_rstpot_renamed_33)) + ) + ) + (net N92 + (joined + (portRef O (instanceRef oshift_27_rstpot_SW1)) + (portRef I3 (instanceRef oshift_27_rstpot_renamed_33)) + ) + ) + (net N94 + (joined + (portRef O (instanceRef oshift_28_rstpot_SW0)) + (portRef I2 (instanceRef oshift_28_rstpot_renamed_34)) + ) + ) + (net N95 + (joined + (portRef O (instanceRef oshift_28_rstpot_SW1)) + (portRef I3 (instanceRef oshift_28_rstpot_renamed_34)) + ) + ) + (net N97 + (joined + (portRef O (instanceRef oshift_29_rstpot_SW0)) + (portRef I2 (instanceRef oshift_29_rstpot_renamed_35)) + ) + ) + (net N98 + (joined + (portRef O (instanceRef oshift_29_rstpot_SW1)) + (portRef I3 (instanceRef oshift_29_rstpot_renamed_35)) + ) + ) + (net N100 + (joined + (portRef O (instanceRef oshift_30_rstpot_SW0)) + (portRef I2 (instanceRef oshift_30_rstpot_renamed_36)) + ) + ) + (net N101 + (joined + (portRef O (instanceRef oshift_30_rstpot_SW1)) + (portRef I3 (instanceRef oshift_30_rstpot_renamed_36)) + ) + ) + (net N103 + (joined + (portRef O (instanceRef oshift_31_rstpot_SW0)) + (portRef I2 (instanceRef oshift_31_rstpot_renamed_37)) + ) + ) + (net N104 + (joined + (portRef O (instanceRef oshift_31_rstpot_SW1)) + (portRef I3 (instanceRef oshift_31_rstpot_renamed_37)) + ) + ) + (net N106 + (joined + (portRef O (instanceRef oshift_32_rstpot_SW0)) + (portRef I2 (instanceRef oshift_32_rstpot_renamed_38)) + ) + ) + (net N107 + (joined + (portRef O (instanceRef oshift_32_rstpot_SW1)) + (portRef I3 (instanceRef oshift_32_rstpot_renamed_38)) + ) + ) + (net N109 + (joined + (portRef O (instanceRef &_n0198_inv1_SW0)) + (portRef I3 (instanceRef oshift_0_rstpot_renamed_39)) + ) + ) + (net N111 + (joined + (portRef O (instanceRef &_n0198_inv1_SW1)) + (portRef I3 (instanceRef oshift_1_rstpot_renamed_40)) + ) + ) + (net (rename &_n0206_inv1_rstpot "_n0206_inv1_rstpot") + (joined + (portRef O (instanceRef &_n0206_inv1_rstpot_renamed_41)) + (portRef I0 (instanceRef icmd_rd_0_dpot_renamed_42)) + (portRef I0 (instanceRef icmd_rd_1_dpot_renamed_43)) + ) + ) + (net icmd_rd_0_dpot + (joined + (portRef O (instanceRef icmd_rd_0_dpot_renamed_42)) + (portRef D (instanceRef icmd_rd_0)) + ) + ) + (net icmd_rd_1_dpot + (joined + (portRef O (instanceRef icmd_rd_1_dpot_renamed_43)) + (portRef D (instanceRef icmd_rd_1)) + ) + ) + (net N113 + (joined + (portRef O (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW2)) + (portRef I5 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o1)) + ) + ) + (net dop_clk_r_1_1 + (joined + (portRef Q (instanceRef dop_clk_r_1_1_renamed_44)) + (portRef I0 (instanceRef Mmux_GND_1_o_ishift_data_71__MUX_49_o11_SW1)) + ) + ) + ) + ) + ) + ) + + (design xjtag_bus + (cellRef xjtag_bus + (libraryRef xjtag_bus_lib) + ) + (property PART (string "xc7k70t-2-fbg676") (owner "Xilinx")) + ) +) + diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/.vivado.begin.rst b/localbus_demo/prj/localbus_demo.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..0ae02bf --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/.vivado.end.rst b/localbus_demo/prj/localbus_demo.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/ISEWrap.js b/localbus_demo/prj/localbus_demo.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000..898ddd7 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/ISEWrap.sh b/localbus_demo/prj/localbus_demo.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000..e1a8f5d --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/__synthesis_is_complete__ b/localbus_demo/prj/localbus_demo.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/gen_run.xml b/localbus_demo/prj/localbus_demo.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..fdf3b1d --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/gen_run.xml @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/htr.txt b/localbus_demo/prj/localbus_demo.runs/synth_1/htr.txt new file mode 100644 index 0000000..2e3b15a --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log t160_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/planAhead.ngc2edif.log b/localbus_demo/prj/localbus_demo.runs/synth_1/planAhead.ngc2edif.log new file mode 100644 index 0000000..308a392 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/planAhead.ngc2edif.log @@ -0,0 +1,11 @@ +Release 14.7 - ngc2edif P_INT.20180321 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design xjtag_bus.ngc ... +WARNING:NetListWriters:298 - No output is written to xjtag_bus.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file xjtag_bus.edif ... +ngc2edif: Total memory usage is 89576 kilobytes + diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/rundef.js b/localbus_demo/prj/localbus_demo.runs/synth_1/rundef.js new file mode 100644 index 0000000..3d60bce --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;"; +} else { + PathVal = "E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64;E:/Xilinx/Vivado/2018.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log t160_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/runme.bat b/localbus_demo/prj/localbus_demo.runs/synth_1/runme.bat new file mode 100644 index 0000000..73c8b46 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/runme.log b/localbus_demo/prj/localbus_demo.runs/synth_1/runme.log new file mode 100644 index 0000000..e88170f --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/runme.log @@ -0,0 +1,328 @@ + +*** Running vivado + with args -log t160_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl + + +****** Vivado v2018.2 (64-bit) + **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 + **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 + ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. + +source t160_top.tcl -notrace +Command: synth_design -top t160_top -part xc7k160tffg676-2 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 7116 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 394.238 ; gain = 93.113 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 't160_top' [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.v:1] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1/.Xil/Vivado-9016-PC2018/realtime/clk_wiz_0_stub.v:5] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (1#1) [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1/.Xil/Vivado-9016-PC2018/realtime/clk_wiz_0_stub.v:5] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (2#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6157] synthesizing module 'xjtag_bus' [D:/Xilinx/xjtag/xjtag_ip/localbus_ip/xjtag_bus.v:1] + Parameter JTAG_SEL bound to: 3 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'xjtag_bus' (3#1) [D:/Xilinx/xjtag/xjtag_ip/localbus_ip/xjtag_bus.v:1] +INFO: [Synth 8-6157] synthesizing module 'localbus_register' [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/localbus_register.v:1] + Parameter ver bound to: 538969620 - type: integer +INFO: [Synth 8-155] case statement is not full and has no default [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/localbus_register.v:49] +WARNING: [Synth 8-3848] Net localbus_finish in module/entity localbus_register does not have driver. [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/localbus_register.v:31] +INFO: [Synth 8-6155] done synthesizing module 'localbus_register' (4#1) [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/localbus_register.v:1] +INFO: [Synth 8-6155] done synthesizing module 't160_top' (5#1) [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.v:1] +WARNING: [Synth 8-3331] design localbus_register has unconnected port localbus_finish +WARNING: [Synth 8-3331] design localbus_register has unconnected port localbus_wmask[3] +WARNING: [Synth 8-3331] design localbus_register has unconnected port localbus_wmask[2] +WARNING: [Synth 8-3331] design localbus_register has unconnected port localbus_wmask[1] +WARNING: [Synth 8-3331] design localbus_register has unconnected port localbus_wmask[0] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.496 ; gain = 143.371 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.496 ; gain = 143.371 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.496 ; gain = 143.371 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_uut' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_uut' +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/t160_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/t160_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 786.301 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 786.301 ; gain = 485.176 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 786.301 ; gain = 485.176 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for sys_clkn. (constraint file d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 3). +Applied set_property CLOCK_BUFFER_TYPE = NONE for sys_clkn. (constraint file d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 4). +Applied set_property IO_BUFFER_TYPE = NONE for sys_clkp. (constraint file d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 5). +Applied set_property CLOCK_BUFFER_TYPE = NONE for sys_clkp. (constraint file d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6). +Applied set_property DONT_TOUCH = true for clk_uut. (constraint file auto generated constraint, line ). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 786.301 ; gain = 485.176 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5545] ROM "gpio0" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "ram0" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "ram1" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 786.301 ; gain = 485.176 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 4 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 + 4 Input 1 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module localbus_register +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 4 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 + 4 Input 1 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 786.301 ; gain = 485.176 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +INFO: [Synth 8-5578] Moved timing constraint from pin 'clk_uut/clk_out1' to pin 'clk_uut/bbstub_clk_out1/O' +INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 803.230 ; gain = 502.105 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |clk_wiz_0 | 1| +|2 |xjtag_bus | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+----------+------+ +| |Cell |Count | ++------+----------+------+ +|1 |clk_wiz_0 | 1| +|2 |xjtag_bus | 1| +|3 |BUFG | 1| +|4 |LUT1 | 1| +|5 |LUT4 | 38| +|6 |LUT5 | 5| +|7 |LUT6 | 38| +|8 |FDCE | 128| +|9 |OBUF | 4| ++------+----------+------+ + +Report Instance Areas: ++------+---------+------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------+------+ +|1 |top | | 319| +|2 | UUT |localbus_register | 209| ++------+---------+------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 814.613 ; gain = 171.684 +Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +INFO: [Project 1-571] Translating synthesized netlist +Release 14.7 - ngc2edif P_INT.20180321 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design xjtag_bus.ngc ... +WARNING:NetListWriters:298 - No output is written to xjtag_bus.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file xjtag_bus.edif ... +ngc2edif: Total memory usage is 89576 kilobytes + +Reading core file 'D:/Xilinx/xjtag/xjtag_ip/localbus_ip/xjtag_bus.ngc' for (cell view 'xjtag_bus', library 'work') +Parsing EDIF File [./.ngc2edfcache/xjtag_bus_ngc_697f0a13.edif] +Finished Parsing EDIF File [./.ngc2edfcache/xjtag_bus_ngc_697f0a13.edif] +INFO: [Netlist 29-17] Analyzing 68 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Xilinx ngc2edif P_INT.20180321 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 55 instances were transformed. + (MUXCY,XORCY) => CARRY4: 2 instances + BSCAN_SPARTAN6 => BSCANE2: 1 instances + FDC => FDCE: 49 instances + FDE => FDRE: 2 instances + INV => LUT1: 1 instances + +INFO: [Common 17-83] Releasing license: Synthesis +29 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 837.926 ; gain = 548.266 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file t160_top_utilization_synth.rpt -pb t160_top_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.084 . Memory (MB): peak = 837.926 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Sun Jun 28 17:14:25 2020... diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/runme.sh b/localbus_demo/prj/localbus_demo.runs/synth_1/runme.sh new file mode 100644 index 0000000..6c40ec3 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin +else + PATH=E:/Xilinx/SDK/2018.2/bin;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/bin/nt64;E:/Xilinx/Vivado/2018.2/ids_lite/ISE/lib/nt64:E:/Xilinx/Vivado/2018.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log t160_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.dcp b/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.dcp new file mode 100644 index 0000000..72a99f6 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.dcp differ diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.tcl b/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.tcl new file mode 100644 index 0000000..337f6fa --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.tcl @@ -0,0 +1,66 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +create_project -in_memory -part xc7k160tffg676-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.cache/wt [current_project] +set_property parent.project_path D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.xpr [current_project] +set_property XPM_LIBRARIES XPM_CDC [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/localbus_register.v + D:/Xilinx/xjtag/xjtag_ip/localbus_ip/xjtag_bus.v + D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.v +} +read_ip -quiet D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] +set_property used_in_implementation false [get_files -all d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] + +read_edif D:/Xilinx/xjtag/xjtag_ip/localbus_ip/xjtag_bus.ngc +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc +set_property used_in_implementation false [get_files D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top t160_top -part xc7k160tffg676-2 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef t160_top.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file t160_top_utilization_synth.rpt -pb t160_top_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.vds b/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.vds new file mode 100644 index 0000000..259b092 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.vds @@ -0,0 +1,329 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun Jun 28 17:13:52 2020 +# Process ID: 9016 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1 +# Command line: vivado.exe -log t160_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl +# Log file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.vds +# Journal file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source t160_top.tcl -notrace +Command: synth_design -top t160_top -part xc7k160tffg676-2 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 7116 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 394.238 ; gain = 93.113 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 't160_top' [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.v:1] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1/.Xil/Vivado-9016-PC2018/realtime/clk_wiz_0_stub.v:5] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (1#1) [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1/.Xil/Vivado-9016-PC2018/realtime/clk_wiz_0_stub.v:5] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (2#1) [E:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609] +INFO: [Synth 8-6157] synthesizing module 'xjtag_bus' [D:/Xilinx/xjtag/xjtag_ip/localbus_ip/xjtag_bus.v:1] + Parameter JTAG_SEL bound to: 3 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'xjtag_bus' (3#1) [D:/Xilinx/xjtag/xjtag_ip/localbus_ip/xjtag_bus.v:1] +INFO: [Synth 8-6157] synthesizing module 'localbus_register' [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/localbus_register.v:1] + Parameter ver bound to: 538969620 - type: integer +INFO: [Synth 8-155] case statement is not full and has no default [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/localbus_register.v:49] +WARNING: [Synth 8-3848] Net localbus_finish in module/entity localbus_register does not have driver. [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/localbus_register.v:31] +INFO: [Synth 8-6155] done synthesizing module 'localbus_register' (4#1) [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/localbus_register.v:1] +INFO: [Synth 8-6155] done synthesizing module 't160_top' (5#1) [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.v:1] +WARNING: [Synth 8-3331] design localbus_register has unconnected port localbus_finish +WARNING: [Synth 8-3331] design localbus_register has unconnected port localbus_wmask[3] +WARNING: [Synth 8-3331] design localbus_register has unconnected port localbus_wmask[2] +WARNING: [Synth 8-3331] design localbus_register has unconnected port localbus_wmask[1] +WARNING: [Synth 8-3331] design localbus_register has unconnected port localbus_wmask[0] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.496 ; gain = 143.371 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.496 ; gain = 143.371 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 444.496 ; gain = 143.371 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7k160tffg676-2 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_uut' +Finished Parsing XDC File [d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_uut' +Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc] +Finished Parsing XDC File [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx/xjtag/xjtag_ip/localbus_demo/src/t160_top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/t160_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/t160_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 786.301 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 786.301 ; gain = 485.176 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tffg676-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 786.301 ; gain = 485.176 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for sys_clkn. (constraint file d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 3). +Applied set_property CLOCK_BUFFER_TYPE = NONE for sys_clkn. (constraint file d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 4). +Applied set_property IO_BUFFER_TYPE = NONE for sys_clkp. (constraint file d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 5). +Applied set_property CLOCK_BUFFER_TYPE = NONE for sys_clkp. (constraint file d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6). +Applied set_property DONT_TOUCH = true for clk_uut. (constraint file auto generated constraint, line ). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 786.301 ; gain = 485.176 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5545] ROM "gpio0" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "ram0" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "ram1" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 786.301 ; gain = 485.176 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 4 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 + 4 Input 1 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module localbus_register +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 4 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 + 4 Input 1 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 786.301 ; gain = 485.176 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +INFO: [Synth 8-5578] Moved timing constraint from pin 'clk_uut/clk_out1' to pin 'clk_uut/bbstub_clk_out1/O' +INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 803.230 ; gain = 502.105 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |clk_wiz_0 | 1| +|2 |xjtag_bus | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+----------+------+ +| |Cell |Count | ++------+----------+------+ +|1 |clk_wiz_0 | 1| +|2 |xjtag_bus | 1| +|3 |BUFG | 1| +|4 |LUT1 | 1| +|5 |LUT4 | 38| +|6 |LUT5 | 5| +|7 |LUT6 | 38| +|8 |FDCE | 128| +|9 |OBUF | 4| ++------+----------+------+ + +Report Instance Areas: ++------+---------+------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------+------+ +|1 |top | | 319| +|2 | UUT |localbus_register | 209| ++------+---------+------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 814.613 ; gain = 171.684 +Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 814.613 ; gain = 513.488 +INFO: [Project 1-571] Translating synthesized netlist +Release 14.7 - ngc2edif P_INT.20180321 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design xjtag_bus.ngc ... +WARNING:NetListWriters:298 - No output is written to xjtag_bus.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file xjtag_bus.edif ... +ngc2edif: Total memory usage is 89576 kilobytes + +Reading core file 'D:/Xilinx/xjtag/xjtag_ip/localbus_ip/xjtag_bus.ngc' for (cell view 'xjtag_bus', library 'work') +Parsing EDIF File [./.ngc2edfcache/xjtag_bus_ngc_697f0a13.edif] +Finished Parsing EDIF File [./.ngc2edfcache/xjtag_bus_ngc_697f0a13.edif] +INFO: [Netlist 29-17] Analyzing 68 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Xilinx ngc2edif P_INT.20180321 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 55 instances were transformed. + (MUXCY,XORCY) => CARRY4: 2 instances + BSCAN_SPARTAN6 => BSCANE2: 1 instances + FDC => FDCE: 49 instances + FDE => FDRE: 2 instances + INV => LUT1: 1 instances + +INFO: [Common 17-83] Releasing license: Synthesis +29 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 837.926 ; gain = 548.266 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file t160_top_utilization_synth.rpt -pb t160_top_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.084 . Memory (MB): peak = 837.926 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Sun Jun 28 17:14:25 2020... diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top_utilization_synth.pb b/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top_utilization_synth.pb new file mode 100644 index 0000000..efb6d6b Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top_utilization_synth.pb differ diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top_utilization_synth.rpt b/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top_utilization_synth.rpt new file mode 100644 index 0000000..4fcea06 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top_utilization_synth.rpt @@ -0,0 +1,188 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Sun Jun 28 17:14:25 2020 +| Host : PC2018 running 64-bit Service Pack 1 (build 7601) +| Command : report_utilization -file t160_top_utilization_synth.rpt -pb t160_top_utilization_synth.pb +| Design : t160_top +| Device : 7k160tffg676-2 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 295 | 0 | 101400 | 0.29 | +| LUT as Logic | 295 | 0 | 101400 | 0.29 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 391 | 0 | 202800 | 0.19 | +| Register as Flip Flop | 391 | 0 | 202800 | 0.19 | +| Register as Latch | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 389 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 2 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 4 | 0 | 400 | 1.00 | +| Bonded IPADs | 0 | 0 | 26 | 0.00 | +| Bonded OPADs | 0 | 0 | 16 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 384 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 2 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 8 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 400 | 0.00 | +| OLOGIC | 0 | 0 | 400 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 1 | 0 | 4 | 25.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 389 | Flop & Latch | +| LUT2 | 102 | LUT | +| LUT6 | 78 | LUT | +| LUT3 | 49 | LUT | +| LUT4 | 42 | LUT | +| LUT5 | 38 | LUT | +| OBUF | 4 | IO | +| LUT1 | 2 | LUT | +| FDRE | 2 | Flop & Latch | +| CARRY4 | 2 | CarryLogic | +| BUFG | 1 | Clock | +| BSCANE2 | 1 | Others | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++-----------+------+ +| Ref Name | Used | ++-----------+------+ +| clk_wiz_0 | 1 | ++-----------+------+ + + +9. Instantiated Netlists +------------------------ + ++-----------+------+ +| Ref Name | Used | ++-----------+------+ +| xjtag_bus | 1 | ++-----------+------+ + + diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/vivado.jou b/localbus_demo/prj/localbus_demo.runs/synth_1/vivado.jou new file mode 100644 index 0000000..e5a4fdd --- /dev/null +++ b/localbus_demo/prj/localbus_demo.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Sun Jun 28 17:13:52 2020 +# Process ID: 9016 +# Current directory: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1 +# Command line: vivado.exe -log t160_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source t160_top.tcl +# Log file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1/t160_top.vds +# Journal file: D:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source t160_top.tcl -notrace diff --git a/localbus_demo/prj/localbus_demo.runs/synth_1/vivado.pb b/localbus_demo/prj/localbus_demo.runs/synth_1/vivado.pb new file mode 100644 index 0000000..669eceb Binary files /dev/null and b/localbus_demo/prj/localbus_demo.runs/synth_1/vivado.pb differ diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp new file mode 100644 index 0000000..1cdd355 Binary files /dev/null and b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp differ diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v new file mode 100644 index 0000000..656ec32 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v @@ -0,0 +1,92 @@ + +// file: clk_wiz_0.v +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1___100.000______0.000______50.0______130.958_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_1_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) + +module clk_wiz_0 + ( + // Clock out ports + output clk_out1, + // Status and control signals + output locked, + // Clock in ports + input clk_in1_p, + input clk_in1_n + ); + + clk_wiz_0_clk_wiz inst + ( + // Clock out ports + .clk_out1(clk_out1), + // Status and control signals + .locked(locked), + // Clock in ports + .clk_in1_p(clk_in1_p), + .clk_in1_n(clk_in1_n) + ); + +endmodule diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo new file mode 100644 index 0000000..fa730ab --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo @@ -0,0 +1,80 @@ + +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1___100.000______0.000______50.0______130.958_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clk_wiz_0 instance_name + ( + // Clock out ports + .clk_out1(clk_out1), // output clk_out1 + // Status and control signals + .locked(locked), // output locked + // Clock in ports + .clk_in1_p(clk_in1_p), // input clk_in1_p + .clk_in1_n(clk_in1_n)); // input clk_in1_n +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci new file mode 100644 index 0000000..2369f71 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -0,0 +1,657 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_0 + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 100.0 + 0000 + 0000 + 100.000 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 1.0 + 1.0 + 1.0 + 1.0 + 1.0 + 1.0 + dout + drdy + dwe + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________100.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 10.000 + 0.000 + FALSE + 10.000 + 10.000 + 10.000 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 1 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out1___100.000______0.000______50.0______130.958_____98.575 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 100.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + clk_wiz_0 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 130.958 + false + 98.575 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_0 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 10.000 + 0.000 + false + 10.000 + 10.000 + 10.000 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 1 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 100.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + false + false + false + false + kintex7 + + xc7k160t + ffg676 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2018.2 + OUT_OF_CONTEXT + + + + + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc new file mode 100644 index 0000000..d15cb6a --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc @@ -0,0 +1,60 @@ + +# file: clk_wiz_0.xdc +# +# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system. If required +# commented constraints can be used in the top level xdc +#---------------------------------------------------------------- +# Differential clock only needs one constraint +create_clock -period 10.000 [get_ports clk_in1_p] +set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.1 + + +set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml new file mode 100644 index 0000000..deae809 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml @@ -0,0 +1,4712 @@ + + + xilinx.com + customized_ip + clk_wiz_0 + 1.0 + + + s_axi_lite + S_AXI_LITE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 1 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + 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+ + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_IN_D + CLKFB_IN_D + Differential Feedback Clock input + + + + + + + CLK_N + + + clkfb_in_n + + + + + CLK_P + + + clkfb_in_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_OUT_D + CLKFB_OUT_D + Differential Feeback Clock Output + + + + + + + CLK_N + + + clkfb_out_n + + + + + CLK_P + + + clkfb_out_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + reset + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_HIGH + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + + + + false + + + + + + resetn + resetn + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + + + + false + + + + + + clock_CLK_OUT1 + + + + + + + CLK_OUT1 + + + clk_out1 + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + + + + xilinx_elaborateports + Elaborate Ports + :vivado.xilinx.com:elaborate.ports + + + outputProductCRC + 8:563fd370 + + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + clk_wiz_v6_0_1 + + xilinx_veriloginstantiationtemplate_view_fileset + + + + GENtimestamp + Sun Jun 28 04:07:02 UTC 2020 + + + outputProductCRC + 8:d0c16f9e + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + clk_wiz_v6_0_1 + + xilinx_anylanguagesynthesis_view_fileset + + + + GENtimestamp + Sun Jun 28 04:07:06 UTC 2020 + + + outputProductCRC + 8:d0c16f9e + + + + + xilinx_anylanguagesynthesiswrapper + Synthesis Wrapper + :vivado.xilinx.com:synthesis.wrapper + clk_wiz_0 + + xilinx_anylanguagesynthesiswrapper_view_fileset + + + + GENtimestamp + Sun Jun 28 04:07:06 UTC 2020 + + + outputProductCRC + 8:d0c16f9e + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + clk_wiz_v6_0_1 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Sun Jun 28 04:07:06 UTC 2020 + + + outputProductCRC + 8:82d1bf70 + + + + + xilinx_anylanguagesimulationwrapper + Simulation Wrapper + :vivado.xilinx.com:simulation.wrapper + clk_wiz_0 + + xilinx_anylanguagesimulationwrapper_view_fileset + + + + GENtimestamp + Sun Jun 28 04:07:06 UTC 2020 + + + outputProductCRC + 8:82d1bf70 + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + GENtimestamp + Sun Jun 28 04:07:07 UTC 2020 + + + outputProductCRC + 8:d0c16f9e + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + GENtimestamp + Sun Jun 28 04:07:07 UTC 2020 + + + outputProductCRC + 8:d0c16f9e + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Sun Jun 28 04:07:42 UTC 2020 + + + outputProductCRC + 8:d0c16f9e + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awaddr + + in + + 10 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awready + + out + + + std_logic + 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+ + false + + + + + + clk_out1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + locked + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + C_CLKOUT2_USED + 0 + + + C_USER_CLK_FREQ0 + 100.0 + + + C_AUTO_PRIMITIVE + MMCM + + + C_USER_CLK_FREQ1 + 100.0 + + + C_USER_CLK_FREQ2 + 100.0 + + + C_USER_CLK_FREQ3 + 100.0 + + + C_ENABLE_CLOCK_MONITOR + 0 + + + C_ENABLE_USER_CLOCK0 + 0 + + + C_ENABLE_USER_CLOCK1 + 0 + + + C_ENABLE_USER_CLOCK2 + 0 + + + C_ENABLE_USER_CLOCK3 + 0 + + + C_Enable_PLL0 + 0 + + + C_Enable_PLL1 + 0 + + + C_REF_CLK_FREQ + 100.0 + + + C_PRECISION + 1 + + + C_CLKOUT3_USED + 0 + + + C_CLKOUT4_USED + 0 + + + C_CLKOUT5_USED + 0 + + + C_CLKOUT6_USED + 0 + + + C_CLKOUT7_USED + 0 + + + C_USE_CLKOUT1_BAR + 0 + + + C_USE_CLKOUT2_BAR + 0 + + + C_USE_CLKOUT3_BAR + 0 + + + C_USE_CLKOUT4_BAR + 0 + + + c_component_name + clk_wiz_0 + + + C_PLATFORM + UNKNOWN + + + C_USE_FREQ_SYNTH + 1 + + + C_USE_PHASE_ALIGNMENT + 1 + + + C_PRIM_IN_JITTER + 0.010 + + + C_SECONDARY_IN_JITTER + 0.010 + + + C_JITTER_SEL + No_Jitter + + + C_USE_MIN_POWER + 0 + + + C_USE_MIN_O_JITTER + 0 + + + C_USE_MAX_I_JITTER + 0 + + + C_USE_DYN_PHASE_SHIFT + 0 + + + C_USE_INCLK_SWITCHOVER + 0 + + + C_USE_DYN_RECONFIG + 0 + + + C_USE_SPREAD_SPECTRUM + 0 + + + C_USE_FAST_SIMULATION + 0 + + + C_PRIMTYPE_SEL + AUTO + + + C_USE_CLK_VALID + 0 + + + C_PRIM_IN_FREQ + 100.000 + + + C_PRIM_IN_TIMEPERIOD + 10.000 + + + C_IN_FREQ_UNITS + Units_MHz + + + C_SECONDARY_IN_FREQ + 100.000 + + + C_SECONDARY_IN_TIMEPERIOD + 10.000 + + + C_FEEDBACK_SOURCE + FDBK_AUTO + + + C_PRIM_SOURCE + Differential_clock_capable_pin + + + C_PHASESHIFT_MODE + WAVEFORM + + + C_SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + C_CLKFB_IN_SIGNALING + SINGLE + + + C_USE_RESET + 0 + + + C_RESET_LOW + 0 + + + C_USE_LOCKED + 1 + + + C_USE_INCLK_STOPPED + 0 + + + C_USE_CLKFB_STOPPED + 0 + + + C_USE_POWER_DOWN + 0 + + + C_USE_STATUS + 0 + + + C_USE_FREEZE + 0 + + + C_NUM_OUT_CLKS + 1 + + + C_CLKOUT1_DRIVES + BUFG + + + C_CLKOUT2_DRIVES + BUFG + + + C_CLKOUT3_DRIVES + BUFG + + + C_CLKOUT4_DRIVES + BUFG + + + C_CLKOUT5_DRIVES + BUFG + + + C_CLKOUT6_DRIVES + BUFG + + + C_CLKOUT7_DRIVES + BUFG + + + C_INCLK_SUM_ROW0 + Input Clock Freq (MHz) Input Jitter (UI) + + + C_INCLK_SUM_ROW1 + __primary_________100.000____________0.010 + + + C_INCLK_SUM_ROW2 + no_secondary_input_clock + + + C_OUTCLK_SUM_ROW0A + C Outclk Sum Row0a + Output Output Phase Duty Cycle Pk-to-Pk Phase + + + C_OUTCLK_SUM_ROW0B + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + + + C_OUTCLK_SUM_ROW1 + clk_out1___100.000______0.000______50.0______130.958_____98.575 + + + C_OUTCLK_SUM_ROW2 + no_CLK_OUT2_output + + + C_OUTCLK_SUM_ROW3 + no_CLK_OUT3_output + + + C_OUTCLK_SUM_ROW4 + no_CLK_OUT4_output + + + C_OUTCLK_SUM_ROW5 + no_CLK_OUT5_output + + + C_OUTCLK_SUM_ROW6 + no_CLK_OUT6_output + + + C_OUTCLK_SUM_ROW7 + no_CLK_OUT7_output + + + C_CLKOUT1_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT1_REQUESTED_PHASE + 0.000 + + + C_CLKOUT2_REQUESTED_PHASE + 0.000 + + + C_CLKOUT3_REQUESTED_PHASE + 0.000 + + + C_CLKOUT4_REQUESTED_PHASE + 0.000 + + + C_CLKOUT5_REQUESTED_PHASE + 0.000 + + + C_CLKOUT6_REQUESTED_PHASE + 0.000 + + + C_CLKOUT7_REQUESTED_PHASE + 0.000 + + + C_CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT1_OUT_FREQ + 100.000 + + + C_CLKOUT2_OUT_FREQ + 100.000 + + + C_CLKOUT3_OUT_FREQ + 100.000 + + + C_CLKOUT4_OUT_FREQ + 100.000 + + + C_CLKOUT5_OUT_FREQ + 100.000 + + + C_CLKOUT6_OUT_FREQ + 100.000 + + + C_CLKOUT7_OUT_FREQ + 100.000 + + + C_CLKOUT1_PHASE + 0.000 + + + C_CLKOUT2_PHASE + 0.000 + + + C_CLKOUT3_PHASE + 0.000 + + + C_CLKOUT4_PHASE + 0.000 + + + C_CLKOUT5_PHASE + 0.000 + + + C_CLKOUT6_PHASE + 0.000 + + + C_CLKOUT7_PHASE + 0.000 + + + C_CLKOUT1_DUTY_CYCLE + 50.0 + + + C_CLKOUT2_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_DUTY_CYCLE + 50.000 + + + C_USE_SAFE_CLOCK_STARTUP + 0 + + + C_USE_CLOCK_SEQUENCING + 0 + + + C_CLKOUT1_SEQUENCE_NUMBER + 1 + + + C_CLKOUT2_SEQUENCE_NUMBER + 1 + + + C_CLKOUT3_SEQUENCE_NUMBER + 1 + + + C_CLKOUT4_SEQUENCE_NUMBER + 1 + + + C_CLKOUT5_SEQUENCE_NUMBER + 1 + + + C_CLKOUT6_SEQUENCE_NUMBER + 1 + + + C_CLKOUT7_SEQUENCE_NUMBER + 1 + + + C_MMCM_NOTES + None + + + C_MMCM_BANDWIDTH + OPTIMIZED + + + C_MMCM_CLKFBOUT_MULT_F + 10.000 + + + C_MMCM_CLKIN1_PERIOD + 10.000 + + + C_MMCM_CLKIN2_PERIOD + 10.000 + + + C_MMCM_CLKOUT4_CASCADE + FALSE + + + C_MMCM_CLOCK_HOLD + FALSE + + + C_MMCM_COMPENSATION + ZHOLD + + + C_MMCM_DIVCLK_DIVIDE + 1 + + + C_MMCM_REF_JITTER1 + 0.010 + + + C_MMCM_REF_JITTER2 + 0.010 + + + C_MMCM_STARTUP_WAIT + FALSE + + + C_MMCM_CLKOUT0_DIVIDE_F + 10.000 + + + C_MMCM_CLKOUT1_DIVIDE + 1 + + + C_MMCM_CLKOUT2_DIVIDE + 1 + + + C_MMCM_CLKOUT3_DIVIDE + 1 + + + C_MMCM_CLKOUT4_DIVIDE + 1 + + + C_MMCM_CLKOUT5_DIVIDE + 1 + + + C_MMCM_CLKOUT6_DIVIDE + 1 + + + C_MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKFBOUT_PHASE + 0.000 + + + C_MMCM_CLKOUT0_PHASE + 0.000 + + + C_MMCM_CLKOUT1_PHASE + 0.000 + + + C_MMCM_CLKOUT2_PHASE + 0.000 + + + C_MMCM_CLKOUT3_PHASE + 0.000 + + + C_MMCM_CLKOUT4_PHASE + 0.000 + + + C_MMCM_CLKOUT5_PHASE + 0.000 + + + C_MMCM_CLKOUT6_PHASE + 0.000 + + + C_MMCM_CLKFBOUT_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT0_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT1_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT2_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT3_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT4_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT5_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT6_USE_FINE_PS + FALSE + + + C_PLL_NOTES + No notes + + + C_PLL_BANDWIDTH + OPTIMIZED + + + C_PLL_CLK_FEEDBACK + CLKFBOUT + + + C_PLL_CLKFBOUT_MULT + 1 + + + C_PLL_CLKIN_PERIOD + 1.000 + + + C_PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + C_PLL_DIVCLK_DIVIDE + 1 + + + C_PLL_REF_JITTER + 0.010 + + + C_PLL_CLKOUT0_DIVIDE + 1 + + + C_PLL_CLKOUT1_DIVIDE + 1 + + + C_PLL_CLKOUT2_DIVIDE + 1 + + + C_PLL_CLKOUT3_DIVIDE + 1 + + + C_PLL_CLKOUT4_DIVIDE + 1 + + + C_PLL_CLKOUT5_DIVIDE + 1 + + + C_PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_PLL_CLKFBOUT_PHASE + 0.000 + + + C_PLL_CLKOUT0_PHASE + 0.000 + + + C_PLL_CLKOUT1_PHASE + 0.000 + + + C_PLL_CLKOUT2_PHASE + 0.000 + + + C_PLL_CLKOUT3_PHASE + 0.000 + + + C_PLL_CLKOUT4_PHASE + 0.000 + + + C_PLL_CLKOUT5_PHASE + 0.000 + + + C_CLOCK_MGR_TYPE + NA + + + C_OVERRIDE_MMCM + 0 + + + C_OVERRIDE_PLL + 0 + + + C_PRIMARY_PORT + clk_in1 + + + C_SECONDARY_PORT + clk_in2 + + + C_CLK_OUT1_PORT + clk_out1 + + + C_CLK_OUT2_PORT + clk_out2 + + + C_CLK_OUT3_PORT + clk_out3 + + + C_CLK_OUT4_PORT + clk_out4 + + + C_CLK_OUT5_PORT + clk_out5 + + + C_CLK_OUT6_PORT + clk_out6 + + + C_CLK_OUT7_PORT + clk_out7 + + + C_RESET_PORT + reset + + + C_LOCKED_PORT + locked + + + C_CLKFB_IN_PORT + clkfb_in + + + C_CLKFB_IN_P_PORT + clkfb_in_p + + + C_CLKFB_IN_N_PORT + clkfb_in_n + + + C_CLKFB_OUT_PORT + clkfb_out + + + C_CLKFB_OUT_P_PORT + clkfb_out_p + + + C_CLKFB_OUT_N_PORT + clkfb_out_n + + + C_POWER_DOWN_PORT + power_down + + + C_DADDR_PORT + daddr + + + C_DCLK_PORT + dclk + + + C_DRDY_PORT + drdy + + + C_DWE_PORT + dwe + + + C_DIN_PORT + din + + + C_DOUT_PORT + dout + + + C_DEN_PORT + den + + + C_PSCLK_PORT + psclk + + + C_PSEN_PORT + psen + + + C_PSINCDEC_PORT + psincdec + + + C_PSDONE_PORT + psdone + + + C_CLK_VALID_PORT + CLK_VALID + + + C_STATUS_PORT + STATUS + + + C_CLK_IN_SEL_PORT + clk_in_sel + + + C_INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + C_CLKFB_STOPPED_PORT + clkfb_stopped + + + C_CLKIN1_JITTER_PS + 100.0 + + + C_CLKIN2_JITTER_PS + 100.0 + + + C_PRIMITIVE + MMCM + + + C_SS_MODE + CENTER_HIGH + + + C_SS_MOD_PERIOD + 4000 + + + C_SS_MOD_TIME + 0.004 + + + C_HAS_CDDC + 0 + + + C_CDDCDONE_PORT + cddcdone + + + C_CDDCREQ_PORT + cddcreq + + + C_CLKOUTPHY_MODE + VCO + + + C_ENABLE_CLKOUTPHY + 0 + + + C_INTERFACE_SELECTION + 0 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 11 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_POWER_REG + 0000 + + + C_CLKOUT0_1 + 0000 + + + C_CLKOUT0_2 + 0000 + + + C_CLKOUT1_1 + 0000 + + + C_CLKOUT1_2 + 0000 + + + C_CLKOUT2_1 + 0000 + + + C_CLKOUT2_2 + 0000 + + + C_CLKOUT3_1 + 0000 + + + C_CLKOUT3_2 + 0000 + + + C_CLKOUT4_1 + 0000 + + + C_CLKOUT4_2 + 0000 + + + C_CLKOUT5_1 + 0000 + + + C_CLKOUT5_2 + 0000 + + + C_CLKOUT6_1 + 0000 + + + C_CLKOUT6_2 + 0000 + + + C_CLKFBOUT_1 + 0000 + + + C_CLKFBOUT_2 + 0000 + + + C_DIVCLK + 0000 + + + C_LOCK_1 + 0000 + + + C_LOCK_2 + 0000 + + + C_LOCK_3 + 0000 + + + C_FILTER_1 + 0000 + + + C_FILTER_2 + 0000 + + + C_DIVIDE1_AUTO + 1 + + + C_DIVIDE2_AUTO + 1.0 + + + C_DIVIDE3_AUTO + 1.0 + + + C_DIVIDE4_AUTO + 1.0 + + + C_DIVIDE5_AUTO + 1.0 + + + C_DIVIDE6_AUTO + 1.0 + + + C_DIVIDE7_AUTO + 1.0 + + + C_PLLBUFGCEDIV + false + + + C_MMCMBUFGCEDIV + false + + + C_PLLBUFGCEDIV1 + false + + + C_PLLBUFGCEDIV2 + false + + + C_PLLBUFGCEDIV3 + false + + + C_PLLBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV1 + false + + + C_MMCMBUFGCEDIV2 + false + + + C_MMCMBUFGCEDIV3 + false + + + C_MMCMBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV5 + false + + + C_MMCMBUFGCEDIV6 + false + + + C_MMCMBUFGCEDIV7 + false + + + C_CLKOUT1_MATCHED_ROUTING + false + + + C_CLKOUT2_MATCHED_ROUTING + false + + + C_CLKOUT3_MATCHED_ROUTING + false + + + C_CLKOUT4_MATCHED_ROUTING + false + + + C_CLKOUT5_MATCHED_ROUTING + false + + + C_CLKOUT6_MATCHED_ROUTING + false + + + C_CLKOUT7_MATCHED_ROUTING + false + + + C_CLKOUT0_ACTUAL_FREQ + 100.000 + + + C_CLKOUT1_ACTUAL_FREQ + 100.000 + + + C_CLKOUT2_ACTUAL_FREQ + 100.000 + + + C_CLKOUT3_ACTUAL_FREQ + 100.000 + + + C_CLKOUT4_ACTUAL_FREQ + 100.000 + + + C_CLKOUT5_ACTUAL_FREQ + 100.000 + + + C_CLKOUT6_ACTUAL_FREQ + 100.000 + + + + + + choice_list_1d3de01d + WAVEFORM + LATENCY + + + choice_list_876bfc32 + UI + PS + + + choice_list_a9bdfce0 + LOW + HIGH + OPTIMIZED + + + choice_list_ac75ef1e + Custom + + + choice_list_b9d38208 + CLKFBOUT + CLKOUT0 + + + choice_list_e099fe6c + MMCM + PLL + + + choice_pairs_035ca1c3 + SYSTEM_SYNCHRONOUS + SOURCE_SYNCHRONOUS + INTERNAL + EXTERNAL + + + choice_pairs_0920eb1b + Custom + sys_diff_clock + + + choice_pairs_11d71346 + Single_ended_clock_capable_pin + Differential_clock_capable_pin + Global_buffer + No_buffer + + + choice_pairs_15c806d5 + FDBK_AUTO + FDBK_AUTO_OFFCHIP + FDBK_ONCHIP + FDBK_OFFCHIP + + + choice_pairs_340369e0 + Custom + sys_clock + sys_diff_clock + + + choice_pairs_3c2d3ec7 + SINGLE + DIFF + + + choice_pairs_502d9f23 + ZHOLD + EXTERNAL + INTERNAL + BUF_IN + + + choice_pairs_66e4c81f + BUFG + BUFH + BUFGCE + BUFHCE + No_buffer + + + choice_pairs_77d3d587 + MMCM + PLL + BUFGCE_DIV + + + choice_pairs_8b28f1f7 + Enable_AXI + Enable_DRP + + + choice_pairs_8eea9b32 + Units_MHz + Units_ns + + + choice_pairs_a4fbc00c + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a8642b4c + No_Jitter + Min_O_Jitter + Max_I_Jitter + + + choice_pairs_c5ef7212 + Units_UI + Units_ps + + + choice_pairs_e1c87518 + REL_PRIMARY + REL_SECONDARY + + + choice_pairs_f4e10086 + CENTER_HIGH + CENTER_LOW + DOWN_HIGH + DOWN_LOW + + + choice_pairs_f669c2f5 + frequency + Time + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + clk_wiz_0.veo + verilogTemplate + + + + xilinx_anylanguagesynthesis_view_fileset + + clk_wiz_0.xdc + xdc + + processing_order + early + + + + clk_wiz_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_7s_pll.vh + verilogSource + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_mmcm.vh + verilogSource + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_pll.vh + verilogSource + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + true + clk_wiz_v6_0_1 + + + clk_wiz_0_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesynthesiswrapper_view_fileset + + clk_wiz_0.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_7s_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_1 + + + clk_wiz_0_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesimulationwrapper_view_fileset + + clk_wiz_0.v + verilogSource + + + + xilinx_implementation_view_fileset + + clk_wiz_0_board.xdc + xdc + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + xilinx_versioninformation_view_fileset + + doc/clk_wiz_v6_0_changelog.txt + text + + + + xilinx_externalfiles_view_fileset + + clk_wiz_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + clk_wiz_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + clk_wiz_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + clk_wiz_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + clk_wiz_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. + + + Component_Name + clk_wiz_0 + + + USER_CLK_FREQ0 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ1 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ2 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ3 + User Frequency(MHz) + 100.0 + + + ENABLE_CLOCK_MONITOR + Enable Clock Monitoring + false + + + ENABLE_USER_CLOCK0 + User Clock + false + + + ENABLE_USER_CLOCK1 + User Clock + false + + + ENABLE_USER_CLOCK2 + User Clock + false + + + ENABLE_USER_CLOCK3 + User Clock + false + + + Enable_PLL0 + User Clock + false + + + Enable_PLL1 + User Clock + false + + + REF_CLK_FREQ + Reference Frequency(MHz) + 100.0 + + + PRECISION + Tolerance(MHz) + 1 + + + PRIMITIVE + Primitive + MMCM + + + PRIMTYPE_SEL + Primtype Sel + mmcm_adv + + + CLOCK_MGR_TYPE + Clock Mgr Type + auto + + + USE_FREQ_SYNTH + true + + + USE_SPREAD_SPECTRUM + false + + + USE_PHASE_ALIGNMENT + true + + + USE_MIN_POWER + false + + + USE_DYN_PHASE_SHIFT + false + + + USE_DYN_RECONFIG + false + + + JITTER_SEL + No_Jitter + + + PRIM_IN_FREQ + 100.000 + + + PRIM_IN_TIMEPERIOD + 10.000 + + + IN_FREQ_UNITS + Units_MHz + + + PHASESHIFT_MODE + WAVEFORM + + + IN_JITTER_UNITS + Units_UI + + + RELATIVE_INCLK + REL_PRIMARY + + + USE_INCLK_SWITCHOVER + false + + + SECONDARY_IN_FREQ + 100.000 + + + SECONDARY_IN_TIMEPERIOD + 10.000 + + + SECONDARY_PORT + clk_in2 + + + SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + JITTER_OPTIONS + UI + + + CLKIN1_UI_JITTER + 0.010 + + + CLKIN2_UI_JITTER + 0.010 + + + PRIM_IN_JITTER + 0.010 + + + SECONDARY_IN_JITTER + 0.010 + + + CLKIN1_JITTER_PS + 100.0 + + + CLKIN2_JITTER_PS + 100.0 + + + CLKOUT1_USED + true + + + CLKOUT2_USED + false + + + CLKOUT3_USED + false + + + CLKOUT4_USED + false + + + CLKOUT5_USED + false + + + CLKOUT6_USED + false + + + CLKOUT7_USED + false + + + NUM_OUT_CLKS + 1 + + + CLK_OUT1_USE_FINE_PS_GUI + false + + + CLK_OUT2_USE_FINE_PS_GUI + false + + + CLK_OUT3_USE_FINE_PS_GUI + false + + + CLK_OUT4_USE_FINE_PS_GUI + false + + + CLK_OUT5_USE_FINE_PS_GUI + false + + + CLK_OUT6_USE_FINE_PS_GUI + false + + + CLK_OUT7_USE_FINE_PS_GUI + false + + + PRIMARY_PORT + clk_in1 + + + CLK_OUT1_PORT + clk_out1 + + + CLK_OUT2_PORT + clk_out2 + + + CLK_OUT3_PORT + clk_out3 + + + CLK_OUT4_PORT + clk_out4 + + + CLK_OUT5_PORT + clk_out5 + + + CLK_OUT6_PORT + clk_out6 + + + CLK_OUT7_PORT + clk_out7 + + + DADDR_PORT + daddr + + + DCLK_PORT + dclk + + + DRDY_PORT + drdy + + + DWE_PORT + dwe + + + DIN_PORT + din + + + DOUT_PORT + dout + + + DEN_PORT + den + + + PSCLK_PORT + psclk + + + PSEN_PORT + psen + + + PSINCDEC_PORT + psincdec + + + PSDONE_PORT + psdone + + + CLKOUT1_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT1_REQUESTED_PHASE + 0.000 + + + CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT2_REQUESTED_PHASE + 0.000 + + + CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT3_REQUESTED_PHASE + 0.000 + + + CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT4_REQUESTED_PHASE + 0.000 + + + CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT5_REQUESTED_PHASE + 0.000 + + + CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT6_REQUESTED_PHASE + 0.000 + + + CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT7_REQUESTED_PHASE + 0.000 + + + CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + USE_MAX_I_JITTER + false + + + USE_MIN_O_JITTER + false + + + CLKOUT1_MATCHED_ROUTING + false + + + CLKOUT2_MATCHED_ROUTING + false + + + CLKOUT3_MATCHED_ROUTING + false + + + CLKOUT4_MATCHED_ROUTING + false + + + CLKOUT5_MATCHED_ROUTING + false + + + CLKOUT6_MATCHED_ROUTING + false + + + CLKOUT7_MATCHED_ROUTING + false + + + PRIM_SOURCE + Differential_clock_capable_pin + + + CLKOUT1_DRIVES + BUFG + + + CLKOUT2_DRIVES + BUFG + + + CLKOUT3_DRIVES + BUFG + + + CLKOUT4_DRIVES + BUFG + + + CLKOUT5_DRIVES + BUFG + + + CLKOUT6_DRIVES + BUFG + + + CLKOUT7_DRIVES + BUFG + + + FEEDBACK_SOURCE + FDBK_AUTO + + + CLKFB_IN_SIGNALING + SINGLE + + + CLKFB_IN_PORT + clkfb_in + + + CLKFB_IN_P_PORT + clkfb_in_p + + + CLKFB_IN_N_PORT + clkfb_in_n + + + CLKFB_OUT_PORT + clkfb_out + + + CLKFB_OUT_P_PORT + clkfb_out_p + + + CLKFB_OUT_N_PORT + clkfb_out_n + + + PLATFORM + UNKNOWN + + + SUMMARY_STRINGS + empty + + + USE_LOCKED + true + + + CALC_DONE + empty + + + USE_RESET + false + + + USE_POWER_DOWN + false + + + USE_STATUS + false + + + USE_FREEZE + false + + + USE_CLK_VALID + false + + + USE_INCLK_STOPPED + false + + + USE_CLKFB_STOPPED + false + + + RESET_PORT + reset + + + LOCKED_PORT + locked + + + POWER_DOWN_PORT + power_down + + + CLK_VALID_PORT + CLK_VALID + + + STATUS_PORT + STATUS + + + CLK_IN_SEL_PORT + clk_in_sel + + + INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + CLKFB_STOPPED_PORT + clkfb_stopped + + + SS_MODE + CENTER_HIGH + + + SS_MOD_FREQ + 250 + + + SS_MOD_TIME + 0.004 + + + OVERRIDE_MMCM + false + + + MMCM_NOTES + None + + + MMCM_DIVCLK_DIVIDE + 1 + + + MMCM_BANDWIDTH + OPTIMIZED + + + MMCM_CLKFBOUT_MULT_F + 10.000 + + + MMCM_CLKFBOUT_PHASE + 0.000 + + + MMCM_CLKFBOUT_USE_FINE_PS + false + + + MMCM_CLKIN1_PERIOD + 10.000 + + + MMCM_CLKIN2_PERIOD + 10.000 + + + MMCM_CLKOUT4_CASCADE + false + + + MMCM_CLOCK_HOLD + false + + + MMCM_COMPENSATION + ZHOLD + + + MMCM_REF_JITTER1 + 0.010 + + + MMCM_REF_JITTER2 + 0.010 + + + MMCM_STARTUP_WAIT + false + + + MMCM_CLKOUT0_DIVIDE_F + 10.000 + + + MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT0_PHASE + 0.000 + + + MMCM_CLKOUT0_USE_FINE_PS + false + + + MMCM_CLKOUT1_DIVIDE + 1 + + + MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT1_PHASE + 0.000 + + + MMCM_CLKOUT1_USE_FINE_PS + false + + + MMCM_CLKOUT2_DIVIDE + 1 + + + MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT2_PHASE + 0.000 + + + MMCM_CLKOUT2_USE_FINE_PS + false + + + MMCM_CLKOUT3_DIVIDE + 1 + + + MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT3_PHASE + 0.000 + + + MMCM_CLKOUT3_USE_FINE_PS + false + + + MMCM_CLKOUT4_DIVIDE + 1 + + + MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT4_PHASE + 0.000 + + + MMCM_CLKOUT4_USE_FINE_PS + false + + + MMCM_CLKOUT5_DIVIDE + 1 + + + MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT5_PHASE + 0.000 + + + MMCM_CLKOUT5_USE_FINE_PS + false + + + MMCM_CLKOUT6_DIVIDE + 1 + + + MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT6_PHASE + 0.000 + + + MMCM_CLKOUT6_USE_FINE_PS + false + + + OVERRIDE_PLL + false + + + PLL_NOTES + None + + + PLL_BANDWIDTH + OPTIMIZED + + + PLL_CLKFBOUT_MULT + 4 + + + PLL_CLKFBOUT_PHASE + 0.000 + + + PLL_CLK_FEEDBACK + CLKFBOUT + + + PLL_DIVCLK_DIVIDE + 1 + + + PLL_CLKIN_PERIOD + 10.000 + + + PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + PLL_REF_JITTER + 0.010 + + + PLL_CLKOUT0_DIVIDE + 1 + + + PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT0_PHASE + 0.000 + + + PLL_CLKOUT1_DIVIDE + 1 + + + PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT1_PHASE + 0.000 + + + PLL_CLKOUT2_DIVIDE + 1 + + + PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT2_PHASE + 0.000 + + + PLL_CLKOUT3_DIVIDE + 1 + + + PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT3_PHASE + 0.000 + + + PLL_CLKOUT4_DIVIDE + 1 + + + PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT4_PHASE + 0.000 + + + PLL_CLKOUT5_DIVIDE + 1 + + + PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT5_PHASE + 0.000 + + + RESET_TYPE + Reset Type + ACTIVE_HIGH + + + USE_SAFE_CLOCK_STARTUP + false + + + USE_CLOCK_SEQUENCING + false + + + CLKOUT1_SEQUENCE_NUMBER + 1 + + + CLKOUT2_SEQUENCE_NUMBER + 1 + + + CLKOUT3_SEQUENCE_NUMBER + 1 + + + CLKOUT4_SEQUENCE_NUMBER + 1 + + + CLKOUT5_SEQUENCE_NUMBER + 1 + + + CLKOUT6_SEQUENCE_NUMBER + 1 + + + CLKOUT7_SEQUENCE_NUMBER + 1 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_IN1_BOARD_INTERFACE + Custom + + + CLK_IN2_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN1_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN2_BOARD_INTERFACE + Custom + + + AUTO_PRIMITIVE + MMCM + + + RESET_BOARD_INTERFACE + Custom + + + ENABLE_CDDC + false + + + CDDCDONE_PORT + cddcdone + + + CDDCREQ_PORT + cddcreq + + + ENABLE_CLKOUTPHY + false + + + CLKOUTPHY_REQUESTED_FREQ + 600.000 + + + CLKOUT1_JITTER + Clkout1 Jitter + 130.958 + + + CLKOUT1_PHASE_ERROR + Clkout1 Phase + 98.575 + + + CLKOUT2_JITTER + Clkout2 Jitter + 0.0 + + + CLKOUT2_PHASE_ERROR + Clkout2 Phase + 0.0 + + + CLKOUT3_JITTER + Clkout3 Jitter + 0.0 + + + CLKOUT3_PHASE_ERROR + Clkout3 Phase + 0.0 + + + CLKOUT4_JITTER + Clkout4 Jitter + 0.0 + + + CLKOUT4_PHASE_ERROR + Clkout4 Phase + 0.0 + + + CLKOUT5_JITTER + Clkout5 Jitter + 0.0 + + + CLKOUT5_PHASE_ERROR + Clkout5 Phase + 0.0 + + + CLKOUT6_JITTER + Clkout6 Jitter + 0.0 + + + CLKOUT6_PHASE_ERROR + Clkout6 Phase + 0.0 + + + CLKOUT7_JITTER + Clkout7 Jitter + 0.0 + + + CLKOUT7_PHASE_ERROR + Clkout7 Phase + 0.0 + + + INPUT_MODE + frequency + + + INTERFACE_SELECTION + Enable_AXI + + + AXI_DRP + Write DRP registers + false + + + PHASE_DUTY_CONFIG + Phase Duty Cycle Config + false + + + + + Clocking Wizard + + XPM_CDC + + 1 + + + + + + + 2018.2 + + + + + + + + diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc new file mode 100644 index 0000000..3422a8e --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc @@ -0,0 +1,2 @@ +#--------------------Physical Constraints----------------- + diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v new file mode 100644 index 0000000..3ba7ae3 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v @@ -0,0 +1,203 @@ + +// file: clk_wiz_0.v +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1___100.000______0.000______50.0______130.958_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +`timescale 1ps/1ps + +module clk_wiz_0_clk_wiz + + (// Clock in ports + // Clock out ports + output clk_out1, + // Status and control signals + output locked, + input clk_in1_p, + input clk_in1_n + ); + // Input buffering + //------------------------------------ +wire clk_in1_clk_wiz_0; +wire clk_in2_clk_wiz_0; + IBUFDS clkin1_ibufgds + (.O (clk_in1_clk_wiz_0), + .I (clk_in1_p), + .IB (clk_in1_n)); + + + + + // Clocking PRIMITIVE + //------------------------------------ + + // Instantiation of the MMCM PRIMITIVE + // * Unused inputs are tied off + // * Unused outputs are labeled unused + + wire clk_out1_clk_wiz_0; + wire clk_out2_clk_wiz_0; + wire clk_out3_clk_wiz_0; + wire clk_out4_clk_wiz_0; + wire clk_out5_clk_wiz_0; + wire clk_out6_clk_wiz_0; + wire clk_out7_clk_wiz_0; + + wire [15:0] do_unused; + wire drdy_unused; + wire psdone_unused; + wire locked_int; + wire clkfbout_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfboutb_unused; + wire clkout0b_unused; + wire clkout1_unused; + wire clkout1b_unused; + wire clkout2_unused; + wire clkout2b_unused; + wire clkout3_unused; + wire clkout3b_unused; + wire clkout4_unused; + wire clkout5_unused; + wire clkout6_unused; + wire clkfbstopped_unused; + wire clkinstopped_unused; + + MMCME2_ADV + #(.BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (10.000), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (10.000), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (10.000)) + mmcm_adv_inst + // Output clocks + ( + .CLKFBOUT (clkfbout_clk_wiz_0), + .CLKFBOUTB (clkfboutb_unused), + .CLKOUT0 (clk_out1_clk_wiz_0), + .CLKOUT0B (clkout0b_unused), + .CLKOUT1 (clkout1_unused), + .CLKOUT1B (clkout1b_unused), + .CLKOUT2 (clkout2_unused), + .CLKOUT2B (clkout2b_unused), + .CLKOUT3 (clkout3_unused), + .CLKOUT3B (clkout3b_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + .CLKOUT6 (clkout6_unused), + // Input clock control + .CLKFBIN (clkfbout_buf_clk_wiz_0), + .CLKIN1 (clk_in1_clk_wiz_0), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (do_unused), + .DRDY (drdy_unused), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (psdone_unused), + // Other control and status signals + .LOCKED (locked_int), + .CLKINSTOPPED (clkinstopped_unused), + .CLKFBSTOPPED (clkfbstopped_unused), + .PWRDWN (1'b0), + .RST (1'b0)); + + assign locked = locked_int; +// Clock Monitor clock assigning +//-------------------------------------- + // Output buffering + //----------------------------------- + + BUFG clkf_buf + (.O (clkfbout_buf_clk_wiz_0), + .I (clkfbout_clk_wiz_0)); + + + + + + + BUFG clkout1_buf + (.O (clk_out1), + .I (clk_out1_clk_wiz_0)); + + + + +endmodule diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc new file mode 100644 index 0000000..cc4492a --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc @@ -0,0 +1,59 @@ + +# file: clk_wiz_0_ooc.xdc +# +# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +################# +#DEFAULT CLOCK CONSTRAINTS + +############################################################ +# Clock Period Constraints # +############################################################ +# Differential clock only needs one constraint +#create_clock -period 10.000 [get_ports clk_in1_p] + diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v new file mode 100644 index 0000000..21283aa --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v @@ -0,0 +1,246 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 12:07:42 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim +// d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +// Design : clk_wiz_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module clk_wiz_0 + (clk_out1, + locked, + clk_in1_p, + clk_in1_n); + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; + + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_n; + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) wire clk_in1_p; + wire clk_out1; + wire locked; + + clk_wiz_0_clk_wiz_0_clk_wiz inst + (.clk_in1_n(clk_in1_n), + .clk_in1_p(clk_in1_p), + .clk_out1(clk_out1), + .locked(locked)); +endmodule + +(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *) +module clk_wiz_0_clk_wiz_0_clk_wiz + (clk_out1, + locked, + clk_in1_p, + clk_in1_n); + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; + + wire clk_in1_clk_wiz_0; + wire clk_in1_n; + wire clk_in1_p; + wire clk_out1; + wire clk_out1_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfbout_clk_wiz_0; + wire locked; + wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; + wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; + wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; + wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_clk_wiz_0), + .O(clkfbout_buf_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUFDS #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufgds + (.I(clk_in1_p), + .IB(clk_in1_n), + .O(clk_in1_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(clk_out1_clk_wiz_0), + .O(clk_out1)); + (* BOX_TYPE = "PRIMITIVE" *) + MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(10.000000), + .CLKFBOUT_PHASE(0.000000), + .CLKFBOUT_USE_FINE_PS("FALSE"), + .CLKIN1_PERIOD(10.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE_F(10.000000), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT0_USE_FINE_PS("FALSE"), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT1_USE_FINE_PS("FALSE"), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT2_USE_FINE_PS("FALSE"), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT3_USE_FINE_PS("FALSE"), + .CLKOUT4_CASCADE("FALSE"), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT4_USE_FINE_PS("FALSE"), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .CLKOUT5_USE_FINE_PS("FALSE"), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.500000), + .CLKOUT6_PHASE(0.000000), + .CLKOUT6_USE_FINE_PS("FALSE"), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(1), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PSEN_INVERTED(1'b0), + .IS_PSINCDEC_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .SS_EN("FALSE"), + .SS_MODE("CENTER_HIGH"), + .SS_MOD_PERIOD(10000), + .STARTUP_WAIT("FALSE")) + mmcm_adv_inst + (.CLKFBIN(clkfbout_buf_clk_wiz_0), + .CLKFBOUT(clkfbout_clk_wiz_0), + .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), + .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), + .CLKIN1(clk_in1_clk_wiz_0), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), + .CLKOUT0(clk_out1_clk_wiz_0), + .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), + .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), + .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), + .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), + .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), + .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(locked), + .PSCLK(1'b0), + .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(1'b0), + .RST(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl new file mode 100644 index 0000000..b095c24 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl @@ -0,0 +1,191 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 12:07:42 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim +-- d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +-- Design : clk_wiz_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_wiz_0_clk_wiz_0_clk_wiz is + port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz"; +end clk_wiz_0_clk_wiz_0_clk_wiz; + +architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is + signal clk_in1_clk_wiz_0 : STD_LOGIC; + signal clk_out1_clk_wiz_0 : STD_LOGIC; + signal clkfbout_buf_clk_wiz_0 : STD_LOGIC; + signal clkfbout_clk_wiz_0 : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkin1_ibufgds : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of clkin1_ibufgds : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of clkin1_ibufgds : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of clkin1_ibufgds : label is "AUTO"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_clk_wiz_0, + O => clkfbout_buf_clk_wiz_0 + ); +clkin1_ibufgds: unisim.vcomponents.IBUFDS + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => clk_in1_p, + IB => clk_in1_n, + O => clk_in1_clk_wiz_0 + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => clk_out1_clk_wiz_0, + O => clk_out1 + ); +mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 10.000000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 10.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 10.000000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_DIVIDE => 1, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => clkfbout_buf_clk_wiz_0, + CLKFBOUT => clkfbout_clk_wiz_0, + CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, + CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, + CLKIN1 => clk_in1_clk_wiz_0, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, + CLKOUT0 => clk_out1_clk_wiz_0, + CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, + CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, + CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, + CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, + CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, + CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, + CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => locked, + PSCLK => '0', + PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_wiz_0 is + port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of clk_wiz_0 : entity is true; +end clk_wiz_0; + +architecture STRUCTURE of clk_wiz_0 is +begin +inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz + port map ( + clk_in1_n => clk_in1_n, + clk_in1_p => clk_in1_p, + clk_out1 => clk_out1, + locked => locked + ); +end STRUCTURE; diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100644 index 0000000..087991a --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Sun Jun 28 12:07:42 2020 +// Host : PC2018 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub +// d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7k160tffg676-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module clk_wiz_0(clk_out1, locked, clk_in1_p, clk_in1_n) +/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1_p,clk_in1_n" */; + output clk_out1; + output locked; + input clk_in1_p; + input clk_in1_n; +endmodule diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..02da164 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +-- Date : Sun Jun 28 12:07:42 2020 +-- Host : PC2018 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub +-- d:/Xilinx/xjtag/xjtag_ip/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k160tffg676-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + clk_out1 : out STD_LOGIC; + locked : out STD_LOGIC; + clk_in1_p : in STD_LOGIC; + clk_in1_n : in STD_LOGIC + ); + +end clk_wiz_0; + +architecture stub of clk_wiz_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1_p,clk_in1_n"; +begin +end; diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt new file mode 100644 index 0000000..2ce117e --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt @@ -0,0 +1,180 @@ +2018.2: + * Version 6.0 (Rev. 1) + * Bug Fix: Removed vco freq check when Primitive is None + * Other: New family support added + +2018.1: + * Version 6.0 + * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature + * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI + * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals. + * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support + * Other: DRCs added for invalid input values in Override mode + +2017.4: + * Version 5.4 (Rev. 3) + * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL + * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4 + +2017.3: + * Version 5.4 (Rev. 2) + * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices + +2017.2: + * Version 5.4 (Rev. 1) + * General: Internal GUI changes. No effect on the customer design. + +2017.1: + * Version 5.4 + * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices. + * Other: Added support for new zynq ultrascale plus devices. + +2016.4: + * Version 5.3 (Rev. 3) + * Bug Fix: Internal GUI issues are fixed. + +2016.3: + * Version 5.3 (Rev. 2) + * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs. + * Feature Enhancement: Added Matched Routing Option for better timing solutions. + * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list. + * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user + * Other: Added support for Spartan7 devices. + +2016.2: + * Version 5.3 (Rev. 1) + * Internal register bit update, no effect on customer designs. + +2016.1: + * Version 5.3 + * Added Clock Monitor Feature as part of clocking wizard + * DRP registers can be directly written through AXI without resource utilization + * Changes to HDL library management to support Vivado IP simulation library + +2015.4.2: + * Version 5.2 (Rev. 1) + * No changes + +2015.4.1: + * Version 5.2 (Rev. 1) + * No changes + +2015.4: + * Version 5.2 (Rev. 1) + * Internal device family change, no functional changes + +2015.3: + * Version 5.2 + * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances + * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported + * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature + * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format + * Example design and simulation files are delivered in verilog only + +2015.2.1: + * Version 5.1 (Rev. 6) + * No changes + +2015.2: + * Version 5.1 (Rev. 6) + * No changes + +2015.1: + * Version 5.1 (Rev. 6) + * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices + * Supported devices and production status are now determined automatically, to simplify support for future devices + +2014.4.1: + * Version 5.1 (Rev. 5) + * No changes + +2014.4: + * Version 5.1 (Rev. 5) + * Internal device family change, no functional changes + * updates related to the source selection based on board interface for zed board + +2014.3: + * Version 5.1 (Rev. 4) + * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface + +2014.2: + * Version 5.1 (Rev. 3) + * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 + +2014.1: + * Version 5.1 (Rev. 2) + * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock + * Internal device family name change, no functional changes + +2013.4: + * Version 5.1 (Rev. 1) + * Added support for Ultrascale devices + * Updated Board Flow GUI to select the clock interfaces + * Fixed issue with Stub file parameter error for BUFR output driver + +2013.3: + * Version 5.1 + * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL + * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies + * Fixed precision issues between displayed and actual frequencies + * Added tool tips to GUI + * Added Jitter and Phase error values to IP properties + * Added support for Cadence IES and Synopsys VCS simulators + * Reduced warnings in synthesis and simulation + * Enhanced support for IP Integrator + +2013.2: + * Version 5.0 (Rev. 1) + * Fixed issue with clock constraints for multiple instances of clocking wizard + * Updated Life-Cycle status of devices + +2013.1: + * Version 5.0 + * Lower case ports for Verilog + * Added Safe Clock Startup and Clock Sequencing + +(c) Copyright 2008 - 2018 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh new file mode 100644 index 0000000..b233fde --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh @@ -0,0 +1,665 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: 7 Series || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1011_00, + 10'b0010_1101_00, + 10'b0010_0011_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0100_1111_00, + 10'b0101_1011_00, + 10'b0111_0111_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_1001_00, + 10'b1101_0001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0111_0001_00, + 10'b0111_0001_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0110_0001_00, + 10'b0110_0001_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0100_1010_00, + 10'b0011_1100_00, + 10'b0011_1100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh new file mode 100644 index 0000000..53ab5ad --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh @@ -0,0 +1,527 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: PLLE2 DRP +// Module Name: plle2_drp_func.h +// Version: 2.00 +// Target Devices: 7 Series || PLL +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// Updated for CR663854. +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + +`ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); +`endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end +`ifdef DEBUG + $display("round_frac: %h", round_frac); +`endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + +`ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); +`endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + +`ifdef DEBUG + $display("temp: %h", temp); +`endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1101_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0011_0111_00, + 10'b0011_0111_00, + 10'b0101_1111_00, + 10'b0111_1111_00, + 10'b0111_1011_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_1101_00, + 10'b1111_0111_00, + 10'b1111_1011_00, + 10'b1111_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); +`endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh new file mode 100644 index 0000000..99b88ca --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh @@ -0,0 +1,665 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: UltraScale Architecture || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_0011_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_1001_11, + 10'b0010_1001_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1011_11, + 10'b0011_1111_11, + 10'b0100_1111_11, + 10'b0100_1111_11, + 10'b0101_1111_11, + 10'b0110_1111_11, + 10'b0111_1111_11, + 10'b0111_1111_11, + 10'b1100_1111_11, + 10'b1101_1111_11, + 10'b1110_1111_11, + 10'b1111_1111_11, + 10'b1111_1111_11, + 10'b1110_0111_11, + 10'b1110_1011_11, + 10'b1111_0111_11, + 10'b1111_1011_11, + 10'b1111_1011_11, + 10'b1110_1101_11, + 10'b1111_1101_11, + 10'b1111_1101_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh new file mode 100644 index 0000000..d12a6f7 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh @@ -0,0 +1,524 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 6/15/2015 +// Design Name: PLLE3 DRP +// Module Name: plle3_drp_func.h +// Version: 1.10 +// Target Devices: UltraScale Architecture +// Tool versions: 2015.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// PM_Rise bits have been removed for PLLE3 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [759:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001 //19 + + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 19 + ); + + reg [639:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0010_1111_01, //1 + 10'b0010_0011_11, //2 + 10'b0011_0011_11, //3 + 10'b0010_0001_11, //4 + 10'b0010_0110_11, //5 + 10'b0010_1010_11, //6 + 10'b0010_1010_11, //7 + 10'b0011_0110_11, //8 + 10'b0010_1100_11, //9 + 10'b0010_1100_11, //10 + 10'b0010_1100_11, //11 + 10'b0010_0010_11, //12 + 10'b0011_1100_11, //13 + 10'b0011_1100_11, //14 + 10'b0011_1100_11, //15 + 10'b0011_1100_11, //16 + 10'b0011_0010_11, //17 + 10'b0011_0010_11, //18 + 10'b0011_0010_11 //19 + }; + + mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits +// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + + diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh new file mode 100644 index 0000000..60b4560 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh @@ -0,0 +1,855 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa. Updated by Ralf Krueger +// Date: 7/30/2014 +// Design Name: MMCME4 DRP +// Module Name: mmcme4_drp_func.h +// Version: 1.31 +// Target Devices: UltraScale Plus Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for UltraScal+ MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function +// 2/28/17 - Updated for Ultrascale Plus +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages during elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_phase-divide:%d,phase:%d", divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [7:0] divide // Max M divide is 128 in UltrascalePlus + ); + + reg [5119:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) + 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 + 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 + 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 + 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 + 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 + 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 + 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup_low; + reg [1279:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0011_1111_11, // M=1 - not legal + 10'b0011_1111_11, // M=2 + 10'b0011_1101_11, // M=3 + 10'b0011_0101_11, // M=4 + 10'b0011_1001_11, // M=5 + 10'b0011_1110_11, // M=6 + 10'b0011_1110_11, // M=7 + 10'b0011_0001_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0100_0110_11, + 10'b0011_1100_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, // M=127 + 10'b1101_1000_11 // M=128 +}; + + lookup_high = { + // CP_RES_LFHF + 10'b0111_1111_11, // M=1 - not legal + 10'b0111_1111_11, // M=2 + 10'b1110_1111_11, // M=3 + 10'b1111_1111_11, // M=4 + 10'b1111_1011_11, // M=5 + 10'b1111_1101_11, // M=6 + 10'b1111_0011_11, // M=7 + 10'b1110_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1110_0110_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11 // M=128 +}; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh new file mode 100644 index 0000000..9bfa6c8 --- /dev/null +++ b/localbus_demo/prj/localbus_demo.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh @@ -0,0 +1,530 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ +// Date: 6/15/2015 +// Design Name: PLLE4 DRP +// Module Name: plle4_drp_func.h +// Version: 2.0 +// Target Devices: UltraScale+ Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// M_Rise bits have been removed for PLLE3 +// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for +// Ultrascale+ and for max M of 21 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [839:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+ + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001, //19 + 40'b11111_11111_0111110100_1111101001_0000000001, //20 + 40'b11111_11111_0111011011_1111101001_0000000001 //21 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [209:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0011_0111_11, //1 not legal in Ultrascale+ + 10'b0011_0111_11, //2 + 10'b0011_0011_11, //3 + 10'b0011_1001_11, //4 + 10'b0011_0001_11, //5 + 10'b0100_1110_11, //6 + 10'b0011_0110_11, //7 + 10'b0011_1010_11, //8 + 10'b0111_1001_11, //9 + 10'b0111_1001_11, //10 + 10'b0101_0110_11, //11 + 10'b1100_0101_11, //12 + 10'b0101_1010_11, //13 + 10'b0110_0110_11, //14 + 10'b0110_1010_11, //15 + 10'b0111_0110_11, //16 + 10'b1111_0101_11, //17 + 10'b1100_0110_11, //18 + 10'b1110_0001_11, //19 + 10'b1101_0110_11, //20 + 10'b1111_0001_11 //21 + }; + + mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" +// will need to divide the doubled clock VCO clock frequency by +// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will +// need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/localbus_demo/prj/localbus_demo.xpr b/localbus_demo/prj/localbus_demo.xpr new file mode 100644 index 0000000..bf73e0a --- /dev/null +++ b/localbus_demo/prj/localbus_demo.xpr @@ -0,0 +1,201 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/localbus_demo/src/localbus_register.v b/localbus_demo/src/localbus_register.v new file mode 100644 index 0000000..da28834 --- /dev/null +++ b/localbus_demo/src/localbus_register.v @@ -0,0 +1,79 @@ +module localbus_register +( +clk, +rst, + +localbus_waddr, +localbus_wdata, +localbus_wmask, +localbus_raddr, +localbus_rdata, +localbus_wvalid, +localbus_rvalid, +localbus_re, +localbus_finish, + +gpio0, +gpio1 +); + +input clk; +input rst; + +input [31:0] localbus_waddr; +input [31:0] localbus_wdata; +input [3:0] localbus_wmask; +input [31:0] localbus_raddr; +output reg [31:0] localbus_rdata; +input localbus_wvalid; +input localbus_rvalid; +output [1:0] localbus_re; +output localbus_finish; +output reg [31:0] gpio0; +input wire [31:0] gpio1; + +reg [31:0] ram0; +reg [31:0] ram1; + +assign localbus_re =2'b10; + +always @(posedge clk or posedge rst) begin + if(rst) begin + gpio0 <=32'd0; + //gpio1 <=32'd0; + ram0 <=32'd0; + ram1 <=32'd0; + end + else begin + if(localbus_wvalid==1'b1) begin + case (localbus_waddr) + 32'd1 : gpio0 <=localbus_wdata; + //32'd2 : gpio1 <=localbus_wdata; + 32'd3 : ram0 <=localbus_wdata; + 32'd4 : ram1 <=localbus_wdata; + endcase + end + end +end + +parameter ver =32'h20200614; + +always @(posedge clk or posedge rst) begin + if(rst) begin + localbus_rdata <=32'd0; + end + else begin + if(localbus_rvalid==1'b1) begin + case (localbus_raddr) + 32'd0 : localbus_rdata <=ver ; + 32'd1 : localbus_rdata <=gpio0 ; + 32'd2 : localbus_rdata <=gpio1 ; + 32'd3 : localbus_rdata <=ram0 ; + 32'd4 : localbus_rdata <=ram1 ; + default : localbus_rdata <=32'd0; + endcase + end + end +end + +endmodule diff --git a/localbus_demo/src/t160_top.v b/localbus_demo/src/t160_top.v new file mode 100644 index 0000000..c04c3ff --- /dev/null +++ b/localbus_demo/src/t160_top.v @@ -0,0 +1,79 @@ +module t160_top +( + +input sys_clkp, +input sys_clkn, + +output [3:0] led + +); + + +wire locked; +wire iclk; //100-200MHz +wire rst; +wire [31:0] Test_data; + +assign led =Test_data[3:0]; + + +clk_wiz_0 clk_uut +( +.clk_out1(iclk), +.locked(locked), +.clk_in1_p(sys_clkp), // input clk_in1_p +.clk_in1_n(sys_clkn)); // input clk_in1_n + +BUFG BUFG_inst ( + .O(rst), // 1-bit output: Clock output + .I(!locked) // 1-bit input: Clock input +); + +wire [31:0] localbus_waddr; +wire [31:0] localbus_wdata; +wire [3:0] localbus_wmask; +wire [31:0] localbus_raddr; +wire [31:0] localbus_rdata; +wire localbus_wvalid; +wire localbus_rvalid; + +xjtag_bus # +( +.JTAG_SEL (3) +) +xjtag_bus_uut +( +.clk (iclk), +.rst (rst), + +.localbus_waddr (localbus_waddr ), +.localbus_wdata (localbus_wdata ), +.localbus_wmask (localbus_wmask ), +.localbus_raddr (localbus_raddr ), +.localbus_rdata (localbus_rdata ), +.localbus_wvalid (localbus_wvalid ), +.localbus_rvalid (localbus_rvalid ) +); + + +localbus_register UUT +( +.clk (iclk), +.rst (rst), + +.localbus_waddr (localbus_waddr ), +.localbus_wdata (localbus_wdata ), +.localbus_wmask (localbus_wmask ), +.localbus_raddr (localbus_raddr ), +.localbus_rdata (localbus_rdata ), +.localbus_wvalid (localbus_wvalid), +.localbus_rvalid (localbus_rvalid), +.localbus_re ( ), +.localbus_finish ( ), + +.gpio0 (Test_data), +.gpio1 (32'h12345678) +); + + +endmodule \ No newline at end of file diff --git a/localbus_demo/src/t160_top.xdc b/localbus_demo/src/t160_top.xdc new file mode 100644 index 0000000..4769e37 --- /dev/null +++ b/localbus_demo/src/t160_top.xdc @@ -0,0 +1,16 @@ +set_property PACKAGE_PIN T20 [get_ports {led[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] + +set_property PACKAGE_PIN R20 [get_ports {led[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] + +set_property PACKAGE_PIN T22 [get_ports {led[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] + +set_property PACKAGE_PIN T23 [get_ports {led[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] + +set_property PACKAGE_PIN AA10 [get_ports sys_clkp] +set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clkp] + + diff --git a/localbus_ip/xjtag_bus.ngc b/localbus_ip/xjtag_bus.ngc new file mode 100644 index 0000000..8d86e9e --- /dev/null +++ b/localbus_ip/xjtag_bus.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/localbus_ip/xjtag_bus.v b/localbus_ip/xjtag_bus.v new file mode 100644 index 0000000..a870e01 --- /dev/null +++ b/localbus_ip/xjtag_bus.v @@ -0,0 +1,30 @@ +module xjtag_bus # +( +parameter JTAG_SEL =3 +) +( +clk, +rst, + +localbus_waddr, +localbus_wdata, +localbus_wmask, +localbus_raddr, +localbus_rdata, +localbus_wvalid, +localbus_rvalid +); + +input clk; +input rst; + +output [31:0] localbus_waddr; +output [31:0] localbus_wdata; +output [3:0] localbus_wmask; +output [31:0] localbus_raddr; +input [31:0] localbus_rdata; +output localbus_wvalid; +output localbus_rvalid; + + +endmodule diff --git a/readme.txt b/readme.txt new file mode 100644 index 0000000..d04a7a4 --- /dev/null +++ b/readme.txt @@ -0,0 +1,22 @@ +API库文件： + api_lib +FPGA工程目录： + axi_bus_demo（演示AXI总线） + localbus_demo（演示Localbus总线） +FPGA的IP文件： + axi_bus_ip （AXI总线IP） + localbus_ip（AXI总线IP） +上位机软件测试工程： + vs2010_axi_bus（演示AXI总线上位机程序） + vs2010_localbus（演示Localbus总线上位机程序） + +AXI总线可寻址范围：FPGA端起始地址0x40000000, +Localbus总线寻址范围：FPGA端起始地址0x00000000， +fpga工程为vivado2018.2 +（运行上位机程序时，请先退出xilinx烧录软件） + +注意：安装SDK时的路径不能有中文、空格。（先安装Xilinx\Vivado\2018.2\data\xicom\cable_drivers\nt64\digilent目录下的SMT2-NC驱动） + +dll如果调用失败，会有出错信息打印，打印输出文件名为：log.txt + +技术支持：qq：2791668178 diff --git a/vs2010_axi_bus/ReadMe.txt b/vs2010_axi_bus/ReadMe.txt new file mode 100644 index 0000000..614b30d --- /dev/null +++ b/vs2010_axi_bus/ReadMe.txt @@ -0,0 +1,36 @@ +锘======================================================================== + 鎺у埗鍙板簲鐢ㄧ▼搴忥細vs2010_axi_bus 椤圭洰姒傝堪 +======================================================================== + +搴旂敤绋嬪簭鍚戝宸蹭负鎮ㄥ垱寤轰簡姝 vs2010_axi_bus 搴旂敤绋嬪簭銆 + +鏈枃浠舵瑕佷粙缁嶇粍鎴 vs2010_axi_bus 搴旂敤绋嬪簭鐨勬瘡涓枃浠剁殑鍐呭銆 + + +vs2010_axi_bus.vcxproj + 杩欐槸浣跨敤搴旂敤绋嬪簭鍚戝鐢熸垚鐨 VC++ 椤圭洰鐨勪富椤圭洰鏂囦欢锛 + 鍏朵腑鍖呭惈鐢熸垚璇ユ枃浠剁殑 Visual C++ + 鐨勭増鏈俊鎭紝浠ュ強鏈夊叧浣跨敤搴旂敤绋嬪簭鍚戝閫夋嫨鐨勫钩鍙般侀厤缃拰椤圭洰鍔熻兘鐨勪俊鎭 + +vs2010_axi_bus.vcxproj.filters + 杩欐槸浣跨敤鈥滃簲鐢ㄧ▼搴忓悜瀵尖濈敓鎴愮殑 VC++ 椤圭洰绛涢夊櫒鏂囦欢銆 + 瀹冨寘鍚湁鍏抽」鐩枃浠朵笌绛涢夊櫒涔嬮棿鐨勫叧鑱斾俊鎭 鍦 IDE + 涓紝閫氳繃杩欑鍏宠仈锛屽湪鐗瑰畾鑺傜偣涓嬩互鍒嗙粍褰㈠紡鏄剧ず鍏锋湁鐩镐技鎵╁睍鍚嶇殑鏂囦欢銆 + 渚嬪锛屸.cpp鈥濇枃浠朵笌鈥滄簮鏂囦欢鈥濈瓫閫夊櫒鍏宠仈銆 + +vs2010_axi_bus.cpp + 杩欐槸涓诲簲鐢ㄧ▼搴忔簮鏂囦欢銆 + +///////////////////////////////////////////////////////////////////////////// +鍏朵粬鏍囧噯鏂囦欢锛 + +StdAfx.h锛孲tdAfx.cpp + 杩欎簺鏂囦欢鐢ㄤ簬鐢熸垚鍚嶄负 vs2010_axi_bus.pch 鐨勯缂栬瘧澶 (PCH) 鏂囦欢鍜 + 鍚嶄负 StdAfx.obj 鐨勯缂栬瘧绫诲瀷鏂囦欢銆 + +///////////////////////////////////////////////////////////////////////////// +鍏朵粬娉ㄩ噴锛 + +搴旂敤绋嬪簭鍚戝浣跨敤鈥淭ODO:鈥濇敞閲婃潵鎸囩ず搴旀坊鍔犳垨鑷畾涔夌殑婧愪唬鐮侀儴鍒嗐 + +///////////////////////////////////////////////////////////////////////////// diff --git a/vs2010_axi_bus/ipch/vs2010_axi_bus-85890a65/vs2010_axi_bus-beb91680.ipch b/vs2010_axi_bus/ipch/vs2010_axi_bus-85890a65/vs2010_axi_bus-beb91680.ipch new file mode 100644 index 0000000..db583eb Binary files /dev/null and b/vs2010_axi_bus/ipch/vs2010_axi_bus-85890a65/vs2010_axi_bus-beb91680.ipch differ diff --git a/vs2010_axi_bus/ipch/vs2010_axi_bus-85890a65/vs2010_axi_bus-fe444242.ipch b/vs2010_axi_bus/ipch/vs2010_axi_bus-85890a65/vs2010_axi_bus-fe444242.ipch new file mode 100644 index 0000000..5e87f70 Binary files /dev/null and b/vs2010_axi_bus/ipch/vs2010_axi_bus-85890a65/vs2010_axi_bus-fe444242.ipch differ diff --git a/vs2010_axi_bus/stdafx.cpp b/vs2010_axi_bus/stdafx.cpp new file mode 100644 index 0000000..f8d0dc8 --- /dev/null +++ b/vs2010_axi_bus/stdafx.cpp @@ -0,0 +1,8 @@ +// stdafx.cpp : 只包括标准包含文件的源文件 +// vs2010_axi_bus.pch 将作为预编译头 +// stdafx.obj 将包含预编译类型信息 + +#include "stdafx.h" + +// TODO: 在 STDAFX.H 中 +// 引用任何所需的附加头文件，而不是在此文件中引用 diff --git a/vs2010_axi_bus/stdafx.h b/vs2010_axi_bus/stdafx.h new file mode 100644 index 0000000..9d41f0f --- /dev/null +++ b/vs2010_axi_bus/stdafx.h @@ -0,0 +1,15 @@ +// stdafx.h : 标准系统包含文件的包含文件， +// 或是经常使用但不常更改的 +// 特定于项目的包含文件 +// + +#pragma once + +#include "targetver.h" + +#include +#include + + + +// TODO: 在此处引用程序需要的其他头文件 diff --git a/vs2010_axi_bus/targetver.h b/vs2010_axi_bus/targetver.h new file mode 100644 index 0000000..7a7d2c8 --- /dev/null +++ b/vs2010_axi_bus/targetver.h @@ -0,0 +1,8 @@ +#pragma once + +// 包括 SDKDDKVer.h 将定义可用的最高版本的 Windows 平台。 + +// 如果要为以前的 Windows 平台生成应用程序，请包括 WinSDKVer.h，并将 +// WIN32_WINNT 宏设置为要支持的平台，然后再包括 SDKDDKVer.h。 + +#include diff --git a/vs2010_axi_bus/vs2010_axi_bus.cpp b/vs2010_axi_bus/vs2010_axi_bus.cpp new file mode 100644 index 0000000..bb24f53 --- /dev/null +++ b/vs2010_axi_bus/vs2010_axi_bus.cpp @@ -0,0 +1,51 @@ +// vs2010_axi_bus.cpp : 定义控制台应用程序的入口点。 +// + +#include "stdafx.h" +#include "xjtag.h" +#include "windows.h" + +unsigned long hif; +DWORD frqReq =250000; //10MHz + +#define LED_ON 0xFFFFFFFF +#define LED_OFF 0x00000000 + + +int _tmain(int argc, _TCHAR* argv[]) +{ + int re =0; + + int err =0; + + unsigned int rdata =0; + + char sel =0; + + re =xbus_axi_open(&hif,0,&sel,&err); + + re =xbus_init(hif,frqReq,0,2,&err); + + while(1) + { + Sleep(500); + + re =xbus_axi_write(hif,0x00000000,LED_ON,0x00); + + Sleep(500); + + re =xbus_axi_write(hif,0x00000000,LED_OFF,0x00); //write GPIO OUT REG + + printf("re =%d\n",re); + + re =xbus_axi_read(hif, 0x00000000,&rdata); + + printf("re =%d rdata=%08x\n",re,rdata); + + } + + return 0; +} + + + diff --git a/vs2010_axi_bus/vs2010_axi_bus.sdf b/vs2010_axi_bus/vs2010_axi_bus.sdf new file mode 100644 index 0000000..a452632 Binary files /dev/null and b/vs2010_axi_bus/vs2010_axi_bus.sdf differ diff --git a/vs2010_axi_bus/vs2010_axi_bus.sln b/vs2010_axi_bus/vs2010_axi_bus.sln new file mode 100644 index 0000000..0977eb6 --- /dev/null +++ b/vs2010_axi_bus/vs2010_axi_bus.sln @@ -0,0 +1,26 @@ +锘 +Microsoft Visual Studio Solution File, Format Version 11.00 +# Visual Studio 2010 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "vs2010_axi_bus", "vs2010_axi_bus.vcxproj", "{40428B15-0FA8-4508-9B16-AFAD7A0A8610}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Debug|x64 = Debug|x64 + Release|Win32 = Release|Win32 + Release|x64 = Release|x64 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Debug|Win32.ActiveCfg = Debug|Win32 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Debug|Win32.Build.0 = Debug|Win32 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Debug|x64.ActiveCfg = Debug|x64 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Debug|x64.Build.0 = Debug|x64 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Release|Win32.ActiveCfg = Release|Win32 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Release|Win32.Build.0 = Release|Win32 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Release|x64.ActiveCfg = Release|x64 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Release|x64.Build.0 = Release|x64 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/vs2010_axi_bus/vs2010_axi_bus.suo b/vs2010_axi_bus/vs2010_axi_bus.suo new file mode 100644 index 0000000..0d16652 Binary files /dev/null and b/vs2010_axi_bus/vs2010_axi_bus.suo differ diff --git a/vs2010_axi_bus/vs2010_axi_bus.vcxproj b/vs2010_axi_bus/vs2010_axi_bus.vcxproj new file mode 100644 index 0000000..4265861 --- /dev/null +++ b/vs2010_axi_bus/vs2010_axi_bus.vcxproj @@ -0,0 +1,164 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + {40428B15-0FA8-4508-9B16-AFAD7A0A8610} + Win32Proj + vs2010_axi_bus + + + + Application + true + Unicode + + + Application + true + Unicode + + + Application + false + true + Unicode + + + Application + false + true + Unicode + + + + + + + + + + + + + + + + + + + false + + + false + + + false + + + false + + + + Use + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + ..\api_lib;%(AdditionalIncludeDirectories) + + + Console + true + ..\api_lib\win32;%(AdditionalLibraryDirectories) + xjtag.lib + + + + + Use + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + ..\api_lib;%(AdditionalIncludeDirectories) + + + Console + true + ..\api_lib\x64;%(AdditionalLibraryDirectories) + xjtag.lib + + + + + Level3 + Use + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + ..\api_lib;%(AdditionalIncludeDirectories) + + + Console + true + true + true + ..\api_lib\win32;%(AdditionalLibraryDirectories) + xjtag.lib + + + + + Level3 + Use + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + ..\api_lib;%(AdditionalIncludeDirectories) + + + Console + true + true + true + ..\api_lib\x64;%(AdditionalLibraryDirectories) + xjtag.lib + + + + + + + + + + + + Create + Create + Create + Create + + + + + + + \ No newline at end of file diff --git a/vs2010_axi_bus/vs2010_axi_bus.vcxproj.filters b/vs2010_axi_bus/vs2010_axi_bus.vcxproj.filters new file mode 100644 index 0000000..9547afb --- /dev/null +++ b/vs2010_axi_bus/vs2010_axi_bus.vcxproj.filters @@ -0,0 +1,36 @@ +锘 + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + + + + 澶存枃浠 + + + 澶存枃浠 + + + + + 婧愭枃浠 + + + 婧愭枃浠 + + + \ No newline at end of file diff --git a/vs2010_axi_bus/vs2010_axi_bus.vcxproj.user b/vs2010_axi_bus/vs2010_axi_bus.vcxproj.user new file mode 100644 index 0000000..1fc9c17 --- /dev/null +++ b/vs2010_axi_bus/vs2010_axi_bus.vcxproj.user @@ -0,0 +1,19 @@ +锘 + + + path=%path%;..\api_lib\win32 + WindowsLocalDebugger + + + path=%path%;..\api_lib\win32 + WindowsLocalDebugger + + + path=%path%;..\api_lib\x64 + WindowsLocalDebugger + + + path=%path%;..\api_lib\x64 + WindowsLocalDebugger + + \ No newline at end of file diff --git a/vs2010_localbus/Debug/CL.read.1.tlog b/vs2010_localbus/Debug/CL.read.1.tlog new file mode 100644 index 0000000..2590aeb Binary files /dev/null and b/vs2010_localbus/Debug/CL.read.1.tlog differ diff --git a/vs2010_localbus/Debug/CL.write.1.tlog b/vs2010_localbus/Debug/CL.write.1.tlog new file mode 100644 index 0000000..a635c28 Binary files /dev/null and b/vs2010_localbus/Debug/CL.write.1.tlog differ diff --git a/vs2010_localbus/Debug/cl.command.1.tlog b/vs2010_localbus/Debug/cl.command.1.tlog new file mode 100644 index 0000000..bca1488 Binary files /dev/null and b/vs2010_localbus/Debug/cl.command.1.tlog differ diff --git a/vs2010_localbus/Debug/link.command.1.tlog b/vs2010_localbus/Debug/link.command.1.tlog new file mode 100644 index 0000000..1112d59 Binary files /dev/null and b/vs2010_localbus/Debug/link.command.1.tlog differ diff --git a/vs2010_localbus/Debug/link.read.1.tlog b/vs2010_localbus/Debug/link.read.1.tlog new file mode 100644 index 0000000..f42db7f Binary files /dev/null and b/vs2010_localbus/Debug/link.read.1.tlog differ diff --git a/vs2010_localbus/Debug/link.write.1.tlog b/vs2010_localbus/Debug/link.write.1.tlog new file mode 100644 index 0000000..6d02c01 Binary files /dev/null and b/vs2010_localbus/Debug/link.write.1.tlog differ diff --git a/vs2010_localbus/Debug/mt.command.1.tlog b/vs2010_localbus/Debug/mt.command.1.tlog new file mode 100644 index 0000000..e8acc23 Binary files /dev/null and b/vs2010_localbus/Debug/mt.command.1.tlog differ diff --git a/vs2010_localbus/Debug/mt.read.1.tlog b/vs2010_localbus/Debug/mt.read.1.tlog new file mode 100644 index 0000000..c24d12f Binary files /dev/null and b/vs2010_localbus/Debug/mt.read.1.tlog differ diff --git a/vs2010_localbus/Debug/mt.write.1.tlog b/vs2010_localbus/Debug/mt.write.1.tlog new file mode 100644 index 0000000..68160b8 Binary files /dev/null and b/vs2010_localbus/Debug/mt.write.1.tlog differ diff --git a/vs2010_localbus/Debug/stdafx.obj b/vs2010_localbus/Debug/stdafx.obj new file mode 100644 index 0000000..a68985e Binary files /dev/null and b/vs2010_localbus/Debug/stdafx.obj differ diff --git a/vs2010_localbus/Debug/vc100.idb b/vs2010_localbus/Debug/vc100.idb new file mode 100644 index 0000000..3390806 Binary files /dev/null and b/vs2010_localbus/Debug/vc100.idb differ diff --git a/vs2010_localbus/Debug/vc100.pdb b/vs2010_localbus/Debug/vc100.pdb new file mode 100644 index 0000000..a0b7893 Binary files /dev/null and b/vs2010_localbus/Debug/vc100.pdb differ diff --git a/vs2010_localbus/Debug/vs2010_axi_bus.log b/vs2010_localbus/Debug/vs2010_axi_bus.log new file mode 100644 index 0000000..fc68c1e --- /dev/null +++ b/vs2010_localbus/Debug/vs2010_axi_bus.log @@ -0,0 +1,24 @@ +锘緽uild started 2021\4\18 鏄熸湡鏃 21:55:04. + 1>Project "G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\vs2010_axi_bus.vcxproj" on node 2 (rebuild target(s)). + 1>InitializeBuildStatus: + Creating "Debug\vs2010_localbus.unsuccessfulbuild" because "AlwaysCreate" was specified. + ClCompile: + D:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin\CL.exe /c /I..\api_lib /ZI /nologo /W3 /WX- /Od /Oy- /D WIN32 /D _DEBUG /D _CONSOLE /D _UNICODE /D UNICODE /Gm /EHsc /RTC1 /MDd /GS /fp:precise /Zc:wchar_t /Zc:forScope /Yc"StdAfx.h" /Fp"Debug\vs2010_localbus.pch" /Fo"Debug\\" /Fd"Debug\vc100.pdb" /Gd /TP /analyze- /errorReport:prompt stdafx.cpp + stdafx.cpp + D:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin\CL.exe /c /I..\api_lib /ZI /nologo /W3 /WX- /Od /Oy- /D WIN32 /D _DEBUG /D _CONSOLE /D _UNICODE /D UNICODE /Gm /EHsc /RTC1 /MDd /GS /fp:precise /Zc:wchar_t /Zc:forScope /Yu"StdAfx.h" /Fp"Debug\vs2010_localbus.pch" /Fo"Debug\\" /Fd"Debug\vc100.pdb" /Gd /TP /analyze- /errorReport:prompt vs2010_localbus.cpp + vs2010_localbus.cpp + Link: + D:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin\link.exe /ERRORREPORT:PROMPT /OUT:"G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\Debug\vs2010_localbus.exe" /INCREMENTAL:NO /NOLOGO /LIBPATH:..\api_lib\win32 xjtag.lib /MANIFEST /ManifestFile:"Debug\vs2010_localbus.exe.intermediate.manifest" /MANIFESTUAC:"level='asInvoker' uiAccess='false'" /DEBUG /PDB:"G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\Debug\vs2010_localbus.pdb" /SUBSYSTEM:CONSOLE /TLBID:1 /DYNAMICBASE /NXCOMPAT /IMPLIB:"G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\Debug\vs2010_localbus.lib" /MACHINE:X86 Debug\stdafx.obj + Debug\vs2010_localbus.obj + 1>stdafx.obj : warning LNK4075: ignoring '/EDITANDCONTINUE' due to '/INCREMENTAL:NO' specification + vs2010_axi_bus.vcxproj -> G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\Debug\vs2010_localbus.exe + Manifest: + C:\Program Files (x86)\Microsoft SDKs\Windows\v7.0A\bin\mt.exe /nologo /verbose /outputresource:"G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\Debug\vs2010_localbus.exe;#1" /manifest Debug\vs2010_localbus.exe.intermediate.manifest + FinalizeBuildStatus: + Deleting file "Debug\vs2010_localbus.unsuccessfulbuild". + Touching "Debug\vs2010_localbus.lastbuildstate". + 1>Done Building Project "G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\vs2010_axi_bus.vcxproj" (rebuild target(s)). + +Build succeeded. + +Time Elapsed 00:00:07.24 diff --git a/vs2010_localbus/Debug/vs2010_localbus.exe b/vs2010_localbus/Debug/vs2010_localbus.exe new file mode 100644 index 0000000..0e2a7a1 Binary files /dev/null and b/vs2010_localbus/Debug/vs2010_localbus.exe differ diff --git a/vs2010_localbus/Debug/vs2010_localbus.exe.intermediate.manifest b/vs2010_localbus/Debug/vs2010_localbus.exe.intermediate.manifest new file mode 100644 index 0000000..ecea6f7 --- /dev/null +++ b/vs2010_localbus/Debug/vs2010_localbus.exe.intermediate.manifest @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/vs2010_localbus/Debug/vs2010_localbus.lastbuildstate b/vs2010_localbus/Debug/vs2010_localbus.lastbuildstate new file mode 100644 index 0000000..2f5db22 --- /dev/null +++ b/vs2010_localbus/Debug/vs2010_localbus.lastbuildstate @@ -0,0 +1,2 @@ +#v4.0:v100 +Debug|Win32|G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\| diff --git a/vs2010_localbus/Debug/vs2010_localbus.obj b/vs2010_localbus/Debug/vs2010_localbus.obj new file mode 100644 index 0000000..012bb50 Binary files /dev/null and b/vs2010_localbus/Debug/vs2010_localbus.obj differ diff --git a/vs2010_localbus/Debug/vs2010_localbus.pch b/vs2010_localbus/Debug/vs2010_localbus.pch new file mode 100644 index 0000000..bd53a13 Binary files /dev/null and b/vs2010_localbus/Debug/vs2010_localbus.pch differ diff --git a/vs2010_localbus/Debug/vs2010_localbus.pdb b/vs2010_localbus/Debug/vs2010_localbus.pdb new file mode 100644 index 0000000..6bb5d94 Binary files /dev/null and b/vs2010_localbus/Debug/vs2010_localbus.pdb differ diff --git a/vs2010_localbus/Debug/vs2010_localbus.write.1.tlog b/vs2010_localbus/Debug/vs2010_localbus.write.1.tlog new file mode 100644 index 0000000..e69de29 diff --git a/vs2010_localbus/ReadMe.txt b/vs2010_localbus/ReadMe.txt new file mode 100644 index 0000000..614b30d --- /dev/null +++ b/vs2010_localbus/ReadMe.txt @@ -0,0 +1,36 @@ +锘======================================================================== + 鎺у埗鍙板簲鐢ㄧ▼搴忥細vs2010_axi_bus 椤圭洰姒傝堪 +======================================================================== + +搴旂敤绋嬪簭鍚戝宸蹭负鎮ㄥ垱寤轰簡姝 vs2010_axi_bus 搴旂敤绋嬪簭銆 + +鏈枃浠舵瑕佷粙缁嶇粍鎴 vs2010_axi_bus 搴旂敤绋嬪簭鐨勬瘡涓枃浠剁殑鍐呭銆 + + +vs2010_axi_bus.vcxproj + 杩欐槸浣跨敤搴旂敤绋嬪簭鍚戝鐢熸垚鐨 VC++ 椤圭洰鐨勪富椤圭洰鏂囦欢锛 + 鍏朵腑鍖呭惈鐢熸垚璇ユ枃浠剁殑 Visual C++ + 鐨勭増鏈俊鎭紝浠ュ強鏈夊叧浣跨敤搴旂敤绋嬪簭鍚戝閫夋嫨鐨勫钩鍙般侀厤缃拰椤圭洰鍔熻兘鐨勪俊鎭 + +vs2010_axi_bus.vcxproj.filters + 杩欐槸浣跨敤鈥滃簲鐢ㄧ▼搴忓悜瀵尖濈敓鎴愮殑 VC++ 椤圭洰绛涢夊櫒鏂囦欢銆 + 瀹冨寘鍚湁鍏抽」鐩枃浠朵笌绛涢夊櫒涔嬮棿鐨勫叧鑱斾俊鎭 鍦 IDE + 涓紝閫氳繃杩欑鍏宠仈锛屽湪鐗瑰畾鑺傜偣涓嬩互鍒嗙粍褰㈠紡鏄剧ず鍏锋湁鐩镐技鎵╁睍鍚嶇殑鏂囦欢銆 + 渚嬪锛屸.cpp鈥濇枃浠朵笌鈥滄簮鏂囦欢鈥濈瓫閫夊櫒鍏宠仈銆 + +vs2010_axi_bus.cpp + 杩欐槸涓诲簲鐢ㄧ▼搴忔簮鏂囦欢銆 + +///////////////////////////////////////////////////////////////////////////// +鍏朵粬鏍囧噯鏂囦欢锛 + +StdAfx.h锛孲tdAfx.cpp + 杩欎簺鏂囦欢鐢ㄤ簬鐢熸垚鍚嶄负 vs2010_axi_bus.pch 鐨勯缂栬瘧澶 (PCH) 鏂囦欢鍜 + 鍚嶄负 StdAfx.obj 鐨勯缂栬瘧绫诲瀷鏂囦欢銆 + +///////////////////////////////////////////////////////////////////////////// +鍏朵粬娉ㄩ噴锛 + +搴旂敤绋嬪簭鍚戝浣跨敤鈥淭ODO:鈥濇敞閲婃潵鎸囩ず搴旀坊鍔犳垨鑷畾涔夌殑婧愪唬鐮侀儴鍒嗐 + +///////////////////////////////////////////////////////////////////////////// diff --git a/vs2010_localbus/ipch/vs2010_axi_bus-461189e7/vs2010_localbus-5e2ec62a.ipch b/vs2010_localbus/ipch/vs2010_axi_bus-461189e7/vs2010_localbus-5e2ec62a.ipch new file mode 100644 index 0000000..03b39c2 Binary files /dev/null and b/vs2010_localbus/ipch/vs2010_axi_bus-461189e7/vs2010_localbus-5e2ec62a.ipch differ diff --git a/vs2010_localbus/ipch/vs2010_axi_bus-461189e7/vs2010_localbus-8f1f6a2c.ipch b/vs2010_localbus/ipch/vs2010_axi_bus-461189e7/vs2010_localbus-8f1f6a2c.ipch new file mode 100644 index 0000000..fc362df Binary files /dev/null and b/vs2010_localbus/ipch/vs2010_axi_bus-461189e7/vs2010_localbus-8f1f6a2c.ipch differ diff --git a/vs2010_localbus/log.txt b/vs2010_localbus/log.txt new file mode 100644 index 0000000..696218b --- /dev/null +++ b/vs2010_localbus/log.txt @@ -0,0 +1,4 @@ +load dll (-1) +加载dll失败 +load dll (-1) +加载dll失败 diff --git a/vs2010_localbus/stdafx.cpp b/vs2010_localbus/stdafx.cpp new file mode 100644 index 0000000..f8d0dc8 --- /dev/null +++ b/vs2010_localbus/stdafx.cpp @@ -0,0 +1,8 @@ +// stdafx.cpp : 只包括标准包含文件的源文件 +// vs2010_axi_bus.pch 将作为预编译头 +// stdafx.obj 将包含预编译类型信息 + +#include "stdafx.h" + +// TODO: 在 STDAFX.H 中 +// 引用任何所需的附加头文件，而不是在此文件中引用 diff --git a/vs2010_localbus/stdafx.h b/vs2010_localbus/stdafx.h new file mode 100644 index 0000000..9d41f0f --- /dev/null +++ b/vs2010_localbus/stdafx.h @@ -0,0 +1,15 @@ +// stdafx.h : 标准系统包含文件的包含文件， +// 或是经常使用但不常更改的 +// 特定于项目的包含文件 +// + +#pragma once + +#include "targetver.h" + +#include +#include + + + +// TODO: 在此处引用程序需要的其他头文件 diff --git a/vs2010_localbus/targetver.h b/vs2010_localbus/targetver.h new file mode 100644 index 0000000..7a7d2c8 --- /dev/null +++ b/vs2010_localbus/targetver.h @@ -0,0 +1,8 @@ +#pragma once + +// 包括 SDKDDKVer.h 将定义可用的最高版本的 Windows 平台。 + +// 如果要为以前的 Windows 平台生成应用程序，请包括 WinSDKVer.h，并将 +// WIN32_WINNT 宏设置为要支持的平台，然后再包括 SDKDDKVer.h。 + +#include diff --git a/vs2010_localbus/vs2010_axi_bus.vcxproj b/vs2010_localbus/vs2010_axi_bus.vcxproj new file mode 100644 index 0000000..aaff9bc --- /dev/null +++ b/vs2010_localbus/vs2010_axi_bus.vcxproj @@ -0,0 +1,165 @@ +锘 + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + {40428B15-0FA8-4508-9B16-AFAD7A0A8610} + Win32Proj + vs2010_axi_bus + vs2010_localbus + + + + Application + true + Unicode + + + Application + true + Unicode + + + Application + false + true + Unicode + + + Application + false + true + Unicode + + + + + + + + + + + + + + + + + + + false + + + false + + + false + + + false + + + + Use + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + ..\api_lib;%(AdditionalIncludeDirectories) + + + Console + true + ..\api_lib\win32;%(AdditionalLibraryDirectories) + xjtag.lib + + + + + Use + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + ..\api_lib;%(AdditionalIncludeDirectories) + + + Console + true + ..\api_lib\x64;%(AdditionalLibraryDirectories) + xjtag.lib + + + + + Level3 + Use + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + ..\api_lib;%(AdditionalIncludeDirectories) + + + Console + true + true + true + ..\api_lib\win32;%(AdditionalLibraryDirectories) + xjtag.lib + + + + + Level3 + Use + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + ..\api_lib;%(AdditionalIncludeDirectories) + + + Console + true + true + true + ..\api_lib\x64;%(AdditionalLibraryDirectories) + xjtag.lib + + + + + + + + + + + + Create + Create + Create + Create + + + + + + + \ No newline at end of file diff --git a/vs2010_localbus/vs2010_axi_bus.vcxproj.filters b/vs2010_localbus/vs2010_axi_bus.vcxproj.filters new file mode 100644 index 0000000..3deb752 --- /dev/null +++ b/vs2010_localbus/vs2010_axi_bus.vcxproj.filters @@ -0,0 +1,36 @@ +锘 + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + + + + 澶存枃浠 + + + 澶存枃浠 + + + + + 婧愭枃浠 + + + 婧愭枃浠 + + + \ No newline at end of file diff --git a/vs2010_localbus/vs2010_axi_bus.vcxproj.user b/vs2010_localbus/vs2010_axi_bus.vcxproj.user new file mode 100644 index 0000000..1fc9c17 --- /dev/null +++ b/vs2010_localbus/vs2010_axi_bus.vcxproj.user @@ -0,0 +1,19 @@ +锘 + + + path=%path%;..\api_lib\win32 + WindowsLocalDebugger + + + path=%path%;..\api_lib\win32 + WindowsLocalDebugger + + + path=%path%;..\api_lib\x64 + WindowsLocalDebugger + + + path=%path%;..\api_lib\x64 + WindowsLocalDebugger + + \ No newline at end of file diff --git a/vs2010_localbus/vs2010_localbus.cpp b/vs2010_localbus/vs2010_localbus.cpp new file mode 100644 index 0000000..82dd2b6 --- /dev/null +++ b/vs2010_localbus/vs2010_localbus.cpp @@ -0,0 +1,48 @@ +// vs2010_axi_bus.cpp : 定义控制台应用程序的入口点。 +// + +#include "stdafx.h" +#include "xjtag.h" +#include "windows.h" + +unsigned long hif; +DWORD frqReq =10000000; //10MHz + +#define LED_ON 0xFFFFFFFF +#define LED_OFF 0x00000000 + +int _tmain(int argc, _TCHAR* argv[]) +{ + int re =0; + + int err =0; + + unsigned int rdata =0; + char sel =0; + + re =xbus_axi_open(&hif,0,&sel,&err); + + if(re!=1) printf("open failed!\n"); + + re =xbus_init(hif,frqReq,0,2,&err); + + if(re!=1) printf("init failed!\n"); + + while(1) + { + Sleep(500); + + re =xbus_local_write(hif,0x00000001,LED_ON,0x0F); + + Sleep(500); + + re =xbus_local_write(hif,0x00000001,LED_OFF,0x0F); + + re =xbus_local_read(hif, 0x00000002,&rdata); + + printf("rdata=%08x\n",rdata); + } + + return 0; +} + diff --git a/vs2010_localbus/vs2010_localbus.sdf b/vs2010_localbus/vs2010_localbus.sdf new file mode 100644 index 0000000..0a58bed Binary files /dev/null and b/vs2010_localbus/vs2010_localbus.sdf differ diff --git a/vs2010_localbus/vs2010_localbus.sln b/vs2010_localbus/vs2010_localbus.sln new file mode 100644 index 0000000..8bd393a --- /dev/null +++ b/vs2010_localbus/vs2010_localbus.sln @@ -0,0 +1,26 @@ +锘 +Microsoft Visual Studio Solution File, Format Version 11.00 +# Visual Studio 2010 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "vs2010_localbus", "vs2010_axi_bus.vcxproj", "{40428B15-0FA8-4508-9B16-AFAD7A0A8610}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Debug|x64 = Debug|x64 + Release|Win32 = Release|Win32 + Release|x64 = Release|x64 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Debug|Win32.ActiveCfg = Debug|Win32 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Debug|Win32.Build.0 = Debug|Win32 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Debug|x64.ActiveCfg = Debug|x64 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Debug|x64.Build.0 = Debug|x64 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Release|Win32.ActiveCfg = Release|Win32 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Release|Win32.Build.0 = Release|Win32 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Release|x64.ActiveCfg = Release|x64 + {40428B15-0FA8-4508-9B16-AFAD7A0A8610}.Release|x64.Build.0 = Release|x64 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/vs2010_localbus/vs2010_localbus.suo b/vs2010_localbus/vs2010_localbus.suo new file mode 100644 index 0000000..afb08bb Binary files /dev/null and b/vs2010_localbus/vs2010_localbus.suo differ diff --git a/vs2010_localbus/x64/Debug/CL.read.1.tlog b/vs2010_localbus/x64/Debug/CL.read.1.tlog new file mode 100644 index 0000000..6a71600 Binary files /dev/null and b/vs2010_localbus/x64/Debug/CL.read.1.tlog differ diff --git a/vs2010_localbus/x64/Debug/CL.write.1.tlog b/vs2010_localbus/x64/Debug/CL.write.1.tlog new file mode 100644 index 0000000..d36d06b Binary files /dev/null and b/vs2010_localbus/x64/Debug/CL.write.1.tlog differ diff --git a/vs2010_localbus/x64/Debug/cl.command.1.tlog b/vs2010_localbus/x64/Debug/cl.command.1.tlog new file mode 100644 index 0000000..af40e17 Binary files /dev/null and b/vs2010_localbus/x64/Debug/cl.command.1.tlog differ diff --git a/vs2010_localbus/x64/Debug/link.command.1.tlog b/vs2010_localbus/x64/Debug/link.command.1.tlog new file mode 100644 index 0000000..2a45e8b Binary files /dev/null and b/vs2010_localbus/x64/Debug/link.command.1.tlog differ diff --git a/vs2010_localbus/x64/Debug/link.read.1.tlog b/vs2010_localbus/x64/Debug/link.read.1.tlog new file mode 100644 index 0000000..fdb6d59 Binary files /dev/null and b/vs2010_localbus/x64/Debug/link.read.1.tlog differ diff --git a/vs2010_localbus/x64/Debug/link.write.1.tlog b/vs2010_localbus/x64/Debug/link.write.1.tlog new file mode 100644 index 0000000..245b56f Binary files /dev/null and b/vs2010_localbus/x64/Debug/link.write.1.tlog differ diff --git a/vs2010_localbus/x64/Debug/mt.command.1.tlog b/vs2010_localbus/x64/Debug/mt.command.1.tlog new file mode 100644 index 0000000..15da0a0 Binary files /dev/null and b/vs2010_localbus/x64/Debug/mt.command.1.tlog differ diff --git a/vs2010_localbus/x64/Debug/mt.read.1.tlog b/vs2010_localbus/x64/Debug/mt.read.1.tlog new file mode 100644 index 0000000..3bef484 Binary files /dev/null and b/vs2010_localbus/x64/Debug/mt.read.1.tlog differ diff --git a/vs2010_localbus/x64/Debug/mt.write.1.tlog b/vs2010_localbus/x64/Debug/mt.write.1.tlog new file mode 100644 index 0000000..c174a71 Binary files /dev/null and b/vs2010_localbus/x64/Debug/mt.write.1.tlog differ diff --git a/vs2010_localbus/x64/Debug/stdafx.obj b/vs2010_localbus/x64/Debug/stdafx.obj new file mode 100644 index 0000000..3f0475e Binary files /dev/null and b/vs2010_localbus/x64/Debug/stdafx.obj differ diff --git a/vs2010_localbus/x64/Debug/vc100.idb b/vs2010_localbus/x64/Debug/vc100.idb new file mode 100644 index 0000000..2a69f35 Binary files /dev/null and b/vs2010_localbus/x64/Debug/vc100.idb differ diff --git a/vs2010_localbus/x64/Debug/vc100.pdb b/vs2010_localbus/x64/Debug/vc100.pdb new file mode 100644 index 0000000..d01433b Binary files /dev/null and b/vs2010_localbus/x64/Debug/vc100.pdb differ diff --git a/vs2010_localbus/x64/Debug/vs2010_axi_bus.log b/vs2010_localbus/x64/Debug/vs2010_axi_bus.log new file mode 100644 index 0000000..d59f25b --- /dev/null +++ b/vs2010_localbus/x64/Debug/vs2010_axi_bus.log @@ -0,0 +1,25 @@ +锘緽uild started 2021\4\18 鏄熸湡鏃 21:54:52. + 1>Project "G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\vs2010_axi_bus.vcxproj" on node 2 (rebuild target(s)). + 1>_PrepareForClean: + Deleting file "x64\Debug\vs2010_localbus.lastbuildstate". + InitializeBuildStatus: + Creating "x64\Debug\vs2010_localbus.unsuccessfulbuild" because "AlwaysCreate" was specified. + ClCompile: + D:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin\x86_amd64\CL.exe /c /I..\api_lib /Zi /nologo /W3 /WX- /Od /D WIN32 /D _DEBUG /D _CONSOLE /D _UNICODE /D UNICODE /Gm /EHsc /RTC1 /MDd /GS /fp:precise /Zc:wchar_t /Zc:forScope /Yc"StdAfx.h" /Fp"x64\Debug\vs2010_localbus.pch" /Fo"x64\Debug\\" /Fd"x64\Debug\vc100.pdb" /Gd /TP /errorReport:prompt stdafx.cpp + stdafx.cpp + D:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin\x86_amd64\CL.exe /c /I..\api_lib /Zi /nologo /W3 /WX- /Od /D WIN32 /D _DEBUG /D _CONSOLE /D _UNICODE /D UNICODE /Gm /EHsc /RTC1 /MDd /GS /fp:precise /Zc:wchar_t /Zc:forScope /Yu"StdAfx.h" /Fp"x64\Debug\vs2010_localbus.pch" /Fo"x64\Debug\\" /Fd"x64\Debug\vc100.pdb" /Gd /TP /errorReport:prompt vs2010_localbus.cpp + vs2010_localbus.cpp + Link: + D:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\bin\x86_amd64\link.exe /ERRORREPORT:PROMPT /OUT:"G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\vs2010_localbus.exe" /INCREMENTAL:NO /NOLOGO /LIBPATH:..\api_lib\x64 xjtag.lib /MANIFEST /ManifestFile:"x64\Debug\vs2010_localbus.exe.intermediate.manifest" /MANIFESTUAC:"level='asInvoker' uiAccess='false'" /DEBUG /PDB:"G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\vs2010_localbus.pdb" /SUBSYSTEM:CONSOLE /TLBID:1 /DYNAMICBASE /NXCOMPAT /IMPLIB:"G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\vs2010_localbus.lib" /MACHINE:X64 x64\Debug\stdafx.obj + x64\Debug\vs2010_localbus.obj + vs2010_axi_bus.vcxproj -> G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\vs2010_localbus.exe + Manifest: + C:\Program Files (x86)\Microsoft SDKs\Windows\v7.0A\bin\mt.exe /nologo /verbose /outputresource:"G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\vs2010_localbus.exe;#1" /manifest x64\Debug\vs2010_localbus.exe.intermediate.manifest + FinalizeBuildStatus: + Deleting file "x64\Debug\vs2010_localbus.unsuccessfulbuild". + Touching "x64\Debug\vs2010_localbus.lastbuildstate". + 1>Done Building Project "G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\vs2010_axi_bus.vcxproj" (rebuild target(s)). + +Build succeeded. + +Time Elapsed 00:00:06.97 diff --git a/vs2010_localbus/x64/Debug/vs2010_localbus.Build.CppClean.log b/vs2010_localbus/x64/Debug/vs2010_localbus.Build.CppClean.log new file mode 100644 index 0000000..bd6480e --- /dev/null +++ b/vs2010_localbus/x64/Debug/vs2010_localbus.Build.CppClean.log @@ -0,0 +1,19 @@ +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\cl.command.1.tlog +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\CL.read.1.tlog +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\CL.write.1.tlog +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\link.command.1.tlog +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\link.read.1.tlog +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\link.write.1.tlog +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\mt.command.1.tlog +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\mt.read.1.tlog +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\mt.write.1.tlog +G:\XJTAG_SDK_V1.0\XJTAG_SDK_DEMO\VS2010_LOCALBUS\X64\DEBUG\STDAFX.OBJ +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\vc100.idb +G:\XJTAG_SDK_V1.0\XJTAG_SDK_DEMO\VS2010_LOCALBUS\X64\DEBUG\VC100.PDB +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\vs2010_axi_bus.vcxprojResolveAssemblyReference.cache +G:\XJTAG_SDK_V1.0\XJTAG_SDK_DEMO\VS2010_LOCALBUS\X64\DEBUG\VS2010_LOCALBUS.EXE +G:\XJTAG_SDK_V1.0\XJTAG_SDK_DEMO\VS2010_LOCALBUS\X64\DEBUG\VS2010_LOCALBUS.EXE.INTERMEDIATE.MANIFEST +G:\XJTAG_SDK_V1.0\XJTAG_SDK_DEMO\VS2010_LOCALBUS\X64\DEBUG\VS2010_LOCALBUS.OBJ +G:\XJTAG_SDK_V1.0\XJTAG_SDK_DEMO\VS2010_LOCALBUS\X64\DEBUG\VS2010_LOCALBUS.PCH +G:\XJTAG_SDK_V1.0\XJTAG_SDK_DEMO\VS2010_LOCALBUS\X64\DEBUG\VS2010_LOCALBUS.PDB +G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\x64\Debug\vs2010_localbus.write.1.tlog diff --git a/vs2010_localbus/x64/Debug/vs2010_localbus.exe b/vs2010_localbus/x64/Debug/vs2010_localbus.exe new file mode 100644 index 0000000..596b58a Binary files /dev/null and b/vs2010_localbus/x64/Debug/vs2010_localbus.exe differ diff --git a/vs2010_localbus/x64/Debug/vs2010_localbus.exe.intermediate.manifest b/vs2010_localbus/x64/Debug/vs2010_localbus.exe.intermediate.manifest new file mode 100644 index 0000000..ecea6f7 --- /dev/null +++ b/vs2010_localbus/x64/Debug/vs2010_localbus.exe.intermediate.manifest @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/vs2010_localbus/x64/Debug/vs2010_localbus.lastbuildstate b/vs2010_localbus/x64/Debug/vs2010_localbus.lastbuildstate new file mode 100644 index 0000000..4579263 --- /dev/null +++ b/vs2010_localbus/x64/Debug/vs2010_localbus.lastbuildstate @@ -0,0 +1,2 @@ +#v4.0:v100 +Debug|x64|G:\xjtag_sdk_v1.0\xjtag_sdk_demo\vs2010_localbus\| diff --git a/vs2010_localbus/x64/Debug/vs2010_localbus.obj b/vs2010_localbus/x64/Debug/vs2010_localbus.obj new file mode 100644 index 0000000..9d3125b Binary files /dev/null and b/vs2010_localbus/x64/Debug/vs2010_localbus.obj differ diff --git a/vs2010_localbus/x64/Debug/vs2010_localbus.pch b/vs2010_localbus/x64/Debug/vs2010_localbus.pch new file mode 100644 index 0000000..2a08bc3 Binary files /dev/null and b/vs2010_localbus/x64/Debug/vs2010_localbus.pch differ diff --git a/vs2010_localbus/x64/Debug/vs2010_localbus.pdb b/vs2010_localbus/x64/Debug/vs2010_localbus.pdb new file mode 100644 index 0000000..8ce1f91 Binary files /dev/null and b/vs2010_localbus/x64/Debug/vs2010_localbus.pdb differ diff --git a/vs2010_localbus/x64/Debug/vs2010_localbus.write.1.tlog b/vs2010_localbus/x64/Debug/vs2010_localbus.write.1.tlog new file mode 100644 index 0000000..e69de29 diff --git a/璇存槑涔.pdf b/璇存槑涔.pdf new file mode 100644 index 0000000..13e1bec Binary files /dev/null and b/璇存槑涔.pdf differ