31 lines
434 B
Verilog
31 lines
434 B
Verilog
module xjtag_bus #
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(
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parameter JTAG_SEL =3
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)
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(
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clk,
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rst,
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localbus_waddr,
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localbus_wdata,
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localbus_wmask,
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localbus_raddr,
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localbus_rdata,
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localbus_wvalid,
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localbus_rvalid
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);
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input clk;
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input rst;
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output [31:0] localbus_waddr;
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output [31:0] localbus_wdata;
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output [3:0] localbus_wmask;
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output [31:0] localbus_raddr;
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input [31:0] localbus_rdata;
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output localbus_wvalid;
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output localbus_rvalid;
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endmodule
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